OpenPDK Production Value and Benchmark Results

Size: px
Start display at page:

Download "OpenPDK Production Value and Benchmark Results"

Transcription

1 OpenPDK Production Value and Benchmark Results Philippe MAGARSHACK Executive Vice-President, Design Enablement and Services June 2 nd, 2014

2 ST s Strong technology portfolio : Several R&D Partnerships & Manufacturing 2 nd Sources Advanced CMOS FD-SOI MEMS 2 envm Power & Discrete CMOS Image Sensor BiCMOS & Photonics Analog Mixed Signal RF SOI BCD

3 Target of OpenPDK Coalition 3 OpenPDK Coalition Introduction The OpenPDK Coalition was founded in mid-2010 with the goal of defining a set of open standards to allow an OpenPDK to be a created set of once open and then standards translated into allow specific an EDA vendor tools and specific foundry formats. OpenPDK to be created once and then translated into specific EDA vendor tools and specific foundry formats. This will allow an OpenPDK to be as portable across foundries and as agnostic to EDA tools as possible. Let s Start with PDK Inputs format Open Process Specification The Si2 OpenPDK standard will enable greater efficiency in PDK development, verification, and delivery.

4 WHAT IS OPS? 4 Open Process Specification (OPS) is a standardized format for exchanging all data needed to generate a complete PDK. Supplier DRM DB Layer List Device Specifications XSL parser script Exchange (standardized) OPS.xml <Process> <Libraries> <Devices> <Layers> <Rules> < > OPS.xsd parser This is the SI2 OPS standard parser parser parser parser Customer PDK DRC LVS Library PEX

5 First edrm & PDK automation (DRC, pcell, QAcell) 40/45nm October 2009 XML edrm program start March rst phase spec frozen June rst IBM & ST discussion about edrm solution 32/28nm August 2010 SI2 OPS Working Group Creation October 2010 ST Contribution : first OPS UML description OPS History March & October 2011 ST Contribution : 1 st & 2 nd OPS.xsd + «demo DRM 45nm 1.0» June 2011 DAC 1 st ST Results with OPS : «Dev. Lib generation from OPS» 20nm June 2012 SI2 DAC Demo : DRM-> XML-> OpenDFM (DRC) -> CDN/SNPS/MGC DRC > Layout Viewer 40nm August 2012 ST Contribution : «Updated demo DRM 45nm» (extended to address Multi Patterning / Local Interconnect Layers & specific rules / 3D Space) Since August 2012 used by ST to generate 20nm/14FDSOI/SI-Photonics PDK Device Library & Techfile November 2012 OPS.XSD 1.0 (semantic of the XML file) Since Q used by ST to generate 3D IC PDK Addons June 2013 DAC Demo : Rule subset from ST Demo DRM 45nm translation into OpenDFM deck November 2013 OPS.XSD 1.1 with ST Contribution : «demo DRM 45nm 1.6» Q1 & Q OPS Proof of concept Scripts : Automatic Translation OPS opendfm & OPS OpenAccess Techfile June 2014 DAC Demo & Presentation : Full ST «Demo DRM 45nm» translation into OpenDFM deck OPS translation into OpenAccess Techfile Q OPS.XSD 1.2 with ST Contribution : «Updated demo DRM 45nm» 5 ST only

6 Open-PDK Value for ST 6 Self-consistent electronic DRM document to generate automatically the PDK Foundries Inputs <<<< DB OPS.XML PDK EDA Tools Standard needed to drive techno alliance & to manage multiple foundry partnership. Several Supplier Formats d i t a FM Other DB r t f OPS.XML Only one Flow PDK OPDK Working Groups motto: Write once, use many, (test forever)! EDA Tools A EDA Tools B OPS.XML PDK for Tool A PDK for Tool B

7 ST Device Library & Techfile 1/2 OPDK Device Library definition Device List : 30 Active (MOS, BIP) + 20 Passive (Res, Capa) CDF : parameters description Callback procedures (range value, parameters checks, equations based, ) Symbol view with display information (pins, params, name) Tools Interfaces : simulation & netlisting stop views. Techfile (Layers, functions, Vias, Constraints) + layer map table + Display info. No Layout Pcell 7 OLG : OpenLibGen ST Tool that creates the OPDK Device Library from OPS.xml. OPS towards Device Library Benchmark Results Manual Generation ex: 45GS, exotic techno, OPS OLG First Library Generation (50 Devices) 4 m.w (Dev + Validation) 1 or 2 DKs per year 1.5 m.w (Dev + Validation) 1 or 2 DKs per year Lib N to Lib N+1 Average Update 1 m.w (4 Days + 1 Validation Day) per DK release (around 120 per year) = 120 m.w 0 m.w (2 hours & correct by construction) per DK release (around 120 per year) = 6 m.w + Automatic Documentation Generation + Quality Improvement + Automatic Documentation Generation Contents New Lib from scratch with a set of 50 devices (Mos, Res, Cap, Bip, ) 15 param per devices + associated callbacks Minimal OA Techfile Generation No Pcell One new device One new param per device One param Value updated per device One new LPP (Layer Purpose Pair) One constraint updated No Pcell update

8 ST Device Library & Techfile 2/2 8 Deployed at Production level in ST PDKs 20nm (2011)/ 14nm FD-SOI (2013) Silicon Photonics (SP) (2012) 3D IC Flow (SP + CMOS Sensor) (2013) Next in PDKs Roadmap 28nm FD-SOI PDKs (Q3 2014) RF, mmw, HV, Imager, etc Techno Nodes at 130nm from Q3/Q4 2014

9 ST Physical Verification 9 OPS to DRC With OPS & SI2 scripts, OPS Translation into a DRC deck is possible DRC format is opendfm Current Generation & Validation Flow edrm Translation Manual Generation DRC deck For Tool A DRC deck For Tool C DRC deck For Tool B Validation Validation Report on Tool C Validation Report on Tool C Comparison Comparison OPS SI2 OPS2openDFM Automatic Script opendfm Validation Validation Report on Tool A OPS replacing edrm Benefits: Time To market opendfm Automatic generation from new edrm format one opendfm Deck fits all DRC EDA Tools Quality Increase Correct by construction DRC Deck Less duplication in validating multi-deck approach.

10 ST Physical Verification 10 Deployment Status in ST PDKs 2012 Benchmark result with OpenDFM 1.0: 60% of Silicon Photonics Rules covered by opendfm Templates Towards complete Adoption by ST : opendfm 1.1 (# rule templates increase) : 2013 OPS 1.2 standard (Full coverage of DRM rule family (20nm)) : Q Automation Script (SI2 OPS-to-openDFM) : Q Next : EDA Vendor Long-Term commitment to opendfm Continued EDA Vendors (SNPS, CDNC, MGC) support will enable simultaneous up-to-date DRC Support by all vendors Roadmap: opendfm Support in ST PDKs at Production Level 28nm FD-SOI (Q3 2014) 14nm FD-SOI (Q4 2014) Silicon Photonics (SP) (Q3 2014)

11 ST Physical Verif : Next 11 OPS to Automated DRC QA pass/fail tests Manual Generation Current ST Internal Automation OPS & EDA Vendors Solution QA pass/fail tests generation 1x 10x 20x No Tooling maintenance DRC vs DRM consistency need to be correct by construction. DRM and other PDK inputs cross-checks DRM vs Design rules check Target : 90%-100% Coverage No existing neither automation nor tooling for verifying DRC decks Need now SI2 & EDA Vendor involvement. Target : from OPS to DRC towards DRC QA Regression 14/28nm FD-SOI (Q4 2014) Silicon Photonics (SP) (Q3 2014)

12 OpenPDK/OPS Next Step : PCells 12 Problems OpenPCell Addresses More productive programming effort Write once Pcell and Callback code Multi flow support Ease of integration into a PDK Assure high quality Expected Results are : Pcell generation productivity ++ Pcell quality enhancement One Spec Several Pcells code No flow supporting multiple language Fully supports SI2 OpenPcell Initiative Strong Link with OPS seen as added value Looking for Build-In Validation Concept

13 ST Next Steps 13 SI2 OpenPDK Project has already delivered several specifications: Device Symbols, Param, Callbacks & Tools Interface ESD, Open Process Spec & Universal Layer Model Others Specs about to be released for Pcells or OPS updates Proof of concept & Scripts are now also available. They will be demonstrated during this DAC at SI2 Booth. OpenPcell & opendfm Last Spec Benchmark to be done Automatic Techfile Constraints generation. Working with EDA Vendors to find a production solution

14 ST strongly supports PDK Standardization : Best Time-to-market PDK for IP-design flow Best PDK Development efficiency, quality Universal data store for design information (OA) Conclusion 14 EDA Vendors adoption of OPS is now a must-have to deploy across Industry within ST foundry offer. With above action plan for OPS Proliferation ST willingness to being more involve in Open3D & Silicon Photonics TABs ST already uses OPDK in production advanced & legacy technology PDKs.

15 THANK YOU

16 Back-Up Slides 10/06/2014

17 SI2 Presentation 17 Silicon Integration Initiative Organization of industry-leading companies in the semiconductor, electronic systems and EDA tool industries. Focused on improving productivity and reducing cost in creating and producing integrated silicon systems. Through collaborative efforts, the industry can achieve higher levels of systems-onsilicon integration while reducing the cost and complexity of integrating future design systems. Several Coalition initiated through SI2 Open Access Coalition OpenPDK Coalition Design For Manufacturability Coalition Compact Model Coalition Open3D TAB Silcon Photonics (SP) TAB Low Power Coalition

18 SI2 DFM Coalition 18 the Design for Manufacturability Coalition (DFMC) has developed a standard interface format that describes a comprehensive set of DFM parameters that can verify that a circuit will meet it s profit targets. The DFM parameters are defined in an open-source and extensible standard format called OpenDFM which provides a common set of DFM parameters to a wide variety of physical verification and analysis tools dramatically improving the interface between EDA vendors and silicon foundries. DFM Coalition Board DFMC Technical Steering Group (TSG) Compatibility Working Group opendfm Targetting Working Group OPEX Working Group LVS Not addressed today

19 SI2 OPDK Coalition 19 OpenPDK Coalition Board Chair: Jim Culp, IBM OpenPDK Technical Steering Group (TSG) Chair : Gilles Namur, ST ESD Open Process Specification (OPS) Symbols, Callbacks & Parameters (SCP) Pcell XML Packaging Pcell Common Language Grammar Unified Layer Model (Jointly with DFMC) OPS to OA TechDB OPS to DRC OpenPDK Working Groups

20 PDK Development Flow Ecosystem 20 Foundry 2 Foundry 1 Foundry 3 Set of PDK Inputs: DRM & Device Spec (Format B) Set of PDK Inputs: DRM & Device Spec (Format A) Set of PDK Inputs: DRM & Device Spec (Format C) PDK Development Team Device Library Spices LVS DRC PEX Customer A Design & Validation With Tool Suite A Customer B Design & Validation With Tool Suite B Customer C Design & Validation With Tool Suite C Several PDK Input formats Several PDK Generation flows Several EDA Tools for the same feature to be supported

21 Why OPS? 21 ST was looking for a smarter & more complete electronic PDK input format because lots of data were missing or were not easy to be extracted in traditionnal edrm. Open Process Specification New Format : Allow Automation for PDK generation. Eases EDA Vendor sync. with foundries Inputs. Foundries Inputs DB OPS.xml <Process> <Libraries> <Devices> <Layers> <Rules> < > PDK EDA Tools OpenPDK At STMicroelectronics

22 Why OPS as a standard? 22 ST wanted to have this format defined as a standard and used across the industry because what ever is the format of the Database used by the supplier to manage the PDK inputs : The PDK generation flow remains the same. FM Supplier Other DB OPS.xml <Process> <Libraries> <Devices> <Layers> <Rules> < > Only one Flow d i t a r t f DRC PDK PEX LVS Library OpenPDK At STMicroelectronics

23 ST was looking for an efficient way to generated several PDKs in parallel without a huge over cost. OPS is an answer to this issue. Once OPS is complete enough to produce a PDK : Why OPS? 23 You can produce any kind of PDK. DRC PDK for Tool A PEX EDA Tools A EDA Tools B OPS.xml <Process> <Libraries> <Devices> <Layers> <Rules> < > LVS DRC Library PDK for Tool B PEX Even better, with the help of EDA Vendors : OPS could become a techfile LVS Library OpenPDK At STMicroelectronics

24 A concrete OPS example 24 ST is ready to produce their own edrm in OPS format. OPS.xml <Process> <Libraries> <Devices> <Layers> <Rules> < > < > OPS.xsd All along the process of definition of OPS, ST has contributed with several DRM examples : demo DRM 45nm. The examples contain a complete DRM.pdf and its associated OPS.xml file aligned with the OPS.xsd defined by SI2 OPDKC OPS WG (available on SI2 website)

25 OPS.xml <Process> <Libraries> <Devices> <Layers> <Rules> < > < > OPS : Automation for DRC & Techfile Constraints GroundRuler 25 Techfile Coder DRC Coder Enriched OPS.xml <Process> <Libraries> <Devices> <Layers> <Rules> < Templates > < > < > New Template In-House Template DB Reference to DRM DB OPS Enriched OPS Reference to New Template opendfm Template DB New Template Generator In-House Template DB Techfile Code DRC Code New Template

26 OPS to DRC Generation 26 OpenDFM File OPS XML The Target Calibre, PVS or ICV Runsets

27 OPS to DRC Generation 27 The Result : SI2 propose a script that automatically generate an opendfm Deck from an OPS.XML file The full set of rules of the demo DRM 45nm provided by ST has been converted in opendfm through this script Next Steps ST will benchmark this tool on a real technology : OPS.xml extracted from a real DRM opendfm Execution of the opendfm deck on DRC Regression Test cases Comparison with hand made DRC deck results on the same testcases.

28 OPS : Automation for Techfile Generation 28 OPS XML file <Process> <Libraries> <Devices> <Layers> <Rules> < > < > The Target Techfile All Layers Design Layers Derived Layers Via Definitions Physical Constraints Tool Directives

29 OPS To Techfile Generation 29 The Result : SI2 propose a script that automatically generate an OA techdb (openaccess techfile) with all the info relative to the layers ST current usage of OPS Coverage Layers Display GDS (Layer map side file) ST already has its own flow using OPS as input file to generate part of the techfile in some technos. Next Steps : Extend the automatic techfile generation with the process constraints through templates as decribed in previous slides. Extend the coverage of technos using this kind of automation. The Bi-Directional Translation allows to create an OPS file from an existing OA DB. Very Helpful for OPS Adoption

30 OPS : Automation for PDK device Library PDK Device Library generation push button flow from an OPS.xml as input. 30 Ref Symbols Library OPS.xsd Pcells Library OPS XML file <Process> <Libraries> <Devices> <Layers> <Rules> < > < > OpenLibGen is an ST Internal API & Tools. ST already has its own flow using OPS as input file to generate part of the techfile in some technos. Next Steps : Extend the automatic techfile generation with the process constraints through templates as described in previous slides. Extend the coverage of technos using this kind of automation. Parameter Setup File.. Callbacks Directory Spiltted Techfile Directory >

31 OPS : Automation for PDK documentation Device Library Documentation for End-User. 31 OPS.xsd OPS XML file <Process> <Libraries> <Devices> <Layers> <Rules> < > < > OpenLibGen is an ST Internal API & Tools. ST already has its own flow using OPS as input file to generate part of the techfile in some technos. Next Steps : Extend the doc template to enhance the full device Library documentation Device Lib Documentation Template (Word) Device Lib Documentation (Word) OPS Introduction

32 Open Pcells 32 Process Inputs Process Constraints Layer Definitions Devices PDK Spec Capture Tool OPS XML file <Process> <Libraries> <Devices> <Layers> <Rules> < > PDK Generation Tool PyCell Plugin TCL Plugin Custom Designer PDK Pyxis PDK PDK Testing Tool Models Vias Code Repository SKILL Python CLG SKILL Plugin Virtuoso PDK OPS with its PCells XML Repository solution is language agnostic and with the use of translators, the data can be adopted to any companies proprietary solution. OPS Introduction

33 OPS Introduction

Open Process Spec Adoption: a Case Study

Open Process Spec Adoption: a Case Study Open Process Spec Adoption: a Case Study June 3 rd, 2014 AGENDA 2 OpenPDK & OPS Introduction What does OPS looks like? Let s do an openpdk with OPS Target of OpenPDK Coalition 3 a set of open standards

More information

OpenPDK Coalition. Open Process Specification Working Group Status

OpenPDK Coalition. Open Process Specification Working Group Status OpenPDK Coalition Open Process Specification Working Group Status Gilles NAMUR OPDKC TSG Chair June 6 th, 2011 PDK Development Flow Ecosystem Foundry 2 Foundry 1 Foundry 3 Set of PDK Inputs: DRM & Device

More information

PDK Automation An IBM Perspective

PDK Automation An IBM Perspective PDK utomation n IBM Perspective Matthew Graf, OPDKC James Culp, ODFMC Si2 Con Oct. 20 th, 2011 IBM s PDK Development History Timeline 1998 2009 OpenPDK OpenDFM Chip Design groups develop their own PDK

More information

IPL Workshop Luncheon DAC Interoperable PDK Libraries: The Proof is in the Pudding

IPL Workshop Luncheon DAC Interoperable PDK Libraries: The Proof is in the Pudding IPL Workshop Luncheon DAC 2008 Interoperable PDK Libraries: The Proof is in the Pudding Agenda 12:00 12:20 Complimentary Lunch Buffet 12:20 12:40 Introduction & IPL Overview Ed Lechner, Synopsys 12:40

More information

OpenPDK Symbol, Callbacks and Parameters Working Group

OpenPDK Symbol, Callbacks and Parameters Working Group OpenPDK Symbol, Callbacks and Parameters Working Group Rich Morse Marketing & EDA Alliances Mgr. SpringSoft October 20, 2011 Overview The SCP working group is focused on developing specifications for a

More information

OpenDFM Targeting Functions. Bob Sayah June 6, 2011 IBM Corporation Si2 Targeting Working Group Chair

OpenDFM Targeting Functions. Bob Sayah June 6, 2011 IBM Corporation Si2 Targeting Working Group Chair OpenDFM Targeting Functions Bob Sayah June 6, 2011 IBM Corporation Si2 Targeting Working Group Chair Targeting Design Drawn Shapes Mfg. Targeting Targeting takes the Drawn Shapes provided by the layout

More information

Adding Curves to an Orthogonal World

Adding Curves to an Orthogonal World Adding Curves to an Orthogonal World Extending the EDA Flow to Support Integrated Photonics Paul Double July 2018 Traditional IC Design BREXIT AHOY! Designers & tool developers have lived in a orthogonal

More information

PDK-Based Analog/Mixed-Signal/RF Design Flow 11/17/05

PDK-Based Analog/Mixed-Signal/RF Design Flow 11/17/05 PDK-Based Analog/Mixed-Signal/RF Design Flow 11/17/05 Silvaco s What is a PDK? Which people build, use, and support PDKs? How do analog/mixed-signal/rf engineers use a PDK to design ICs? What is an analog/mixed-signal/rf

More information

Putting Curves in an Orthogonal World

Putting Curves in an Orthogonal World Putting Curves in an Orthogonal World Extending the EDA Flow to Support Integrated Photonics Masahiro Shiina October 2018 Traditional IC Design Designers & tool developers have lived in a orthogonal world

More information

Will Silicon Proof Stay the Only Way to Verify Analog Circuits?

Will Silicon Proof Stay the Only Way to Verify Analog Circuits? Will Silicon Proof Stay the Only Way to Verify Analog Circuits? Pierre Dautriche Jean-Paul Morin Advanced CMOS and analog. Embedded analog Embedded RF 0.5 um 0.18um 65nm 28nm FDSOI 0.25um 0.13um 45nm 1997

More information

Detailed Presentation

Detailed Presentation Detailed Presentation PDK Leadership - Developing and Delivering High Quality PDKs Simucad PDKs are being rapidly adopted worldwide by leading foundries and design houses because of their quality and ease

More information

OpenAccess PCells Ed Petrus VP Engineering V2

OpenAccess PCells Ed Petrus VP Engineering V2 OpenAccess PCells Ed Petrus VP Engineering V2 April 2005 Page 1 Copyright 2005 CiraNova, Inc. What is CiraNova about? 4 CiraNova enables analog designers to create migratable, re-usable analog objects

More information

2011 OpenDFM Overview: A Customer Perspective. Fred Valente Distinguished Member Technical Staff Texas Instruments Incorporated

2011 OpenDFM Overview: A Customer Perspective. Fred Valente Distinguished Member Technical Staff Texas Instruments Incorporated 2011 OpenDFM Overview: A Customer Perspective Fred Valente Distinguished Member Technical Staff Texas Instruments Incorporated 1 Key Players Texas Instruments Fred Valente Lisa Fisher Si2 -- Jake Buurma

More information

Concurrent, OA-based Mixed-signal Implementation

Concurrent, OA-based Mixed-signal Implementation Concurrent, OA-based Mixed-signal Implementation Mladen Nizic Eng. Director, Mixed-signal Solution 2011, Cadence Design Systems, Inc. All rights reserved worldwide. Mixed-Signal Design Challenges Traditional

More information

Expert Layout Editor. Technical Description

Expert Layout Editor. Technical Description Expert Layout Editor Technical Description Agenda Expert Layout Editor Overview General Layout Editing Features Technology File Setup Multi-user Project Library Setup Advanced Programmable Features Schematic

More information

Synopsys Design Platform

Synopsys Design Platform Synopsys Design Platform Silicon Proven for FDSOI Swami Venkat, Senior Director, Marketing, Design Group September 26, 2017 2017 Synopsys, Inc. 1 Synopsys: Silicon to Software Software Application security

More information

Laker and Calibre RealTime, an OA Integration Success Story

Laker and Calibre RealTime, an OA Integration Success Story Silicon Integration Initiative Laker and Calibre RealTime, an OA Integration Success Story Rich Morse, Marketing & EDA Alliances Manager, SpringSoft Anant Adke, Director of Engineering, Design to Silicon

More information

DRVerify: The Verification of Physical Verification

DRVerify: The Verification of Physical Verification DRVerify: The Verification of Physical Verification Sage Design Automation, Inc. Santa Clara, California, USA Who checks the checker? DRC (design rule check) is the most fundamental physical verification

More information

Virtuoso Custom Design Platform GXL. Open Database. PDKs. Constraint Management. Customer IP

Virtuoso Custom Design Platform GXL. Open Database. PDKs. Constraint Management. Customer IP Virtuoso Custom Design Platform GL The Cadence Virtuoso custom design platform is the industry s leading design system for complete front-to-back analog, RF, mixed-signal, and custom digital design. The

More information

OpenAccess based architecture for Neolinear s Rapid Analog Design Flow

OpenAccess based architecture for Neolinear s Rapid Analog Design Flow OpenAccess based architecture for Neolinear s Rapid Analog Design Flow Bogdan Arsintescu, David Cuthbert, Elias Fallon, Matt Phelps Abstract Developing tools for today s analog and mixed-signal design

More information

Design software and services for the integrated photonics market IPKISS Moves the edges in PIC PDK building

Design software and services for the integrated photonics market IPKISS Moves the edges in PIC PDK building Design software and services for the integrated photonics market IPKISS 3.1.3 Moves the edges in PIC PDK building take controltake of your control photonics of your photonics design flow design flow 1

More information

Silicon Photonics Scalable Design Framework:

Silicon Photonics Scalable Design Framework: Silicon Photonics Scalable Design Framework: From Design Concept to Physical Verification Hossam Sarhan Technical Marketing Engineer hossam_sarhan@mentor.com Objective: Scalable Photonics Design Infrastructure

More information

Virtuoso - Enabled EPDA framework AIM SUNY Process

Virtuoso - Enabled EPDA framework AIM SUNY Process Virtuoso - Enabled EPDA framework AIM SUNY Process CADENCE, LUMERICAL, PHOENIX SOFTWARE Driven by our customers Cadence is the leader with Virtuoso custom design platform for electronics custom and mixed

More information

AIM Photonics Silicon Photonics PDK Overview. March 22, 2017 Brett Attaway

AIM Photonics Silicon Photonics PDK Overview. March 22, 2017 Brett Attaway AIM Photonics Silicon Photonics PDK Overview March 22, 2017 Brett Attaway Silicon Photonics Process Design Kits (PDK) PDK 3 technologies, 2 major releases/year Full (active)- v1.0 available now Passive-

More information

Collaborate to Innovate FinFET Design Ecosystem Challenges and Solutions

Collaborate to Innovate FinFET Design Ecosystem Challenges and Solutions 2013 TSMC, Ltd Collaborate to Innovate FinFET Design Ecosystem Challenges and Solutions 2 Agenda Lifestyle Trends Drive Product Requirements Concurrent Technology and Design Development FinFET Design Challenges

More information

Virtuoso Layout Suite XL

Virtuoso Layout Suite XL Accelerated full custom IC layout Part of the Cadence Virtuoso Layout Suite family of products, is a connectivity- and constraint-driven layout environment built on common design intent. It supports custom

More information

Design Solutions in Foundry Environment. by Michael Rubin Agilent Technologies

Design Solutions in Foundry Environment. by Michael Rubin Agilent Technologies Design Solutions in Foundry Environment by Michael Rubin Agilent Technologies Presenter: Michael Rubin RFIC Engineer, R&D, Agilent Technologies former EDA Engineering Manager Agilent assignee at Chartered

More information

Soitec ultra-thin SOI substrates enabling FD-SOI technology. July, 2015

Soitec ultra-thin SOI substrates enabling FD-SOI technology. July, 2015 Soitec ultra-thin SOI substrates enabling FD-SOI technology July, 2015 Agenda FD-SOI: Background & Value Proposition C1- Restricted July 8, 2015 2 Today Ultra-mobile & Connected Consumer At Any Time With

More information

take control of your photonics design flow Photonic-Electronic IC design and implementation Pieter Dumon 27/09/2016

take control of your photonics design flow Photonic-Electronic IC design and implementation Pieter Dumon 27/09/2016 take control of your photonics design flow Photonic-Electronic IC design and implementation Pieter Dumon 27/09/2016 Giving photonic IC designers the same power as electronic IC designers. Make it possible

More information

SystemC Standardization Update Including UVM for SystemC Accellera Systems Initiative SystemC Standards Update. Andy Goodrich, Cadence Design Systems

SystemC Standardization Update Including UVM for SystemC Accellera Systems Initiative SystemC Standards Update. Andy Goodrich, Cadence Design Systems SystemC Standardization Update Including UVM for SystemC Accellera Systems Initiative SystemC Standards Update Andy Goodrich, Cadence Design Systems Presentation Overview Accellera Overview Membership

More information

O N C A D E N C E V I R T U O S O. CHEN, Jason Application Engineer, Keysight Technologies

O N C A D E N C E V I R T U O S O. CHEN, Jason Application Engineer, Keysight Technologies O N C A D E N C E V I R T U O S O CHEN, Jason 2018.05.08 Application Engineer, Keysight Technologies Introduction to Momentum Momentum Features for RFIC Design Circuit/EM Cosimulation Flow on Cadence Virtuoso

More information

GF14LPP-XL AMS Reference Flow for FINFET Technology. Rajashekhar Chimmalagi Design Methodology April 5 th 2016

GF14LPP-XL AMS Reference Flow for FINFET Technology. Rajashekhar Chimmalagi Design Methodology April 5 th 2016 GF14LPP-XL AMS Reference Flow for FINFET Technology Rajashekhar Chimmalagi Design Methodology April 5 th 2016 Agenda 1 FinFET & FinFET Challenges 2 GF Reference Flows 3 Ref Flow Design 4 Ref Flow Modules

More information

CircuitsMulti-Projets

CircuitsMulti-Projets From layout to chips CircuitsMulti-Projets MPW Services Center for ICs, Photonics & MEMS Prototyping & Low Volume Production mycmp.fr Grenoble - France From layout to chips STMicroelectronics Standard

More information

BOOST YOUR DESIGNS TO A NEW LEVEL OF ACCURACY AND CONFIDENCE WITH VERILOG-A

BOOST YOUR DESIGNS TO A NEW LEVEL OF ACCURACY AND CONFIDENCE WITH VERILOG-A BOOST YOUR DESIGNS TO A NEW LEVEL OF ACCURACY AND CONFIDENCE WITH VERILOG-A NICOLAS WILLIAMS, PRODUCT MARKETING MANAGER, MENTOR GRAPHICS JEFF MILLER, PRODUCT MARKETING MANAGER, MENTOR GRAPHICS A M S D

More information

Photonics Integration in Si P Platform May 27 th Fiber to the Chip

Photonics Integration in Si P Platform May 27 th Fiber to the Chip Photonics Integration in Si P Platform May 27 th 2014 Fiber to the Chip Overview Introduction & Goal of Silicon Photonics Silicon Photonics Technology Wafer Level Optical Test Integration with Electronics

More information

DFT-3D: What it means to Design For 3DIC Test? Sanjiv Taneja Vice President, R&D Silicon Realization Group

DFT-3D: What it means to Design For 3DIC Test? Sanjiv Taneja Vice President, R&D Silicon Realization Group I N V E N T I V E DFT-3D: What it means to Design For 3DIC Test? Sanjiv Taneja Vice President, R&D Silicon Realization Group Moore s Law & More : Tall And Thin More than Moore: Diversification Moore s

More information

FinFET Technology Understanding and Productizing a New Transistor A joint whitepaper from TSMC and Synopsys

FinFET Technology Understanding and Productizing a New Transistor A joint whitepaper from TSMC and Synopsys White Paper FinFET Technology Understanding and Productizing a New Transistor A joint whitepaper from TSMC and Synopsys April, 2013 Authors Andy Biddle Galaxy Platform Marketing, Synopsys Inc. Jason S.T.

More information

Joe Civello ADS Product Manager/ Keysight EEsof EDA

Joe Civello ADS Product Manager/ Keysight EEsof EDA Joe Civello 2018.01.11 ADS Product Manager/ Keysight EEsof EDA 3D Layout Viewing directly from the Layout Window 3D Editing & Routing PCB & IC/Module Design Dramatically Improved Visual Inspection Simplified

More information

Technology & Manufacturing. Laurent Bosson Executive Vice President Front End Technology & Manufacturing

Technology & Manufacturing. Laurent Bosson Executive Vice President Front End Technology & Manufacturing Technology & Manufacturing Laurent Bosson Executive Vice President Front End Technology & Manufacturing Manufacturing and Technology Strategy LEADING EDGE TECHNOLOGY + SHAREHOLDER VALUE TIME TO MARKET

More information

Circuits Multi Projets

Circuits Multi Projets Circuits Multi Projets MPW Services Center for IC / MEMS Prototyping http://cmp.imag.fr Grenoble France CMP annual users meeting, 4 Feb. 2016, PARIS STMicroelectronics Standard Technology offers at CMP

More information

An Incremental Technology Database Structure for Analog/Mixed-Signal Methodologies

An Incremental Technology Database Structure for Analog/Mixed-Signal Methodologies An Incremental Technology Database Structure for Analog/Mixed-Signal Methodologies Introduction David Kaplan (Cadence Design Systems, Inc.) Sini Mukundan (National Semiconductor, Inc.) OpenAccess plays

More information

Laker Custom Layout Automation System

Laker Custom Layout Automation System The Laker Custom Layout offers powerful solutions for analog, mixed-signal, memory, and custom digital IC design that address key pain points in the layout process. The Laker layout system provides an

More information

How Can Testing Teams Play a Key Role in DevOps Adoption?

How Can Testing Teams Play a Key Role in DevOps Adoption? June 3, 2016 How Can Testing Teams Play a Key Role in DevOps Adoption? Sujay Honnamane QA Director @sujayh Rameshkumar Bar Sr. Automation Architect @rameshbar 2016 Cognizant Session take away DevOps Overview

More information

DATASHEET VIRTUOSO LAYOUT SUITE GXL

DATASHEET VIRTUOSO LAYOUT SUITE GXL DATASHEET Part of the Cadence Virtuoso Layout Suite family of products, is a collection of fully automated layout capabilities such as custom placement and routing, layout optimization, module generation,

More information

Lecture 6. Tutorial on Cadence

Lecture 6. Tutorial on Cadence Lecture 6. Tutorial on Cadence Virtuoso Schematic Editor Jaeha Kim Mixed-Signal IC and System Group (MICS) Seoul National University jaeha@ieee.org Schematic Editor Schematic editor (e.g. Cadence Virtuoso)

More information

Improve Reliability With Accurate Voltage-Aware DRC. Matthew Hogan, Mentor Graphics

Improve Reliability With Accurate Voltage-Aware DRC. Matthew Hogan, Mentor Graphics Improve Reliability With Accurate Voltage-Aware DRC Matthew Hogan, Mentor Graphics BACKGROUND Consumer expectations for longer device operations at sustained performance levels means designing for reliability

More information

AIM Photonics: Manufacturing Challenges for Photonic Integrated Circuits

AIM Photonics: Manufacturing Challenges for Photonic Integrated Circuits AIM Photonics: Manufacturing Challenges for Photonic Integrated Circuits November 16, 2017 Michael Liehr Industry Driving Force EXA FLOP SCALE SYSTEM Blades SiPh Interconnect Network Memory Stack HP HyperX

More information

Imaging, BiCMOS ASIC and Silicon Photonics. Eric Aussedat Executive Vice President General Manager, Imaging, Bi-CMOS ASIC and Silicon Photonics Group

Imaging, BiCMOS ASIC and Silicon Photonics. Eric Aussedat Executive Vice President General Manager, Imaging, Bi-CMOS ASIC and Silicon Photonics Group Imaging, BiCMOS ASIC and Silicon Photonics Eric Aussedat Executive Vice President General Manager, Imaging, Bi-CMOS ASIC and Silicon Photonics Group IBP Leading Position Targets 2 Image Sensors Solutions

More information

SOI REQUIRES BETTER THAN IR-DROP. F. Clément, CTO

SOI REQUIRES BETTER THAN IR-DROP. F. Clément, CTO SOI REQUIRES BETTER THAN IR-DROP F. Clément, CTO Content IR Drop Vs. System-level Interferences CWS Expertise Accuracy and Performance Silicon Validation Conclusion Copyright CWS 2004-2016 2 Sensitive

More information

idrm: Fixing the broken interface between design and manufacturing

idrm: Fixing the broken interface between design and manufacturing idrm: Fixing the broken interface between design and manufacturing Abstract Sage Design Automation, Inc. Santa Clara, California, USA This paper reviews the industry practice of using the design rule manual

More information

PIC design across platforms. Ronald Broeke Bright Photonics

PIC design across platforms. Ronald Broeke Bright Photonics PIC design across platforms Ronald Broeke Bright Photonics OUTLINE Introduction PIC applications & designs MPW Materials & platforms Design modules PICs in Phoxtrot Design House for Photonics ICs Custom

More information

Quality Assured SoC Design Using Crossfire. A Fractal whitepaper

Quality Assured SoC Design Using Crossfire. A Fractal whitepaper Quality Assured SoC Design Using Crossfire A Fractal whitepaper Introduction There is no industry where the need for early bug-detection is more paramount than in SoC design. Consequences like design-re-spins

More information

SysML Past, Present, and Future. J.D. Baker Sparx Systems Ambassador Sparx Systems Pty Ltd

SysML Past, Present, and Future. J.D. Baker Sparx Systems Ambassador Sparx Systems Pty Ltd SysML Past, Present, and Future J.D. Baker Sparx Systems Ambassador Sparx Systems Pty Ltd A Specification Produced by the OMG Process SysML 1.0 SysML 1.1 Etc. RFI optional Issued by Task Forces RFI responses

More information

DATASHEET VIRTUOSO LAYOUT SUITE FAMILY

DATASHEET VIRTUOSO LAYOUT SUITE FAMILY DATASHEET The Cadence Virtuoso Layout Suite family of products delivers a complete solution for front-to-back custom analog, digital, RF, and mixed-signal design. It preserves design intent throughout

More information

NANOIOTECH The Future of Nanotechnologies for IoT & Smart Wearables Semiconductor Technology at the Core of IoT Applications

NANOIOTECH The Future of Nanotechnologies for IoT & Smart Wearables Semiconductor Technology at the Core of IoT Applications NANOIOTECH The Future of Nanotechnologies for IoT & Smart Wearables Semiconductor Technology at the Core of IoT Applications Giorgio Cesana STMicroelectronics Success Factors for new smart connected Applications

More information

Laker 3 Custom Design Tools

Laker 3 Custom Design Tools Datasheet Laker 3 Custom Design Tools Laker 3 Custom Design Tools The Laker 3 Custom Design Tools form a unified front-to-back environment for custom circuit design and layout. They deliver a complete

More information

Process Agnostic Library Migration Automation

Process Agnostic Library Migration Automation Need for Speed: Process Agnostic Library Migration Automation Joseph Murray Lijun Li Outline Motivation Approach PyCell Studio Cadence SKILL Comparison Summary Why Process Agnostic Migration Automation

More information

Designing into a Foundry Low Power High-k Metal Gate 28nm CMOS Solution for High-Performance Analog Mixed Signal and Mobile Applications

Designing into a Foundry Low Power High-k Metal Gate 28nm CMOS Solution for High-Performance Analog Mixed Signal and Mobile Applications Designing into a Foundry Low Power High-k Metal Gate 28nm CMOS Solution for High-Performance Analog Mixed Signal and Mobile Applications A Collaborative White Paper by RAMBUS and GLOBALFOUNDRIES W h i

More information

Model Builder Program (MBP) Complete Silicon Turnkey Device Modeling Software

Model Builder Program (MBP) Complete Silicon Turnkey Device Modeling Software Model Builder Program (MBP) Complete Silicon Turnkey Device Modeling Software Introduction Model Builder Program (MBP) is a complete modeling solution that integrates SPICE simulation, model parameter

More information

AMS DESIGN METHODOLOGY

AMS DESIGN METHODOLOGY OVER VIEW CADENCE ANALOG/ MIXED-SIGNAL DESIGN METHODOLOGY The Cadence Analog/Mixed-Signal (AMS) Design Methodology employs advanced Cadence Virtuoso custom design technologies and leverages silicon-accurate

More information

Keysight Technologies Integrating Multiple Technology Devices onto Laminate-Based Multi-Chip-Modules Using an Integrated Design Flow

Keysight Technologies Integrating Multiple Technology Devices onto Laminate-Based Multi-Chip-Modules Using an Integrated Design Flow Keysight Technologies Integrating Multiple Technology Devices onto Laminate-Based Multi-Chip-Modules Using an Integrated Design Flow Article Reprint This article was first published in Microwave Product

More information

Assessment of the OpenAccess Standard: Insights on the new EDA Industry Standard from Hewlett-Packard, a Beta Partner and Contributing Developer

Assessment of the OpenAccess Standard: Insights on the new EDA Industry Standard from Hewlett-Packard, a Beta Partner and Contributing Developer Assessment of the OpenAccess Standard: Insights on the new EDA Industry Standard from Hewlett-Packard, a Beta Partner and Contributing Developer Terry Blanchard Hewlett-Packard Company terry.blanchard@hp.com

More information

SMASH: a Verilog-A simulator for analog designers

SMASH: a Verilog-A simulator for analog designers SMASH: a Verilog-A simulator for analog designers Gilles DEPEYROT, Frédéric POULLET & Benoît DUMAS DOLPHIN Integration Outline Context & Goals Coding Guidelines Benchmark of Verilog-A vs. SPICE Progress

More information

TSBCD025 High Voltage 0.25 mm BCDMOS

TSBCD025 High Voltage 0.25 mm BCDMOS TSBCD025 High Voltage 0.25 mm BCDMOS TSI Semiconductors' 0.25 mm process is a feature rich platform with best in class CMOS, LDMOS, and BiPolar devices. The BCD technology enables logic, Mixed-Signal,

More information

Virtuoso System Design Platform Unified system-aware platform for IC and package design

Virtuoso System Design Platform Unified system-aware platform for IC and package design Unified system-aware platform for IC and package design The Cadence Virtuoso System Design Platform is a holistic, system-based solution that provides the functionality to drive simulation and LVS-clean

More information

Galaxy Custom Designer LE Custom Layout Editing

Galaxy Custom Designer LE Custom Layout Editing Datasheet Galaxy Custom Designer LE Custom Layout Editing Overview Galaxy Custom Designer LE is the modern-era choice for layout entry and editing, enabling users to meet the challenges of today s fast-moving

More information

CREATIVE CHIPS GmbH. Facts Phone: / Fax: / Internet:

CREATIVE CHIPS GmbH. Facts Phone: / Fax: / Internet: CREATIVE CHIPS GmbH Facts 2014 CREATIVE CHIPS GmbH Im Bubenstueck 1 55411 Bingen at Rhine Germany Phone: +49 6721 / 98722 0 Fax: + 49 6721 / 98722 70 E-Mail: info@creativechips.com Internet: www.creativechips.com

More information

Guidelines for Verilog-A Compact Model Coding

Guidelines for Verilog-A Compact Model Coding Guidelines for Verilog-A Compact Model Coding Gilles DEPEYROT, Frédéric POULLET, Benoît DUMAS DOLPHIN Integration Outline Dolphin EDA Solutions by Dolphin Overview of SMASH Context & Goals Verilog-A for

More information

Process Design Kit for for Flexible Hybrid Electronics (FHE-PDK)

Process Design Kit for for Flexible Hybrid Electronics (FHE-PDK) Process Design Kit for for Flexible Hybrid Electronics (FHE-PDK) Tsung-Ching Jim Huang, PhD Sr. Research Scientist, Hewlett Packard Labs MEPTEC2018 Outline Introduction Modeling and design needs for flexible

More information

An Overview of Standard Cell Based Digital VLSI Design

An Overview of Standard Cell Based Digital VLSI Design An Overview of Standard Cell Based Digital VLSI Design With examples taken from the implementation of the 36-core AsAP1 chip and the 1000-core KiloCore chip Zhiyi Yu, Tinoosh Mohsenin, Aaron Stillmaker,

More information

Dr. Ajoy Bose. SoC Realization Building a Bridge to New Markets and Renewed Growth. Chairman, President & CEO Atrenta Inc.

Dr. Ajoy Bose. SoC Realization Building a Bridge to New Markets and Renewed Growth. Chairman, President & CEO Atrenta Inc. SoC Realization Building a Bridge to New Markets and Renewed Growth Dr. Ajoy Bose Chairman, President & CEO Atrenta Inc. October 20, 2011 2011 Atrenta Inc. SoCs Are Driving Electronic Product Innovation

More information

Enabling An Interconnected Digital World Cadence EDA and IP Update. Jonathan Smith Director, Strategic Alliances June 1, 2017

Enabling An Interconnected Digital World Cadence EDA and IP Update. Jonathan Smith Director, Strategic Alliances June 1, 2017 Enabling An Interconnected Digital World Cadence EDA and IP Update Jonathan Smith Director, Strategic Alliances June 1, 2017 IoT Market Definition and Growth Estimates Large and widely varying Known: IoT

More information

Stacked IC Analysis Modeling for Power Noise Impact

Stacked IC Analysis Modeling for Power Noise Impact Si2 Open3D Kick-off Meeting June 7, 2011 Stacked IC Analysis Modeling for Power Noise Impact Aveek Sarkar Vice President Product Engineering & Support Stacked IC Design Needs Implementation Electrical-,

More information

Galaxy Custom Designer SE The New Choice in Custom Schematic Editing and Simulation Environment

Galaxy Custom Designer SE The New Choice in Custom Schematic Editing and Simulation Environment Datasheet Galaxy Custom Designer SE The New Choice in Custom Schematic Editing and Simulation Environment Overview Galaxy Custom Designer SE is the next-generation choice for schematic entry, enabling

More information

Microsemi IP Cores Accelerate the Development Cycle and Lower Development Costs

Microsemi IP Cores Accelerate the Development Cycle and Lower Development Costs Microsemi IP Cores Accelerate the Development Cycle and Lower Development Costs October 2014 Introduction Today s FPGAs and System-on-Chip (SoC) FPGAs offer vast amounts of user configurable resources

More information

AN INTRODUCTION TO HYPERLYNX SI/PI TECHNOLOGY

AN INTRODUCTION TO HYPERLYNX SI/PI TECHNOLOGY AN INTRODUCTION TO HYPERLYNX SI/PI TECHNOLOGY BY STEVE KAUFER, MENTOR H I G H S P E E D D E S I G N W H I T E P A P E R OVERVIEW Digital designers are now required to make the leap from time domain to

More information

Common Platform Ecosystem Enablement

Common Platform Ecosystem Enablement Joe Abler Common Platform Ecosystem Enablement IBM provides a complete Foundry solution Innovative technology Leadership road map with advanced SiGe & RF offerings Leading-edge CMOS process development

More information

DEMO: OpenPDK Schematic Symbol Standard V1.0 It s ALIVE!

DEMO: OpenPDK Schematic Symbol Standard V1.0 It s ALIVE! OA DEMO: OpenPDK Schematic Symbol Standard V1.0 It s ALIVE! OPDK Reference Symbol Library Ruby Tools: Translate SYMBOLS: OA to XML & OA to SVG 89 symbols OA opdksymbolchk.py * XSD/XML Validation * Constraints

More information

VLSI design project, TSEK01

VLSI design project, TSEK01 VLSI design project, TSEK01 Project description and requirement specification Version 1.0 Project: A First-Order Sigma-Delta Modulator with 3-bit Quantizer Project number: 5 Project Group: Name Project

More information

One-Shot DRC within a Fine-Grain Physical Verification Platform for advanced process nodes

One-Shot DRC within a Fine-Grain Physical Verification Platform for advanced process nodes One-Shot DRC within a Fine-Grain Physical Verification Platform for advanced process nodes Last updated: May, 2017 To meet the challenge of nano-scale, deep sub-wavelength processes, innovative One -Shot

More information

Transforming a Leading-Edge Microprocessor Wafer Fab into a World Class Silicon Foundry. Dr. Thomas de Paly

Transforming a Leading-Edge Microprocessor Wafer Fab into a World Class Silicon Foundry. Dr. Thomas de Paly Transforming a Leading-Edge Microprocessor Wafer Fab into a World Class Silicon Foundry Dr. Thomas de Paly October 06, 2009 Opportunity Meets Vision Vision To be the first truly global semiconductor foundry,

More information

Mixed-Signal Analog. C.S. Lee. Senior Vice President High-Volume Analog & Logic

Mixed-Signal Analog. C.S. Lee. Senior Vice President High-Volume Analog & Logic Mixed-Signal Analog C.S. Lee Senior Vice President High-Volume Analog & Logic Mixed-Signal Analog Market Total Analog TAM 2004 $31.4 Billion Standard $11.9B Vertical Applications $19.5B Market Characteristics

More information

Visual Design Flows for Faster Debug and Time to Market FlowTracer White Paper

Visual Design Flows for Faster Debug and Time to Market FlowTracer White Paper Visual Design Flows for Faster Debug and Time to Market FlowTracer White Paper 2560 Mission College Blvd., Suite 130 Santa Clara, CA 95054 (408) 492-0940 Introduction As System-on-Chip (SoC) designs have

More information

Dell Software Defined Enterprise

Dell Software Defined Enterprise Dell Software Defined Enterprise A practical vision of Future Ready IT Armughan Ahmad Vice President, Dell Enterprise Solutions @ArmughanAA 1 2 3 Defining the Software-Defined Enterprise Strategy for success

More information

electronic lab 11 Fedora Electronic Lab empowers hardware engineers and universities with opensource solutions for micro nano electronics engineering.

electronic lab 11 Fedora Electronic Lab empowers hardware engineers and universities with opensource solutions for micro nano electronics engineering. The Fedora Project is out front for you, leading the advancement of free, open software and content. electronic lab 11 Community Leader in opensource EDA deployment Fedora Electronic Lab empowers hardware

More information

Dictionary Driven Exchange Content Assembly Blueprints

Dictionary Driven Exchange Content Assembly Blueprints Dictionary Driven Exchange Content Assembly Blueprints Concepts, Procedures and Techniques (CAM Content Assembly Mechanism Specification) Author: David RR Webber Chair OASIS CAM TC January, 2010 http://www.oasis-open.org/committees/cam

More information

Connected Grid Design Suite-Substation Workbench Release 1.0: Frequently Asked Questions (FAQ)

Connected Grid Design Suite-Substation Workbench Release 1.0: Frequently Asked Questions (FAQ) Connected Grid Design Suite-Substation Workbench Release 1.0: Frequently Asked Questions (FAQ) Revised June 12, 2013 Online Part Number: Cisco Systems, Inc. www.cisco.com Questions: Questions: Introduction

More information

VLSI CAD ENGINEERING GRACE GAO, PRINCIPLE ENGINEER, RAMBUS INC. AUGUST 5, 2017

VLSI CAD ENGINEERING GRACE GAO, PRINCIPLE ENGINEER, RAMBUS INC. AUGUST 5, 2017 VLSI CAD ENGINEERING GRACE GAO, PRINCIPLE ENGINEER, RAMBUS INC. AUGUST 5, 2017 Agenda CAD (Computer-Aided Design) General CAD CAD innovation over the years (Short Video) VLSI CAD (EDA) EDA: Where Electronic

More information

PACKAGE DESIGNERS NEED ASSEMBLY-LEVEL LVS FOR HDAP VERIFICATION TAREK RAMADAN MENTOR, A SIEMENS BUSINESS

PACKAGE DESIGNERS NEED ASSEMBLY-LEVEL LVS FOR HDAP VERIFICATION TAREK RAMADAN MENTOR, A SIEMENS BUSINESS PACKAGE DESIGNERS NEED ASSEMBLY-LEVEL LVS FOR HDAP VERIFICATION TAREK RAMADAN MENTOR, A SIEMENS BUSINESS D E S I G N T O S I L I C O N W H I T E P A P E R w w w. m e n t o r. c o m INTRODUCTION Contrary

More information

RTL2GDS Low Power Convergence for Chip-Package-System Designs. Aveek Sarkar VP, Technology Evangelism, ANSYS Inc.

RTL2GDS Low Power Convergence for Chip-Package-System Designs. Aveek Sarkar VP, Technology Evangelism, ANSYS Inc. RTL2GDS Low Power Convergence for Chip-Package-System Designs Aveek Sarkar VP, Technology Evangelism, ANSYS Inc. Electronics Design Complexities Antenna Design and Placement Chip Low Power and Thermal

More information

5.2 Technology Leadership

5.2 Technology Leadership 5.1.4 Production in 2009 and 2008 Unit: Capacity / Output (8-inch equivalent wafers) / Amount (NT$ thousands) Wafers Year Capacity Output Amount 2009 9,954,558 7,582,664 150,572,709 2008 9,376,612 8,350,692

More information

High Volume Manufacturing Supply Chain Ecosystem for 2.5D HBM2 ASIC SiPs

High Volume Manufacturing Supply Chain Ecosystem for 2.5D HBM2 ASIC SiPs Open-Silicon.com 490 N. McCarthy Blvd, #220 Milpitas, CA 95035 408-240-5700 HQ High Volume Manufacturing Supply Chain Ecosystem for 2.5D HBM2 ASIC SiPs Open-Silicon Asim Salim VP Mfg. Operations 20+ experience

More information

oascript HowTo Kevin Nesmith Lead Engineer, Si2 June 10, 2013

oascript HowTo Kevin Nesmith Lead Engineer, Si2 June 10, 2013 oascript HowTo Kevin Nesmith Lead Engineer, Si2 June 10, 2013 1 oascript News Chip Designer Centric Python API Tcl API Ruby API Perl API Language-Specific Bindings Type Mapping Type Mapping Type Mapping

More information

Manufacturing and Technology R&D

Manufacturing and Technology R&D Manufacturing and Technology R&D Jean-Marc Chery Chief Operating Officer Orio Bellezza Executive Vice President General Manager, Front-End Manufacturing & Technology R&D Sense and Power & Automotive (SP&A)

More information

Compact Model Council

Compact Model Council Compact Model Council Keith Green (TI) Chair Peter Lee (Elpida) Vice Chair 1 History and Purpose The CMC was formed in 1996 as a collaboration of foundries, fabless companies, IDMs and EDA vendors Foundry

More information

Xilinx SSI Technology Concept to Silicon Development Overview

Xilinx SSI Technology Concept to Silicon Development Overview Xilinx SSI Technology Concept to Silicon Development Overview Shankar Lakka Aug 27 th, 2012 Agenda Economic Drivers and Technical Challenges Xilinx SSI Technology, Power, Performance SSI Development Overview

More information

Simulation and Modeling for Signal Integrity and EMC

Simulation and Modeling for Signal Integrity and EMC Simulation and Modeling for Signal Integrity and EMC Lynne Green Sr. Member of Consulting Staff Cadence Design Systems, Inc. 320 120th Ave NE Bellevue, WA 98005 USA (425) 990-1288 http://www.cadence.com

More information

Preface. This Book and Simulation Software Bundle Project

Preface. This Book and Simulation Software Bundle Project Preface This Book and Simulation Software Bundle Project Dear Reader, this book project brings to you a unique study tool for ESD protection solutions used in analog-integrated circuit (IC) design. Quick-start

More information

An overview of standard cell based digital VLSI design

An overview of standard cell based digital VLSI design An overview of standard cell based digital VLSI design Implementation of the first generation AsAP processor Zhiyi Yu and Tinoosh Mohsenin VCL Laboratory UC Davis Outline Overview of standard cellbased

More information

CMOS Design Lab Manual

CMOS Design Lab Manual CMOS Design Lab Manual Developed By University Program Team CoreEl Technologies (I) Pvt. Ltd. 1 Objective Objective of this lab is to learn the Mentor Graphics HEP2 tools as well learn the flow of the

More information