Review from last lecture

Transcription

1 CSE820 Gaduate Compute Achitectue Week 3 Pefomance + Pipeline Review Based on slides by David Patteson Review fom last lectue Tacking and extapolating technology pat of achitect s esponsibility Expect Bandwidth in disks, DRAM, netwok, and pocessos to impove by at least as much as the squae of the impovement in Latency Quantify Cost (vs. Pice) IC f(aea 2 ) + Leaning cuve, volume, commodity, magins Quantify dynamic and static powe Capacitance x Voltage 2 x fequency, Enegy vs. powe Quantify dependability Reliability (MTTF vs. FIT), Availability (MTTF/(MTTF+MTTR) 2 CS252 S05 1

2 Outline Review Quantify and summaize pefomance Ratios, Geometic Mean, Multiplicative Standad Deviation F&P: Benchmaks age, disks fail,1 point fail dange MIPS An ISA fo Pipelining 5 stage pipelining Stuctual and Data Hazads Fowading Banch Schemes Exceptions and Inteupts Conclusion 3 Definition: Pefomance Pefomance is in units of things pe sec bigge is bette If we ae pimaily concened with esponse time pefomance(x) = 1 execution_time(x) " X is n times faste than Y" means Pefomance(X) Execution_time(Y) n = = Pefomance(Y) Execution_time(X) 4 CS252 S05 2

3 Fallacies and Pitfalls (1/2) Fallacies - commonly held misconceptions When discussing a fallacy, we ty to give a counteexample. Pitfalls - easily made mistakes. Often genealizations of pinciples tue in limited context Show Fallacies and Pitfalls to help you avoid these eos Fallacy: Benchmaks emain valid indefinitely Once a benchmak becomes popula, temendous pessue to impove pefomance by tageted optimizations o by aggessive intepetation of the ules fo unning the benchmak: benchmaksmanship. 70 benchmaks fom the 5 SPEC eleases. 70% wee dopped fom the next elease since no longe useful Pitfall: A single point of failue Rule of thumb fo fault toleant systems: make sue that evey component was edundant so that no single component failue could bing down the whole system (e.g, powe supply) 5 Fallacies and Pitfalls (2/2) Fallacy - Rated MTTF of disks is 1,200,000 hous o 140 yeas, so disks pactically neve fail If disk lifetime is 5 ys eplace disks evey 5 ys; on avg. 28 eplacements wouldn't fail in 140 yeas A bette unit: % that fail (1.2M MTTF = 833 FIT) Fail ove lifetime: if had 1000 disks fo 5 yeas = 1000*(5*365*24)*833 /10 9 = 36,485,000 / 10 6 = 37 = 3.7% (37/1000) fail ove 5 y lifetime (1.2M h MTTF) But this is unde pistine conditions little vibation, naow tempeatue ange no powe failues Real wold: 3% to 6% of SCSI dives fail pe yea FIT o 150, ,000 hou MTTF [Gay & van Ingen 05] 3% to 7% of ATA dives fail pe yea FIT o 125, ,000 hou MTTF [Gay & van Ingen 05] 6 CS252 S05 3

4 Outline Review Quantify and summaize pefomance Ratios, Geometic Mean, Multiplicative Standad Deviation F&P: Benchmaks age, disks fail,1 point fail dange 252 Administivia MIPS An ISA fo Pipelining 5 stage pipelining Stuctual and Data Hazads Fowading Banch Schemes Exceptions and Inteupts Conclusion 7 A "Typical" RISC ISA 32-bit fixed fomat instuction (3 fomats) bit GPR (R0 contains zeo, DP take pai) 3-addess, eg-eg aithmetic instuction Single addess mode fo load/stoe: base + displacement no indiection Simple banch conditions Delayed banch see: SPARC, MIPS, HP PA-Risc, DEC Alpha, IBM PowePC, CDC 6600, CDC 7600, Cay-1, Cay-2, Cay-3 8 CS252 S05 4

5 Example: MIPS (- MIPS) iste-iste Op Rs1 iste-immediate Rs Op Rs1 Rd immediate Banch Op taget Rd Opx Op Rs1 Rs2/Opx immediate Jump / Call 9 Datapath vs Contol Datapath Contolle signals Contol Points Datapath: Stoage, FU, inteconnect sufficient to pefom the desied functions Inputs ae Contol Points Outputs ae signals Contolle: State machine to ochestate opeation on the data path Based on desied function and signals 10 CS252 S05 5

6 Appoaching an ISA Instuction Set Achitectue Defines set of opeations, instuction fomat, hadwae suppoted data types, named stoage, addessing modes, sequencing Meaning of each instuction is descibed by RTL on achitected egistes and memoy Given technology constaints assemble adequate datapath Achitected stoage mapped to actual stoage Function units to do all the equied opeations Possible additional stoage (eg. MAR, MBR, ) Inteconnect to move infomation among egs and FUs Map each instuction to sequence of RTLs Collate sequences into symbolic contolle state tansition diagam (STD) Lowe symbolic STD to contol points Implement contolle 11 5 Steps of MIPS Datapath Figue A.2, Page A-8 Instuction Fetch Inst. Decode. Fetch Execute Add. Calc Memoy Access Wite Back Next PC 4 Adde Next SEQ PC RS1 Zeo? MUX Addess Memoy Inst RS2 RD File MUX MUX Data Memoy L M D MUX IR <= mem[pc]; PC <= PC + 4 Imm Sign Extend [IR d ] <= [IR s ] op IRop [IR t ] WB Data 12 CS252 S05 6

7 5 Steps of MIPS Datapath Figue A.3, Page A-9 Instuction Fetch Inst. Decode. Fetch Execute Add. Calc Memoy Access Wite Back Next PC 4 Adde Next SEQ PC RS1 Next SEQ PC Zeo? MUX Addess Memoy IR <= mem[pc]; PC <= PC + 4 A <= [IR s ]; IF/ID RS2 Imm File Sign Extend ID/EX MUX MUX EX/MEM RD RD RD Data Memoy MEM/WB MUX WB Data B <= [IR t ] slt <= A op IRop B WB <= slt [IR d ] <= WB 13 Inst. Set Pocesso Contolle IR <= mem[pc]; PC <= PC + 4 JSR b JR jmp A <= [IR s ]; B <= [IR t ] RR opfetch-dcd RI LD ST if bop(a,b) PC <= IR jadd <= A op IRop B <= A op IRop IR im <= A + IR im PC <= PC+IR im WB <= WB <= WB <= Mem[] [IR d ] <= WB [IR d ] <= WB [IR d ] <= WB 14 CS252 S05 7

8 5 Steps of MIPS Datapath Figue A.3, Page A-9 Next PC Instuction Fetch 4 Adde Inst. Decode. Fetch Next SEQ PC RS1 Execute Add. Calc Next SEQ PC Zeo? Memoy Access MUX Wite Back Addess Memoy IF/ID RS2 File ID/EX MUX MUX EX/MEM Data Memoy MEM/WB MUX Imm Sign Extend RD RD RD WB Data Data stationay contol local decode fo each instuction phase / pipeline stage 15 Visualizing Pipelining Figue A.2, Page A-8 Time (clock cycles) I n s t. Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 O d e 16 CS252 S05 8

9 Pipelining is not quite that easy! Limits to pipelining: Hazads pevent next instuction fom executing duing its designated clock cycle Stuctual hazads: HW cannot suppot this combination of instuctions (single peson to fold and put clothes away) Data hazads: Instuction depends on esult of pio instuction still in the pipeline (missing sock) Contol hazads: Caused by delay between the fetching of instuctions and decisions about changes in contol flow (banches and jumps). 17 One Memoy Pot/Stuctual Hazads Figue A.4, Page A-14 Time (clock cycles) Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 I n s t. O d e Load Inst 1 Inst 2 Inst 3 Inst 4 18 CS252 S05 9

10 One Memoy Pot/Stuctual Hazads (Simila to Figue A.5, Page A-15) Time (clock cycles) Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 I n s t. O d e Load Inst 1 Inst 2 Stall Inst 3 Bubble Bubble Bubble Bubble Bubble How do you bubble the pipe? 19 Speed Up Equation fo Pipelining Appendix A, page A-12 CPI pipelined = Ideal CPI + Aveage Stall cycles pe Inst If all instuctions take the same time, unpipelined CPI is the pipeline depth. Ideal CPI Pipeline depth Speedup = Ideal CPI + Pipeline stall CPI Cycle Cycle Time Time unpipelined pipelined Fo simple RISC pipeline, CPI = 1: Pipeline depth Speedup = 1 + Pipeline stall CPI Cycle Cycle Time Time unpipelined pipelined 20 CS252 S05 10

11 Example: Dual-pot vs. Single-pot Machine A: Dual poted memoy ( Havad Achitectue ) Machine B: Single poted memoy, but its pipelined implementation has a 1.05 times faste clock ate (i.e. has a stuctual hazad with espect to memoy) Ideal CPI = 1 fo both Loads ae 40% of instuctions executed SpeedUp A = Pipeline Depth/(1 + 0) x (clock unpipe /clock pipe ) = Pipeline Depth SpeedUp B = Pipeline Depth/( x 1) x (clock unpipe /(clock unpipe / 1.05) = (Pipeline Depth/1.4) x 1.05 = 0.75 x Pipeline Depth SpeedUp A / SpeedUp B = Pipeline Depth/(0.75 x Pipeline Depth) = 1.33 Machine A is 1.33 times faste 21 Data Hazad on R1 Figue A.6, Page A-17 Time (clock cycles) IF ID/RF EX MEM WB I n s t. add 1,2,3 sub 4,1,3 O d e and 6,1,7 o 8,1,9 xo 10,1,11 22 CS252 S05 11

12 Thee Geneic Data Hazads Read Afte Wite (RAW) Inst J ties to ead opeand befoe Inst I wites it I: add 1,2,3 J: sub 4,1,3 Caused by a Dependence (in compile nomenclatue). This hazad esults fom an actual need fo communication. 23 Thee Geneic Data Hazads Wite Afte Read (WAR) Inst J wites opeand befoe Inst I eads it I: sub 4,1,3 J: add 1,2,3 K: mul 6,1,7 Called an anti-dependence by compile wites. This esults fom euse of the name 1. Cannot happen in MIPS 5 stage pipeline because: All instuctions take 5 stages, and Reads ae always in stage 2, and Wites ae always in stage 5 24 CS252 S05 12

13 Thee Geneic Data Hazads Wite Afte Wite (WAW) Inst J wites opeand befoe Inst I wites it. I: sub 1,4,3 J: add 1,2,3 K: mul 6,1,7 Called an output dependence by compile wites. This also esults fom the euse of name 1. Cannot happen in MIPS 5 stage pipeline because: All instuctions take 5 stages, and Wites ae always in stage 5 Will see WAR and WAW in moe complicated pipes 25 Fowading to Avoid Data Hazad Figue A.7, Page A-19 Time (clock cycles) I n s t. add 1,2,3 sub 4,1,3 O d e and 6,1,7 o 8,1,9 xo 10,1,11 26 CS252 S05 13

14 HW Change fo Fowading Figue A.23, Page A-37 NextPC istes ID/EX mux mux EX/MEM Data Memoy MEM/WR Immediate mux What cicuit detects and esolves this hazad? 27 Fowading to Avoid LW-SW Data Hazad Figue A.8, Page A-20 Time (clock cycles) I n s t. add 1,2,3 lw 4, 0(1) O d e sw 4,12(1) o 8,6,9 xo 10,9,11 28 CS252 S05 14

15 Data Hazad Even with Fowading Figue A.9, Page A-21 Time (clock cycles) I n s t. lw 1, 0(2) sub 4,1,6 O d e and 6,1,7 o 8,1,9 29 Data Hazad Even with Fowading (Simila to Figue A.10, Page A-21) Time (clock cycles) I n s t. O d e lw 1, 0(2) sub 4,1,6 and 6,1,7 Bubble Bubble o 8,1,9 Bubble How is this detected? 30 CS252 S05 15

16 Softwae Scheduling to Avoid Load Hazads Ty poducing fast code fo a = b + c; d = e f; assuming a, b, c, d,e, and f in memoy. Slow code: LW Rb,b LW Rc,c ADD Ra,Rb,Rc SW a,ra LW Re,e LW Rf,f SUB Rd,Re,Rf SW d,rd Fast code: LW Rb,b LW Rc,c LW Re,e ADD Ra,Rb,Rc LW Rf,f SW a,ra SUB Rd,Re,Rf SW d,rd Compile optimizes fo pefomance. Hadwae checks fo safety. 31 Outline Review Quantify and summaize pefomance Ratios, Geometic Mean, Multiplicative Standad Deviation F&P: Benchmaks age, disks fail,1 point fail dange 252 Administivia MIPS An ISA fo Pipelining 5 stage pipelining Stuctual and Data Hazads Fowading Banch Schemes Exceptions and Inteupts Conclusion 32 CS252 S05 16

17 Contol Hazad on Banches Thee Stage Stall 10: beq 1,3,36 14: and 2,3,5 18: o 6,1,7 22: add 8,1,9 36: xo 10,1,11 What do you do with the 3 instuctions in between? How do you do it? Whee is the commit? 33 Banch Stall Impact If CPI = 1, 30% banch, Stall 3 cycles => new CPI = 1.9! Two pat solution: Detemine banch taken o not soone, AND Compute taken banch addess ealie MIPS banch tests if egiste = 0 o 0 MIPS Solution: Move Zeo test to ID/RF stage Adde to calculate new PC in ID/RF stage 1 clock cycle penalty fo banch vesus 3 34 CS252 S05 17

18 Pipelined MIPS Datapath Figue A.24, page A-38 Next PC Instuction Fetch 4 Adde Inst. Decode. Fetch Next SEQ PC Adde RS1 MUX Zeo? Execute Add. Calc Memoy Access Wite Back Addess Memoy IF/ID RS2 File ID/EX MUX EX/MEM Data Memoy MEM/WB MUX Imm Sign Extend RD RD RD WB Data Inteplay of instuction set design and cycle time. 35 Fou Banch Hazad Altenatives #1: Stall until banch diection is clea #2: Pedict Banch Not Taken Execute successo instuctions in sequence Squash instuctions in pipeline, if banch actually taken Advantage of late pipeline state update 47% MIPS banches not taken on aveage PC+4 aleady calculated, so use it to get next instuction #3: Pedict Banch Taken 53% MIPS banches taken on aveage But haven t calculated banch taget addess in MIPS» MIPS still incus 1 cycle banch penalty» Othe machines: banch taget known befoe outcome 36 CS252 S05 18

19 Fou Banch Hazad Altenatives #4: Delayed Banch Define banch to take place AFTER a following instuction banch instuction sequential successo 1 sequential successo 2... sequential successo n banch taget if taken Banch delay of length n 1 slot delay allows pope decision and banch taget addess in 5 stage pipeline MIPS uses this 37 Scheduling Banch Delay Slots (Fig A.14) A. Fom befoe banch B. Fom banch taget C. Fom fall though add $1,$2,$3 if $2=0 then delay slot sub $4,$5,$6 add $1,$2,$3 if $1=0 then delay slot add $1,$2,$3 if $1=0 then delay slot sub $4,$5,$6 becomes becomes becomes add $1,$2,$3 if $2=0 then if $1=0 then add $1,$2,$3 add $1,$2,$3 if $1=0 then sub $4,$5,$6 sub $4,$5,$6 A is the best choice, fills delay slot & educes instuction count (IC) In B, the sub instuction may need to be copied, inceasing IC In B and C, must be okay to execute sub when banch fails 38 CS252 S05 19

20 Delayed Banch Compile effectiveness fo single banch delay slot: Fills about 60% of banch delay slots About 80% of instuctions executed in banch delay slots useful in computation About 50% (60% x 80%) of slots usefully filled Delayed Banch downside: As pocesso go to deepe pipelines and multiple issue, the banch delay gows and need moe than one delay slot Delayed banching has lost populaity compaed to moe expensive but moe flexible dynamic appoaches Gowth in available tansistos has made dynamic appoaches elatively cheape 39 Evaluating Banch Altenatives Pipeline speedup = Pipeline depth 1 +Banch fequency Banch penalty Assume 4% unconditional banch, 6% conditional banchuntaken, 10% conditional banch-taken Scheduling Banch CPI speedup v. speedup v. Scheme penalty unpipelined stall Stall pipeline Pedict taken Pedict not taken Delayed banch CS252 S05 20

21 Poblems with Pipelining Exception: An unusual event happens to an instuction duing its execution Examples: divide by zeo, undefined opcode Inteupt: Hadwae signal to switch the pocesso to a new instuction steam Example: a sound cad inteupts when it needs moe audio output samples (an audio click happens if it is left waiting) Poblem: It must appea that the exception o inteupt must appea between 2 instuctions (I i and I i+1 ) The effect of all instuctions up to and including I i is totally complete No effect of any instuction afte I i can take place The inteupt (exception) handle eithe abots pogam o estats at instuction I i+1 41 Pecise Exceptions in Static Pipelines Key obsevation: achitected state only change in memoy and egiste wite stages. CS252 S05 21

22 And In Conclusion: Contol and Pipelining Quantify and summaize pefomance Ratios, Geometic Mean, Multiplicative Standad Deviation F&P: Benchmaks age, disks fail,1 point fail dange Next time: Read Appendix A, ecod bugs online! Contol VIA State Machines and Micopogamming Just ovelap tasks; easy if tasks ae independent Speed Up Pipeline Depth; if ideal CPI is 1, then: Pipeline depth Cycle Time Speedup = 1 + Pipeline stall CPI Cycle Time unpipelined pipelined Hazads limit pefomance on computes: Stuctual: need moe HW esouces Data (RAW,WAR,WAW): need fowading, compile scheduling Contol: delayed banch, pediction Exceptions, Inteupts add complexity 43 CS252 S05 22