Overview of Pipelining

Transcription

1 EEC 58 Compter Architectre Pipelining Department of Electrical Engineering and Compter Science Cleveland State University Fndamental Principles Overview of Pipelining

2 Pipelined Design otivation: Increase throghpt with little increase in hardware. Bandwidth or Throghpt = Performance Bandwidth (BW) = no. of tasks/nit time For a system that operates on one task at a time: Bandwidth = /delay (latency) BW can be increased by pipelining if many operands eist which need the same operation, i.e. many repetitions of the same task are to be performed. Latency reqired for each task remains the same or may even increase slightly. Ideal Pipelining L Comb. Logic n Gate Delay BW = ~(/n) L n -- 2 Gate Delay L n -- 2 Gate Delay BW = ~(2/n) L n -- Gate 3 Delay L n -- Gate 3 Delay L n -- Gate 3 Delay BW = ~(3/n) Bandwidth increases linearly with pipeline depth Latency increases by latch delays 2

3 F/F F/F Pipeline Stage Combinational Logic FO Intel Pentim (22-) pipeline stages: 2 (Northwood, 3 nm) to 3 (Prescott, 9 nm) Intel Core 2 (26) pipeline stages: (Penryn, 5 nm) Intel Core i7 (28) pipeline stages: 6 (Nehalem, 5 nm) P pipe stage~ 6 FO Pipelining Idealisms Uniform sbcomptations Can pipeline into stages with eqal delay Balance pipeline stages Identical comptations Can fill pipeline with identical work Unify instrction types Independent comptations No relationships between work nits inimize pipeline stalls Are these practical? No, bt can get close enogh to get significant speedp 3

4 Five-stage Pipelined path Inst. Fetch Inst. Decode Eec em WB IF/ID ID/EX EX/E E/WB reslt ress 2 reslt ress 6 etend 7 Eample for lw instrction: Fetch (IF) fetch IF/ID ID/EX EX/E E/WB reslt ress 2 reslt ress 6 etend 8

5 Eample for lw instrction: Decode (ID) decode IF/ID ID/EX EX/E E/WB reslt ress 2 reslt ress 6 etend 9 Eample for lw instrction: Eection (EX) Eection IF/ID ID/EX EX/E E/WB reslt ress 2 reslt ress 6 etend 5

6 Eample for lw instrction: emory (E) emory IF/ID ID/EX EX/E E/WB reslt ress 2 reslt ress 6 etend Eample for lw instrction: back (WB) back IF/ID ID/EX EX/E E/WB reslt ress 2 reslt ress 6 etend 2 6

7 Eample for sw instrction: emory (E) emory IF/ID ID/EX EX/E E/WB reslt ress 2 reslt ress 6 etend 3 Eample for sw instrction: back (WB): do nothing back IF/ID ID/EX EX/E E/WB reslt ress 2 reslt ress 6 etend 7

8 Corrected path (for lw) IF/ID ID/EX EX/E E/WB reslt ress 2 reslt ress 6 etend 5 Pipelining Eample add $, $5, $6 lw $3, 2($) add $2, $3, $ sb $, $2, $3 lw $, 2($) IF/ID ID/EX EX/E E/WB reslt ress 2 reslt ress 6 etend 6 8

9 Pipeline Control Src IF/ID ID/EX EX/E E/WB Evalate branch TARGET reslt Branch ress For I-type 2 [5 ] 6 etend Src 6 Evalate branch CONDITION control reslt em ress em emto [2 6] [5 ] Op Dst Pipeline Control Etend pipeline s to inclde control information (created in ID) Pass control signals along jst like the Eection/ress Calclation stage control lines emory access stage control lines -back stage control lines Dst Op Op Src Branch em em write em to R-format lw sw X X beq X X WB Control WB EX WB 8 IF/ID ID/EX EX/E E/WB 9

10 path with Control Src Control ID/EX WB EX/E WB E/WB IF/ID EX WB ress 2 reslt Src reslt Branch ress em emto 6 [5 ] etend 6 control em [2 6] [5 ] 9 Dst Op Pipelining is not qite that straightforward! Limits to pipelining: Hazards prevent net instrction from eecting dring its designated clock cycle Strctral hazards: HW cannot spport this combination of instrctions hazards: depends on reslt of prior instrction still in the pipeline Control hazards: Cased by delay between the fetching of instrctions and decisions abot changes in control flow (branches and jmps). 2

11 order order Single emory Port Time (clock cycles) Cycle Cycle 2 Cycle 3 Cycle Cycle 5 Cycle 6 Cycle 7 Load Dem Instr Dem Instr 2 Dem Instr 3 Dem Instr Dem 2 Single emory Port / Strctral Hazard Time (clock cycles) Cycle Cycle 2 Cycle 3 Cycle Cycle 5 Cycle 6 Cycle 7 Load Dem add Dem Instr 2 Dem Instr 3 Dem Instr Dem 22

12 order order Hazard Time (clock cycles) add r,r2,r3 Dem sb r,r,r3 Dem and r6,r,r7 Dem or r8,r,r9 Dem or r,r,r Dem 23 Forwarding to Avoid Hazard Time (clock cycles) add r,r2,r3 Dem sb r,r,r3 Dem and r6,r,r7 Dem or r8,r,r9 Dem or r,r,r Dem 2 2

13 UX UX UX UX Forwarding (simplified) ID/EX EX/E E/WB ister File emory 25 Forwarding (from EX/E) ID/EX EX/E E/WB ister File emory 26 3

14 order UX UX UX Forwarding (from E/WB) ID/EX EX/E E/WB ister File emory 27 Hazard Even with Forwarding Time (clock cycles) lw r, (r2) Dem sb r,r,r6 Dem and r6,r,r7 Dem or r8,r,r9 Dem Forward backward in time no way!! (or way?) 28

15 order Hazard Even with Forwarding Time (clock cycles) lw r, (r2) Dem sb r,r,r6 Bbble Dem and r6,r,r7 Bbble Dem or r8,r,r9 Bbble Dem Need pipeline interlock (or stall) to stop instrctions from issing. How is this detected? 29 Strctral Hazards Clock Cycles UL.D F,F,F6 IF ID WB ADD.D F2,F,F6 IF ID EX WB IF ID EX WB IF ID A A2 A3 A WB IF ID EX WB IF ID EX WB L.D F2,(R2) IF ID EX WB to file at the same cycle (cc) to the same (WAW) E in cc 3 5

16 Hazard Detection Unit Stall by letting an instrction that won t write anything go forward Stall the pipeline if ID/EX is a load, and (load rt=if/id.rs or load rt=if/id.rt) ID/EX.em Hazard detection nit ID/EX i.e., stall if DESTINATION of load is a SOURCE of the following instrction IF/ID Control WB EX/E WB E/WB IF/ID EX WB IF/ID.isterRs IF/ID.isterRt IF/ID.isterRt IF/ID.isterRd Rt Rd EX/E.isterRd ID/EX.isterRt Rs Rt Forwarding nit E/WB.isterRd 3 Code Reschedling to Avoid Load Hazards Try prodcing fast code for a = b + c; d = e f; assming a, b, c, d, e, and f in. Slow code: LW LW ADD SW LW LW SUB SW Rb,b Rc,c Ra,Rb,Rc a,ra Re,e Rf,f Rd,Re,Rf d,rd Fast code: LW LW LW ADD LW SW SUB SW Rb,b Rc,c Re,e Ra,Rb,Rc Rf,f a,ra Rd,Re,Rf d,rd Compiler optimizes for performance. Hardware checks for safety. 6

17 Control Hazard de to Branches (3 stall cycles) : beq r,r3,36 Dem : and r2,r3,r5 Dem 8: or r6,r,r7 Dem 22: add r8,r,r9 Dem 36: or r,r,r Dem What do yo do with the 3 instrctions in between? How do yo do it? Where is the commit? 33 Branch Hazard Resoltions # Stall ntil branch direction is clear () #2: Static Branch Prediction Predict Not Taken (Fall throgh, as shown in previos slide) Eecte sccessor instrctions in seqence Sqash instrctions in pipeline if branch actally taken + already calclated, so se it to get net instrction Predict Branch Taken Bt haven t calclated branch target address ight incr cycle branch penalty Other machines: branch target known before otcome #3 Dynamic Branch Prediction Several techniqes eist 3 7

18 Alternative Branch Hazard Resoltions # Delayed Branch Define branch to take place AFTER a following instrction branch instrction seqential sccessor seqential sccessor 2... seqential sccessor n branch target if taken Branch delay of length n slot delay allows proper decision and branch target address in 5 stage pipeline [after moving the branch target address calclation and branch decision evalation in the SECOND (i.e., ID) stage] 35 Other Pipelining Isses To have all instrctions finish within one cycle Slow down freqency to cope w/ the critical operation, or Allow non-niform latency operation 36 8

19 Spport ltiple FP Operations 2 3 E X Integer Unit FP mltiplier IF ID FP add E WB A A A A FP divider (non-pipelined) Complicate bypass (forwarding) Potential strctral hazard ltiple (FP) instrctions can complete at the same time RF might need to be mlti-ported Ordering isse, who gets to pdate the? Ot-of-order completion/retirement: Precise eception isse 37 Fll Bypass/Forwarding Needed Clock Cycles L.D F,(R2) IF ID EX WB UL.D F,F,F6 IF ID S WB ADD.D F2,F,F8 IF S ID S S S S S S A A2 A3 A WB S.D F2,(R2) IF S S S S S S ID EX S S S WB 38 9

20 Precise Eception Isse DIV.D F,F2,F ADD.D F3,F,F8 SUB.D F2,F2,F (eception!) (completed) (completed) Precise eception: If the pipeline can (or mst) be stopped All the instrctions before the falty (or intended) instrction mst be completed All the instrctions after it mst not be completed Restart the eection from the falty (or intended) instrction State mst be consistent with the original program order Not straightforward with ot-of-order completion Simple soltion: Stalling ntil no eception of prior long-latency instrction is garanteed Other modern soltion: ROB (Re-Order Bffer) 39 2