1. Micro Architecture and Finite Length. Olle Seger Andreas Ehliar Dake Liu, Rizwan Azhgar

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1 1. Micro Architecture and Finite Length Olle Seger Andreas Ehliar Dake Liu, Rizwan Azhgar 1

2 Outline Introduction Some Administrative Information Basic Components Finite Length, Overflow, 2-complement, rounding, saturation About Lab-1, the Senior Processor.. 2

3 Administrative Information Labs In groups of two students No written report Be prepared to answer questions (both of you) about how your design works Mandatory 3

4 Some Basic Components Busses Multiplexers Registers Adders Multipliers 4

5 On-chip Busses Sharing data between different modules. All can read from the bus at the same time Only one can write to it at one time VHDL Verilog C<= A(4 downto 1) & B(6 downto 0); assign C = {A[4:1], B[6:0]}; 5

6 MUX or Multiplexer A B C D VHDL Y <= A when ctrl = 00 else B when ctrl = 01 else C when ctrl = 10 else D; (or) with ctrl select Y <= A when 00, B when 01, C when 10, D when others; process(a,b,c,d,ctrl)is begin case ctrl is when 0 => Y <= A; when 1 => Y <= B; when 2 => Y <= C; when others => Y <= D; end case; end process; ctrl Verilog Y = (ctrl == 2 b00)? A : (ctrl == 2 b01)? B : (ctrl == 2 b10)? C : D; (or) begin case (ctrl) 2 b00 : Y = A; 2 b01 : Y = B; 2 b10 : Y = C; 2 b11 : Y = D; endcase end Y 6

7 Registers VHDL process(clk)is if rising_edge(clk) then if rst=1 then q <= 0; elsif ld=1 then q <= d; end if; end process; Verilog clk) begin if (rst) q <= 0; else if (ld) q <= d; end d 0 ld rst K clk N rst ld out q 7

8 2 s Complement Number Representation -1 ½ ¼ 1/ /4 [-1,1-1/8] It s easy to increase the number of bits. It s still the same number ½ ¼ 1/8 1/16 1/ /4 [-4,4-1/32] duplicate sign bit concatenate zeros 8

9 2 s Complement Number Representation ½ ¼ 1/8 1/16 1/32 x y 1 y 2 x 2 rounding truncate ½ ¼ 1/8 x 1 x y ½ ¼ 1/8 x 1 x saturate x 1 =0 x 1 x 2 =10 x 1 x 2 =11-1 ½ ¼ 1/ ½ ¼ 1/ ½ ¼ 1/ y 1 MAX MIN 9

10 Adder(signed/unsigned) Implicitly: integer, two s complement {c_o, O[15:0]} <= A[15:0] + B[15:0] + {15 b0, c_i} Alternatively {c_o,o[15:0],x} <= {A[15],A[15:0],1} + {B[15],B[15:0], c_i} A B Input operands : N bit ; Output : N+1 bit c_o + c_i Subtraction : Using 2 s Complement O 10

11 Multiplier(signed) O[7:0] <= A[3:0] B[3:0] Example: Integer or Fractional Multiplication = or = = OMA[15:0] MULS 32 OMB[15:0] Input operands : N bit ; Output : 2N bit Mul_Output [31:0] 12

12 Signed multiplication paper&pencil algorithm * * * *

13 Register File X ar DM0 DM1 ar (1,15) (2,30) (1,15) ALU sign extend to(10,30) accumulator (10,30) scale round (10,30) (10,15) sat (1,15) 15

14 A Rounding Example Sign bit Sign bit Round Arithmetic Example: Round 8 bits to 4 bits Before round: 8 bits A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0 To round up, add A 3 as the carry in Round to nearest arithmetic b[3:0] = a[7:4] + {3 b000, a[3]} B 3 B 2 B 1 B 0 4 bits left after round and truncation A 7 A 6 A 5 A A 3 B 7 B 6 B 5 B 4 A 3 A 7 A 6 A 5 A 4 A B 7 B 6 B 5 B 4 X 16

15 Senior Assembler & Simulator Assembly Code Includes: Assembly Instructions: LD, ST, ADD, CMP, Symbolic name for memory locations: labels Assembler directives:.skip 31,.df 0.125, Senior Assembler: Translates assembly code into an executable binary code (Hex Format). Senior Simulator: Takes the hex file and provides a debugging environment. Assembly Code (ex.asm) Assembler (srasm) ex.hex Simulator (srsim) Debugging + Output text file 17

16 Senior Senior: DSP with lots of bells and whistles bit general regs (r0-r31) bit special purpose regs 4 32-bit accumulator regs + 8 guard bits (acr0-acr3) 18

17 Special purpose registers About Senior 19

18 About Senior Memory Where is the data? rom0 Where are the coefficients? rom0 But you need them at the same time. So? How to save the output to a text file out 0x11, r31 Important instructions convxx repeat vs cmp & jump set, clr move, ld, st Hint : check the cycles required for data to be ready and use NOP accordingly. PM dm0 ram0 rom0 RF DP CP dm1 ram1 20

19 About Senior move, load and store instructions move move.eq r7,r14 r22, rnd mul2 acr3 set r21,711 ld0 r1,(ar1,r9) ; r1 <- M0(ar1+r9) ld1 r1,(ar0++%) ; r1 <- M1(ar0) ; ar0 = (ar0==top0)?bot0:ar+step0 st1 (ar2++),r5 ; M1(ar2)<-r5,ar2++ 21

20 About Senior Short arithmetic, logic, shift instructions add add.ne r7,r14,r15 r7,r12 Long instructions addl.meq addl convss acr2,acr1,acr0 acr1,acr3,r2:0 acr0,(ar0++%),(ar1++%) ;acr0 += M0(ar0)*M1(ar1), ar0, ar1 22

21 23 About Senior How to use repeat Hardware loop! label_end repeat label_end, 32 set r4,0xfa72 move r1,sr3 mac acr0, r0, r1 move r17,sr31 These 3 instructions are repeated. No (visible) loop counter. No test. No jump.

22 About Senior How to use conditional branch jump label_start set r0,32 ; set loop counter dec r0 ; decrement loop counter jump.ne label_start ; no delay slots xxx ; branch delayed yyy ; 3 cycles zzz ; 24

23 About Senior jump instruction Another Example jump.ne ds2,label4 move r1,sr3 ; this will always execute set r2,7 ; so will this move r12,r3 ; but not this label4 set r7,3 label_start set r0,32 ; set loop counter dec r0 ; decrement loop counter jump.ne ds3 label_start xxx yyy zzz 25

24 About srsim How to debug in simulator (srsim) h: help menu r<n>: execution n lines of instructions l: list the instructions around the pc p: print of the values in registers Special registers: which are ar0 and ar1? Accumulation registers: which is acr0? g: run the whole program 26

25 Exercise 27

26 Exercise 28

27 Convolution y( n) 4 = h( k) x( n k) k = 0 = h(0) x( n) + h(1) x( n 1) + h(2) x( n 2) + h(3) x( n 3) + h(4) x( n 4) present sample previous sample x(n) x(n-1) x(n-2) x(n-3) x(n-4) reg reg reg reg h(0) h(1) h(2) h(3) h(4) Round Saturation y(n) 30

28 Exercise y( n) = h( k) x( n k) k = 0 0 n < 1000 coeffs ar1 h(0) h(1) h(31) 0 0 x(0) x(1) x(999) ar0 bot1 top1 signal ram1 rom0 ;; coeffs copied rom0 -> ram1 fir_filter set r3,signal set r1,1000 ; loop counter set ar1,coeffs ; ar1->coeffs set ar0,zeros ; ar0->signals set step1,1 set bot1,coeffs set top1,coeffs_end ;; loop inc r3 move ar0,r3 repeat falt,32 convss acr0,(--ar0),(ar1++%) falt dec r1 jump.ne ds3 loop move r31,rnd div2 acr0 clr acr0 ; clear accu out 0x11,r31 ;; ;; end of code out 0x13,r0 signal.rom0.scale 2.0.df df ;; 31

29 Exercise 1.2 with ringbuffer coeffs ar0 h(0) h(1) h(31) bot0 ringbuffer ar1 x(0) bot1 ekg top0 x(1) top1 rom0 ram1 x(0) x(1) x(999) ; ekg copied rom0->ram1 ; zeros in ringbuffer ; pointers fixed ;; set r1,1000 ; loop counter ;; loop ld1 r0,(ar2++) ; read signal dec r1 ; dec loop cnt st1 (ar1),r0 ; write r.b. repeat falt,31 convss acr0,(ar0++%),(ar1++%) falt move r2,ar1 convss acr0,(ar0++%),(ar1++%) move ar1,r2 jump.ne ds3 loop move r31,rnd div2 acr0 clr acr0 ; clear accu out 0x11,r31 ;; end of code out 0x13,r0 ar2 32

30 x = x0 + sin h y( n) = 31 k = 0 h( k) x( n k) 33

31 Frequency domain 34

32 0 Exercise 1.3 in r0,0x10 ringbuffer r 0 r 1 r 2 r 3 r 4 coeffs clr acr0 macss acr0,r0,r5 macss acr0,r1,r6 macss acr0,r2,r7 macss acr0,r3,r8 macss acr0,r4,r9 move r10,sat rnd acr0 nop out 0x11,r10 r 5 r 6 r 7 r 8 r 9 h 0 in r4,0x10 h 1 h 2 h 3 h clr acr0 4 macss acr0,r4,r5 macss acr0,r0,r6 macss acr0,r1,r7 macss acr0,r2,r8 macss acr0,r3,r9 move r10,sat rnd acr0 nop out 0x11,r10 Unroll the loop 5 times! Step h,x forward Fill in x backward 35

05 - Microarchitecture, RF and ALU

05 - Microarchitecture, RF and ALU September 15, 2015 Microarchitecture Design Step 1: Partition each assembly instruction into microoperations, allocate each microoperation into corresponding hardware modules. Step 2: Collect all microoperations