Design of Embedded DSP Processors

Transcription

1 Design of Embedded DSP Processors Unit 10: Integration and Verification 10/3/2017 Unit 10 of TSEA H1 1

2 Three integrations 1. Hardware integration (Integration of RTL codes) 2. Integration of the behavior model (the simulator) 3. Phy integration (HW protocol, clock /power domains, and critical paths) 10/3/2017 Unit 10 of TSEA H1 2

3 Contents 1. Integration of an IP core 2. Integration of SoC 3. Introduction to verification 4. Write testbench 10/3/2017 Unit 10 of TSEA H1 3

4 Integration of a (processor) core 10/3/2017 Unit 10 of TSEA H1 4

5 Some cores are complicated A power core 10/3/2017 For teachers use the book 5

6 RF PC FSM PM Instruction decoder AGU DMs Copyright of Linköping University, all rights reserved Some cores are simple Control path Addressing path mem subsystem MAC accelerator ALU Datapath Memory bus Register bus Control signals Integrate datapath, data access, accelerators, and control path into a core 10/3/2017 Unit 10 of TSEA H1 6

7 It is not just connections behavior function SoC Micro arc RTL layout structure 1. Functional: Be sure all instructions can be executed with available HW and connections, no structural hazard Reachable: All special registers/ports can be accessed 2. Structural: HW arch follows the instruction-set Combinational: bus matches, width, endian, direction Sequential: pipeline modification and balancing 3. Physical: speed, power consumption, silicon cost New hidden critical path, unnecessary toggling or even bugs after integration (missing keeper, missing default). Clock and power domains 10/3/2017 Unit 10 of TSEA H1 7 physical

8 E.g. integration for move/load/store DM0: Data memory 0 I/O port registers Special registers in AGU DM1: Data memory 1 Accumulator register in MAC General register file Special registers in control path Immediate data from control path General RF to all, so that all are reachable via general RF 10/3/2017 Unit 10 of TSEA H1 8

9 Move instructions based on busses 1. Should be a move instruction if a connection is available 2. Move must be emulated if there is no direct connection available 10/3/2017 Unit 10 of TSEA H1 9

10 Emulate when there is no HW Operation From To Emulation Move DM0 DM1 Load DM0 to GRF; Store GRF to DM1 Move DM1 DM0 Load DM1 to GRF; Store GRF to DM0 Load I/O port DM1/0 Load I/O port to GRF; Store GRF to DM1/0 Store DM1/0 I/O port Load DM1/0 to GRF; Store GRF to I/O port Load DM0 ACR Load DM0 to GRF; Move GRF to ACR (G,H,L) Store ACR DM0 Move ACR (G,H,L) to GRF; Store GRF to DM0 Load DM1 ACR Load DM1 to GRF; Move GRF to ACR (G,H,L) Store ACR DM1 Move ACR (G,H,L) to GRF; Store GRF to DM1 Load DM0/1 SRF Load DM0/1 to GRF; Move GRF to SRF Store SRF DM0/1 Move SRF to GRF; Store GRF to DM0/1 10/3/2017 Unit 10 of TSEA H1 10

11 Data Format Conversion While Accessing ACR Instruction Load ACR lower part Load ACR high part Load ACR guard Load ACR high and guard Load ACR Store ACR higher part Store ACR lower part Store guard bits in ACR Store result Operation ACR <= {ACR[39:16], Ra[15:0]} ACR <= { ACR[39:32], Ra[15:0]; ACR[15:0]} ACR <= { Ra[7:0], ACR[31:0]} ACR <= { {8{Ra[15]}}, Ra[15:0]; 16 b0} ACR<={ {8{Ra[15]}, Ra[15:0]; Rb[15:0]} Rd <= ACR[31:16] Rd <= ACR[15:0] Rd [7:0] <= ACR[39:32] Rd<=Saturation (round(acr[31:16])) 10/3/2017 Unit 10 of TSEA H1 11

12 Integrate RF / ALU / MAC into a core Operands and results Supply operands from memories and RF Shuffling multi operands to avoid conflicts Data forwarding for ALU, MAC, AGU Control signals Supply correct control signals at right time Manage critical control signal fanout 10/3/2017 Unit 10 of TSEA H1 12

13 Integrate control path into a core Avoid structural hazard Sufficient availalbe HW or remove instructions Careful memory partition, pipeline shimming Avoid pipeline hazard Check all pipeline execution tables Check control signals arrive at right pipelines Controls for clock / Power gating 10/3/2017 Unit 10 of TSEA H1 13

14 Implicit micro-operations: for example bus transactions, and instruction decoding Data memory addressing Operands Destination Operation Explicit specifiers Target addressing Copyright of Linköping University, all rights reserved Be sure there is no missing (explicit and hidden) function All micro-operations in an assembly instruction Explicit micro-operations specified in assembly manual: Explicit micro-operations specified in assembly code and binary machine code: Implicit microoperations not specified in assembly code: For example flag ops and PC<=PC+1 10/3/2017 Unit 10 of TSEA H1 14

15 Sufficient exposes to SoC 1. Memory (mapped / addressed) I/O 2. Connection to interrupt controller and timer 3. DMA / memory interface design 4. Data input / output design 5. Design for program loading and POR 6. Host interface and SoC bus interface 7. Nonfunctional (DFT, debug, trace, gatings) 10/3/2017 Unit 10 of TSEA H1 15

16 Datapath physical integration Critical path in a function block (such as MAC) and critical path in the core To simplify pipeline of a core, combinational pins may exist between function blocks. Hidden critical path will be exposed, mostly are false path not existing in specification. What is and how to manage false path 10/3/2017 Unit 10 of TSEA H1 16

17 Physical critical paths in DP Memory ports Registers A[15:0] Guard and concatenate on inputs Signed B B[15:0] Unsigned B 0 1 ACR1 ACR2 ACRm ACRn 17x17 bits multiplier Pipeline 10/3/2017 Unit 10 of TSEA H1 17

18 Physical critical paths in DP D-mem 1 D-mem 2 D-mem 3 D-mem 4 RF OPB RF OPA Constant 32 to1 32 to1 Long wires Long wires signed unsigned Very heavy fan out here! pipeline-op Multiplier 10/3/2017 Unit 10 of TSEA H1 18

19 Pipeline balancing Moving functions between pipelines Pre-processing Pre-processing Kernel processing Kernel processing Post-processing Post-processing (a) Before pipeline modification (b) After pipeline modification 10/3/2017 Unit 10 of TSEA H1 19

20 AA <= OPA AB <= OPB AA <= OPA AB <= INV (OPB) AA <= INV(OPA) AB <= OPB AA <= OPA, AB <= 1 AA <= 1, AB <= OPB AA <= OPA, AB <= -1 AA <= -1, AB <= OPB AA <= OPA AB <= OPB AA <= OPA AB <= INV (OPB) AA <= INV(OPA) AB <= OPB AA <= OPA, AB <= 1 AA <= 1, AB <= OPB AA <= OPA, AB <= -1 AA <= -1, AB <= OPB Pipeline balancing: Moving functions between pipelines Copyright of Linköping University, all rights reserved Pipeline register OPA <= {A[15], A[15:0]}; OPB <= {B[15], B[15:0]} OPA <= {A[15], A[15:0]}; OPB <= {B[15], B[15:0]} A+B, A-B, B-A, A+1, B+1, A-1, B-1 A+B, A-B, B-A, A+1, B+1, A-1, B-1 Logic above for Pre-processing Pipeline register Kernel arithmetic component: RA[17:0] <= {AA[16:0], 1 b1} + {AB[16:0], Carry_in} Kernel arithmetic component: RA[17:0] <= {AA[16:0], 1 b1} + {AB[16:0], Carry_in} SRA [15:0] <= RA[16:1] saturation yes SRA[15:0] <= SAT (RA[17:1]) SRA [15:0] <= RA[16:1] saturation yes SRA[15:0] <= SAT (RA[17:1]) Carry and saturation flag Carry and saturation flag 10/3/2017 For teachers use the book 20 Finish (a) Finish (b)

21 Integrate a DSP subsystem 10/3/2017 Unit 10 of TSEA H1 21

22 Definition: A DSP subsystem A DSP subsystem (not yet a chip) consists of one or several DSP cores, data memories and program memories, peripheral modules (interrupt controller, DMA ctrl, timer, and main memory interface), and accelerators 10/3/2017 Unit 10 of TSEA H1 22

23 A DSP subsystem example BBP ADC port Memory interface MCU (the baseband controller) Host interface DAC port Baseband connection network Symbol processor DFE Symbol processor FFT Symbol processor Matrix LLR processor Bit processor FEC processor 10/3/2017 Unit 10 of TSEA H1 23

24 The integration includes 1. Functional: inter-core communication (data, ctrl) Data communication: use/not use system DDR Inter module FIFO, resource/memory sharing hardware Control semaphore: APB (flex)? custom design (quality)? 2. Structural: NoC IP or custom connections Combinational: Avoid inter-core combinational logic Sequential: convention: all latches are on the receiver side 3. Physical: OBS! Extra critical path! What to do? Add SoC pipelines, use communication / bus protocols, GALS manage multi clock domains, clock/power gating 10/3/2017 Unit 10 of TSEA H1 24

25 SoC Integration 10/3/2017 Unit 10 of TSEA H1 25

26 SoC definition Very confusing, most chips can be a SoC Several functional IP cores + IP modules + controller as a master (run OS and main) + on chip main memories + peripherals Could be even without a master (dataflow processor) (NPU or GPU master can be in another chip) 10/3/2017 Unit 10 of TSEA H1 26

27 A typical high-end SoC A smartphone chip from Qualcomm/MTK Include all RF + ADC + DAC + digital baseband + ARM Application processor cluster with NEON + Mali core + Rendering IP + ISP + video / audio codec + GSM module + CDMA2000 module + WiFi module + BT module + GPS module + AHB/CCI + chip level cache + LPDDR controller/phy + LED driver + MIPI controller/phy + USB controller/phy + APB bridge + always-on + human peripherals /3/2017 Unit 10 of TSEA H1 27

28 Oracle SPARC M7: A 20 nm 32-Core 64 MB L3 Cache 1TOPS Processor /3/2017 Unit 10 of TSEA H1 28

29 A typical low-end SoC An IoT chip: Intel Edison dual-core Intel Quark x86 CPU, Bluetooth module, WiFi module, ADC, DAC, UART (connect to a micro USB), I2C (connect to SD memory) A NB-IoT chip... 10/3/2017 Unit 10 of TSEA H1 29

30 Non-functional modules A module not for customer functions DFT: (ATPG, BIST, SoC, Boundary scan) What are that? Challenges (SoC test time)? DFT challenged by large combinational blocks DFT challenged by many memory blocks Trace Real time probing and buffering Power control module, clock gating module 10/3/2017 Unit 10 of TSEA H1 30

31 DMA Copyright of Linköping University, all rights reserved SoC of an embedded system DSPs MCU Accelerators L1: RF DP+CP L1: RF DP+CP DP+CP DM1 DMn PM DM1 DMn PM DMn PM I/F DMA DMA I/F DMA I/F SoC connection network and its arbitration / routing / control Main on-chip memory Nonvolatile memory I/F Off-chip DRAM I/F I/F 10/3/2017 Unit 10 of TSEA H1 31

32 Point to point network Traditional bus 2D crossbar network Router IP synthesizer Routing algorithm Round robin Priority arbitration First request first taken HW: Daisy chain Simple data Data link control protocol Data correction protocol Global memory addr. Distributed memory addr. Synch and clocking Driving and speed Copyright of Linköping University, all rights reserved SoC integration (in another course) System-on-chip level hardware integration Interconnection network NoC Connection and arbitrate protocol Data and addressing protocols Physical issues 10/3/2017 Unit 10 of TSEA H1 32

33 Finally: Build a SoC simulator A SoC simulator is the chip behavior model You may not have it, just use FPGA emulator 1.SW architecture: Speed, scalable, debug 2.Cycle accurate/behavior CORE simulation 3.SoC cycle accurate transactional simulation 4.Host adaptation to speed up SoC simulation 10/3/2017 Unit 10 of TSEA H1 33

34 Design for reuse 1. Designed to solve a general problem easily configurable to fit different applications. 2. Designed for use in multiple technologies For soft IP, the synthesis scripts make quality results with different libraries. 3. Designed for simulation with a variety of simulators With both Verilog and VHDL versions, verification test-benches, and work with all the major commercial simulators. 4. Designed with standards-based interfaces Unique or custom interfaces should not be used. 10/3/2017 Unit 10 of TSEA H1 34

35 Design for reuse 5. Verified independently to any SoC IP has full, standalone test-benches, verification suites, full test coverage. 6. Verified to a high level of confidence Need a MPW prototype, in an actual system running real software. 7. Fully documented applications and restrictions valid configurations and parameter values are documented. Any restrictions on configurations or parameter values are clearly stated. Interfacing requirements, restrictions on how the IP can be used are documented. 10/3/2017 Unit 10 of TSEA H1 35

36 Verification 10/3/2017 Unit 10 of TSEA H1 36

37 Verification in general HW Verification is to demonstrate the functional correctness of a design - Janick Bergeron, To prove the consistency between the final functional design and the paper specification. System verification: To verify the application function Hardware verification: To verify the HW compliance Verification versus HW test (fab follows the design) 10/3/2017 Unit 10 of TSEA H1 37

38 Re-convergence path Transformation Specification Design Verification Paper doc Transformation from a paper document Transformation Verification Without re-convergence With re-convergence 10/3/2017 Unit 10 of TSEA H1 38

39 Verification methodology Top HW function specification System verification Partition and bus design Bus level verification Block level design Block level verification RTL coding Classic verification flow Concurrent verification flow 10/3/2017 Unit 10 of TSEA H1 39

40 Compliance test To verify HW not to the system Execute instructions correctly To verify that the design complies with the specification the specification is the hardware design documents. Not the specification of applications. 10/3/2017 Unit 10 of TSEA H1 40

41 Compliance test Check operations following the instruction set manual Consuming the right number of clock cycles Writing back during correct cycles Checking all memory addressing models Checking all register addressing models Checking all branch instructions and conditions Checking all jump target addresses calculations Checking all configurations to every instruction Checking all acceleration functions 10/3/2017 Unit 10 of TSEA H1 41

42 Corner test Corner test Corner means Irregular, designs based on informal methods To limits, cross boundaries, finite precision Find possible corners Data boundary: flags, carry-out, scaling, saturation, overflow, underflow, rounding, forwarding, etc. Address boundary: memory address, stack, register file boundaries Irregular: split / merge bus, fractional +1 problem 10/3/2017 Unit 10 of TSEA H1 42

43 Datapath Corner test (optional) In the integer (fractional) datapath: All data truncation points, data concatenation points All guards, rounds, saturate, and flags All result patterns affecting flag values Corner cases to set and reset each flag Which instructions change / keep flags All cases changing data formats Change data types between ALU and MAC Change other data formats (such as the fractional multiplication, saturation for unsigned) 10/3/2017 Unit 10 of TSEA H1 43

44 Control / M Corner test (optional) All control and status registers are cleaned after system reset (while clocks are off by gating) All registers can be accessed according to the hardware specifications Reaction of all specified exceptions induced by Data dependency, Computing exception Overflow and underflow of the hardware stack FIFO limiters (top and the bottom registers) Corners of memory / register addressing (MAX/MIN) PC corners, values such as destinations of branches Starting/stopping points of hardware loop functions 10/3/2017 Unit 10 of TSEA H1 44

45 Random test Run the same randomly generated test vectors on the behavioral model and the RTL code A result consistency check gives results of the random test The method to run random tests is (1) to generate a random stimuli-set (instruction and data), run on instruction simulator first. (2) to run the same stimuli-set on RTL code (3) to compare results from the instruction set simulator and results from RTL code. 10/3/2017 Unit 10 of TSEA H1 45

46 Real code test Real code test run applications Supply programs and related stimuli to the instruction set simulator to get results / cycle cost The same results and cycle cost should be from the RTL code Test of the C-compiler 10/3/2017 Unit 10 of TSEA H1 46

47 Hierarchical verification Test benches Assembly instruction set simulator = RTL codes 10/3/2017 Unit 10 of TSEA H1 47

48 Test suit and DUT 10/3/2017 Unit 10 of TSEA H1 48

49 Testbench Example (1) clk_gen clk reset_gen reset_n input_gen in_port DUT DSP_Core out_port ouput_save 10/3/2017 Unit 10 of TSEA H1 49

50 Testbench Example (2) clk_gen reset_gen architecture bahav of clk_gen is begin process begin clk <= 1 ; wait for 10 ns; clk <= 0 ; wait for 10 ns; end process; end behav; architecture bahav of reset_gen is signal res_int_n :std_logic begin res_int_n <= 0, 1 after 10 ns; reset_int_n <= reset_n; end behav; 10/3/2017 Unit 10 of TSEA H1 50

51 Testbench Example (3) output_save use ieee.std_logic_textio.all; file output_file : text is out /data/out.txt ; variable l : line; process(clk) begin if (rising_edge(clk)) then write(l, out_port); writeline(output_file, l); end if; end process; input_gen use ieee.std_logic_textio.all; file input_file : text is in /data/in.txt ; variable l : line; variable slv: std_logic_vector(15 downto 0); process(clk) begin if (rising_edge(clk)) then if not (endfile(input_file)) then readline(input_file, l); read(l, slv); in_port <= slv; end if; end if; end process; 10/3/2017 Unit 10 of TSEA H1 51

52 Concepts Copyright of Linköping University, all rights reserved Review on integration behavior function SoC Micro arc RTL layout structure and verification Skills physical Integration and verification Micro architecture Register file ALU: Arithmetic & Logic MAC: MUL and ACC Memory and data access Program flow control Assembly coding tools Firmware plan & design 1. Functional: Be sure that all instructions mapped and can be executed (with available connections). All special registers/ports can be accessed (in)directly 2. Structural: HW arch adapted to instruction-set Combinational: bus matches, width, endian, direction Sequential: pipeline compliance with the specification 3. Physical: speed, power consumption, and cost New hidden critical path, unnecessary toggling or even bugs after integration (missing keeper, default). 10/3/2017 Unit 10 of TSEA H1 52

53 Self reading after the lecture The book was written in 2006, 10 years old. The integration engineering has been very much changed! Follow my slides and take chapter 19, 15, and 16 as references. Essential: Core integration is the essential part and will be in exam. 10/3/2017 Unit 10 of TSEA H1 53

54 Exciting time now! Let us discuss Whatever you want to discuss and related to HW You will have the chance after each lecture (Fö), do take the chance! Prepare your Qs for the next time 10/3/2017 Unit 10 of TSEA H1 54

55 LOGO Welcome to ask any questions you want to I can answer Or discuss together I want to know what you want Dake Liu, Room 554 coridoor B, Hus-B, phone , dake.liu@liu.se