Engineer To Engineer Note

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1 Engineer To Engineer Note EE-167 Technicl Notes on using Anlog Devices' DSP components nd development tools Contct our technicl support by phone: (800) ANALOG-D or e-mil: Or visit our on-line resources nd Introduction to TigerSHARC Multiprocessor Systems Using VisulDSP++ Contributed by Mikel Kokly-Bnnourh April 04, 2003 Introduction The following Engineer-to-Engineer note is intended to give n introduction to Multiprocessor (MP) systems using VisulDSP++. The explntion will be bsed on ssembly code written for the ADDS-TS101S EZ-Kit Lite, consisting of two TigerSHARC Processors, using VisulDSP TigerSHARC Multiprocessor systems cn be configured in different wys: Severl processors shring the externl bus Link Port point-to-point communiction This note will discuss the implementtion of n MP system with the processors shring the externl bus. For more detils on other implementtions plese refer to the TigerSHARC Processor Hrdwre Reference. In ddition to the ssembly code explored throughout this note, n MP code exmple written in C is lso vilble. Linker Description File (LDF) for MP Systems The very first step in setting up n MP system is to crete multiprocessor project using the multiprocessing cpbilities of the linker, nd n LDF file to describe the system. The LDF describes the multiprocessor memory offsets, shred memory, nd ech processor s memory. The following LDF commnds must be considered when writing n MP LDF: MPMEMORY{}, it defines ech processor s offset within multi-processor memory spce (MMS). The linker uses the offsets during multiprocessor linking. MEMORY{}, it defines memory for ll processors present in the system. PROCESSOR{} nd SECTIONS{} commnds define ech processor nd plce progrm sections for ech processor s output file, using the memory definitions. SHARED_MEMORY{}, it is needed when externl shred memory is used in the system. This commnd identifies the output for the shred memory items nd genertes Shred Memory executble files (.SM) tht reside in the shred memory of the MP system. The.SM file is generted from source code file (.ASM,.C or.cpp), which must be included with the project files. This file contins the vrible definitions for the dt tht will be plced in the externl shred memory. LINK_AGAINST(), it resolves symbols within multiprocessor memory nd directs the linker to check specified executbles (.DXEs nd.sms) to resolve vribles nd lbels tht hve not been resolved loclly. Whenever expressions or vribles re defined in the MMS (i.e. internl memory of nother processor in the system) the LINK_AGAINST() commnd must be used in the LDF. Copyright 2003, Anlog Devices, Inc. All rights reserved. Anlog Devices ssumes no responsibility for customer product design or the use or ppliction of customers products or for ny infringements of ptents or rights of others which my result from Anlog Devices ssistnce. All trdemrks nd logos re property of their respective holders. Informtion furnished by Anlog Devices Applictions nd Development Tools Engineers is believed to be ccurte nd relible, however no responsibility is ssumed by Anlog Devices regrding technicl ccurcy nd topiclity of the content provided in Anlog Devices Engineer-to-Engineer Notes.

2 Note: if.sm files nd DXE files re included in the commnd line, the.sm file must be plced first, followed by ll other DXE s, for the linker to be ble to resolve the vribles correctly. The mximum number of processors tht cn be declred in one LDF is rchitecture-specific (i.e. mximum of 8 ADSP-TS101S s). Also note tht combintion of different DSPs with different rchitectures (i.e. ADSP-TS101S nd ADSP ) in the sme LDF is not supported by VisulDSP++. Figure 1Excerpt from nd MP LDF exmple An MP LDF exmple where ll the bove commnds re used is shown in Figure 1. The remining of the LDF file is bsiclly the sme s the defult one provided with the tools (plese refer to the Linker nd Utilities Mnul for TigerSHARC DSPs or to EE-69 Understnding nd Using Linker Description Files (LDFs) for generl description on LDF files). In Figure 1, 2 ADSP-TS101S nd externl shred memory system is defined Now tht the different sections of the LDF hve been discussed, we cn exmine the exmple code tht explores some of the MP cpbilities of the processor. For MP system hrdwre configurtion plese refer to Cluster Bus chpter of the TigerSHARC Processor Hrdwre Reference. Introduction to TigerSHARC Multiprocessor Systems Using VisulDSP++ (EE-167) Pge 2 of 12

3 Multiprocessor Memory Spce (MMS) The multiprocessor memory spce is divided into number of ddress regions (this number is processor specific) tht correspond to the internl memory of the processors in n MP system. The ADSP-TS101S s multiprocessor memory spce ppers in Figure 2. not be used or other thn in specil cses where dt must pss through the TigerSHARC bus interfce. Performing self-multiprocessor red ccess will set the SELF MPROC READ bit in the SYSTAT register s n error indiction for the illegl ccess. Exmple 1 shows source code where the MMS is used to ccess memory loction of nother DSP in the system. In this cse DSP with ID0 ccesses memory loction in ID1 s internl memory. Exmple 1: // Code in ID0 r0=0x ; //M0 Dt in int mem of ID1 Figure 2 ADSP-TS101S s Multiprocessor Memory Spce. Depending on the ddress rnge used, the internl memory of prticulr DSP in the multiprocessor system will be ccessed s source or destintion. Writes to the Brodcst region ccess the memory of ll DSPs in the multiprocessing system. For instnce, ccessing memory loction within the ddress rnge 0x x33FFFFF, is equivlent to ccessing the internl memory of the DSP in the MP system with ID 4. Note: A TigerSHARC s own Internl spce cn be ccessed vi the multiprocessing spce for write trnsctions only. This, however, is performed through the externl bus nd should In exmple 1, the MMS ddress for ID1 is 0x , which is then dded to the ddress corresponding to ID1 s internl memory (0x80000). Therefore, this will result in red ccess of ID0 from ID1 s internl memory. Note: In DSP multiprocessor systems including SDRAM DSP with ID=000 must be present, since this DSP performs the initiliztion (MRS) of the SDRAM. Also, there re issues relted to open drin pull-ups only enbled on the DSP with ID=000. After reset, ID0 becomes the bus mster nd priority rottes in round robin fshion, going up from the present mster. Externl Memory The ADSP-TS101S hs 6Mbits of onchip SRAM memory tht cn store both progrm nd dt. However, some pplictions lso require the use of externl memory devices. Externl memory is widely used in MP systems, nd cn be implemented s shred resource for ll DSPs in the system, or dedicted to prticulr processor. It is very importnt to keep in mind tht ll DSPs in the system must set up the proper ccess mode for the type of memory used in the hrdwre system. The ccess mode is Introduction to TigerSHARC Multiprocessor Systems Using VisulDSP++ (EE-167) Pge 3 of 12

4 progrmmed vi the System Control (SYSCON) register. Defult power up/reset settings for SYSCON re detiled in the TigerSHARC Processor Hrdwre Reference. User defined settings must support the ccess mode pproprite to the memory device(s) tht the user intends to use in their hrdwre systems. SYSCON settings must be the sme cross ll devices shring the cluster bus connection. Note tht SDRAM is gluelessly supported by the ADSP-TS101S. As with the SYSCON register, the SDRAM Configurtion (SDRCON) register of ll processors in the system must be initilized to the sme vlue. Once the DSP s internl memory controller hs been configured, the externl memory cn be ccessed by the DSP vi the externl bus. In this project, SDRAM ws used s n externl shred resource for the two DSPs in the system. The code shown in exmple 2 corresponds to the SDRCON register initiliztion, which, s previously mentioned, must be done by ll DSPs shring the sme externl memory (in this cse, ID0 nd ID1). Exmple 2: // Excerpt from ID0 & ID1: SDRAM Init. j11 = j31 + 0x ;; SDRCON = j11;; // Enble SDRAM: ENA=1,CAS=2CL,pipedepth=0, pge=512w, ref.rte=1200,trp=2,trs=5,init=1 Shred.sm contins the vrible definitions for the dt tht will be plced in externl memory. Note: the DSP with the lowest ID number (nd therefore highest priority in the system) is responsible for initilizing the externl dt defined in the.asm shred memory file during the booting-up sequence. Vector Interrupt (VIRPT) Vector Interrupts re used for interprocessor communiction between host nd DSP or between DSPs. This interrupt is generl-purpose interrupt for nother mster s use. The host (or mster DSP) cn issue vector interrupt to the slve DSP by writing the ddress of n interrupt service routine to the VIRPT register. When serviced, this high priority interrupt cuses the DSP to brnch to the service routine t tht ddress. Exmple 3: // Extrct from ID1: VIRPT Genertion j1 = MMS_ID0 + VIRPT_REG;; xr0 = VIRPT_ISR_ID0 - MMS_ID0;; [j1 += j31]= xr0;; In exmple 3, ID1 triggers vector interrupt in ID0 by writing the ddress of the service routine to be served in ID0 (lbeled VIRPT_ISR_ID0) to the VIRPT register in ID0 (0x = 0x VIRPT ddress + 0x MMS ID0). Note: In cse n externl defined lbel is used for the ISR ddress (like in this exmple, i.e. VIRPT_ISR_ID0), the MMS offset vlue of the DSP serving the interrupt (MMS_ID0) must be subtrcted for the DSP to vector to the ddress of the ISR correctly. This is just n exmple of how inter-processor VIRPT interrupts cn be used s flgs or just to indicte progrm execution completion in MP systems. Bus Lock nd Semphores Semphores re useful for synchronizing tsks performed in n MP system. A semphore is flg, set of dt or memory loction tht cn be ccessed by ny of the DSPs present in the system. In criticl tsks (i.e. should not be interrupted), when ttempting red-modify-write opertion Introduction to TigerSHARC Multiprocessor Systems Using VisulDSP++ (EE-167) Pge 4 of 12

5 on semphore, the DSP must hve bus mstership for the durtion of the opertion. This cn be chieved by using the DSP s bus lock feture, which retins mstership of the bus nd prevents other processors from simultneously ccessing the semphore. A red-modify-write opertion is ccomplished with the following steps (exmple 4): 1. Request bus lock by setting the BUSLK bit in the BUSLK register. 2. Wit for bus mstership to be cquired (condition codes BM nd NBM cn be used). 3. Red the semphore, nd write to it. Exmple 4 is n excerpt from ID0 s code demonstrting the use of Bus Lock in combintion with Brodcst write: Exmple 4: // Excerpt ID0 code: BROADCAST write using // Bus Lock j11 = j31 + 1;; BUSLK = j11;; // Lock the bus BUS_MASTER: if NBM, jump BUS_MASTER;; // Check for bus mstership DCS0 = xr3:0;; yr0 = MMS_Brodcst;; DCD0 = yr3:0;; // Perform Brodcst dt trnsfer j11 = j31 + 0;; BUSLK = j11;; // Relinquish the bus While the BUSLK bit is set, the DSP cn determine if it hs cquired bus mstership by executing conditionl instruction with the Not Bus Mster (NBM) condition code. If it hs become the bus mster, the DSP cn proceed with the externl red or write. If not, it cn either cler its BUSLK bit nd try gin lter, or simply wit until the bus is cquired. Bus lock cn be used in combintion with brodcst writes to implement reflective semphores in multiprocessing system. The reflective semphore (i.e. locted in the DSP s internl memory or n I/O processor register) must be locted t the sme ddress of ech DSP. Once the DSP hs become the bus mster, it performs brodcst write to the specified ddress on every DSP, including itself. Lstly, the BUSLK bit must be clered to free the bus fter the brodcst trnsfer hs finished. Multiprocessor Dt Trnsfers Throughout the code, severl types of externl port (EP) dt trnsfers hve been implemented: 1. Direct Memory Access (DMA) between ID0 nd ID1, 2. DMA from ID0 nd ID1 to externl memory (SDRAM), 3. Core trnsfer from ID1 to ID0, 4. Brodcst Write to ll DSPs in the system. The TigerSHARC includes 14 DMA chnnels, four of which re dedicted to externl memory devices: chnnels 0, 1, 2, nd 3. For detils on DMAs nd how the different dt trnsfers re performed, plese refer to EE-143 Understnding DMA on the ADSP-TS101S TigerSHARC nd the DMA Controller chpter of the TigerSHARC Processor Hrdwre Reference. Let s now exmine the different types of dt trnsfers performed in this specific MP project. Note tht the Brodcst Write hs lredy been discussed in the previous sections. DMA trnsfer from ID0 to ID1 This exmple shows DMA trnsfer from internl memory of ID0 to internl memory of ID1. In this cse, DMA chnnel 0 is used to trnsmit the dt stored in tx_id0 to rx_id1. For this kind of trnsmission, two trnsfer control blocks (TCBs), one for the source nd nother one for the destintion, must be set up. Introduction to TigerSHARC Multiprocessor Systems Using VisulDSP++ (EE-167) Pge 5 of 12

6 Exmple 5 shows the loded vlues into ech TCB using DMA chnnel 0. Note tht the vlue in register xr2/yr2 is irrelevnt due to the fct tht 2-dimensionl DMA is not selected for this prticulr exmple. As soon s both the source nd destintion TCBs re loded with vlues the DMA trnsfer strts. Once the DMA is completed n interrupt occurs nd the _dm_ int vector interrupt routine is then run. Exmple 5: // Excerpt from ID0: DMA0 // Externl Port trnsfer from ID0 to ID1 xr0 = tx_id0;; // xr0=index= ID0 xr1 = 0x ;; // count=0x10,modify=4 xr3 = 0x ;; // int mem,prio=norm, //2D=no,word=qud,int=yes,RQ=enbl,chin=no DCS0 = xr3:0;; // Source yr0 = rx_id1;; // xr0=index= ID1 yr1 = 0x ;; // count=0x10,modify=4 yr3 = 0x ;; // ext mem,prio=norm, //2D=no,word=qud,int=yes,RQ=enbl,chin=no DCD0 = yr3:0;; // Destintion DMA trnsfer from ID0 to SDRAM The trnsfer of the dt from internl memory of ID0 to the SDRAM is executed with minor ltertions to the previous exmple. The source TCB is loded with the sme contents s before (xr3:0) nd the destintion TCB is written with the vlues of registers yr3:0 where yr0 is ltered from rx_id1 to shred_dt. In this cse, DMA chnnel 1 is used for the dt trnsfer by replcing DCS0 nd DCD0 with DCS1 nd DCD1 respectively. Exmple 6: // Excerpt from ID0: DMA0 // Ext Port trnsfer from ID0 to SDRAM DCS1 = xr3:0;; // Sme s before yr0 = shred_dt;; // xr0=index= SDRAM DCD0 = yr3:0;; // Destintion Note: writing to n ctive TCB, i.e. bck-tobck DMA using the sme chnnel before the current trnsfer hs completed, results in n illegl opertion. An error indiction will be flgged in the DMA sttus register (DSTAT). DMA from ID1 to SDRAM As in exmple 6, this is DMA dt trnsfer from internl memory (in this cse from ID1 insted of ID0) to the SDRAM. Agin, the sme concepts pply, where the source nd destintion TCBs re set up s shown in exmple 7. Exmple 7: // Excerpt from ID1: DMA0 // Externl Port trnsfer from ID1 to SDRAM xr0 = tx_id1;; // xr0=index= ID1 xr1 = 0x ;; // count=0x10,modify=4 xr3 = 0x ;; // int mem,prio=norm, //2D=no,word=qud,int=yes,RQ=enbl,chin=no DCS0 = xr3:0;; // Source yr0 = shred_dt+taps;; //xr0=index=sdram yr1 = 0x ;; //count=0x10,modify=4 yr3 = 0x ;; //ext mem,prio=norm, //2D=no,word=qud,int=yes,RQ=enbl,chin=no DCD0 = yr3:0;; // Destintion The source TCB is loded with the sme contents s before (xr3:0) with the only vrition tht the index now points to internl memory of ID1, tx_id1. The destintion TCB is written with the vlues of registers yr3:0 where yr0 now points to shred_dt+taps. TAPS is the offset vlue used to point to the second hlf of the buffer declred in SDRAM to prevent from overwriting the lredy trnsferred dt by ID0. Once gin, DMA chnnel 0 is used. Core trnsfer from ID1 to ID0 Core trnsfer is different wy of hndling dt where no DMA is used. In this cse, the Integer Arithmetic Logic Unit (IALU) is used to directly trnsfer dt from internl memory of ID1 to internl memory of ID0. An exmple of this is shown below: Exmple 8: // Excerpt from ID1: Core trnsfer // from ID1 to ID0 using the IALU jb0 = tx_id1;; // Bse ddress in ID1 j0 = jb0;; // Set index equls to bse jl0 = TAPS;; // Set buffer length Introduction to TigerSHARC Multiprocessor Systems Using VisulDSP++ (EE-167) Pge 6 of 12

7 jb1 = rx_id0;; // Bse register in ID0 j1 = jb1;; // Set index equls to bse jl1 = TAPS;; // Set buffer length j4 = 1;; LC0 = TAPS;; write_ext: // Set loop modifier // loop counter xr0 = CB[j0 += j4];; // red dt from tx_id1 CB[j1 += j4] = xr0;; // write dt to rx_id0 if NLC0E, jump write_ext;; // keep looping until completion Two dt rrys re declred, one in ech DSP s internl memory. ID1 writes to the rry stored in ID0 through MMS (tx_id1 to rx_id0). The IALU registers re used to ccess the two dt buffers to perform the direct dt trnsfer. Some Performnce Considertions Core dt trnsfers re nice nd fst wy of trnsferring words of dt since there is no need to set up trnsfer control block of ny kind. However, DMA is better choice when lrge mounts of dt need to be trnsferred since the core cn be utilized for computtionl processing. Remember tht DMA trnsfers operte in the bckground freeing up the core. ID Checking This routine cn be used to check whether the executble file generted gets loded into the correct DSP in the system. It ensures no ID mismtch. Exmple 9: // Extrct from ID1: ID Checking xr0 = 0x3;; // FEXT opernd xr1 = SYSTAT;; // red SYSTAT xr2 = 1;; // DSP = ID1 xr1 = FEXT R1 by R0;; // get ID vlue xr1 = r2 - r1;; // is DSP ID1? if NAEQ, jump incorrect_id;; // if flse, stop nd enter endless loop Bsiclly, it reds the DSP ID vlue from the SYSTAT register nd it compres it with the theoreticl vlue of the DSP ID. In this cse, the code hs been written for ID1, so it mkes sure it hs been loded into the correct trget tht is DSP 1. If flse, it will enter n endless loop indicting tht n error hs occurred. Multiprocessor Support Debugger VisulDSP++ Multiprocessor Debugger provides the user with full system evlution using the Emultor. The Emultor llows code testing nd evlution on the hrdwre pltform. I/O inter-processor communictions s well s MMS dt trnsfers re supported. MP debugger opertions like MP lod, run or reset provide the user with the cpbility of testing the system with full synchroniztion of ll DSPs. Some of the MP debugger fetures re: Multiprocessor debug commnds llow the user to downlod, reset, restrt, run nd step through the code just like with single-processor commnds, except tht they work synchronously on ll ctive DSPs in the selected MP group. The Debugger provides Multiprocessor Sttus window. This window displys the current sttus of ech DSP in the system: Running, Hlted, or Unknown. The contents of ech debugger window within n MP emultion debugger session reflects the selected DSP, i.e. the window in Focus. By defult, the contents of ech window will chnge depending on which DSP is in focus. The debugger supports Pinning windows (Memory, Registers, etc.) dedicting them to specific DSP in the MP system. This will llow the user to dedicte prticulr debugger window to only disply informtion from one prticulr DSP in the system, s opposed to hving the contents of the window chnge whenever new processor is selected vi the MP Sttus window. The debugger provides Multiprocessor Group window from which the processors cn be grouped into multiple, logicl units upon which Introduction to TigerSHARC Multiprocessor Systems Using VisulDSP++ (EE-167) Pge 7 of 12

8 ll MP commnds re pplied. This window is prticulrly useful when mny processors re present in system nd the user wishes to control/debug subsets of these processors together. Use pinning, nd the processor sttus items in the Multiprocessor window, in conjunction with single-processor debug commnds to debug individul processors in n MP session. Figure 3 Multiprocessor Debugger Support VisulDSP ICE Configurtor The Debugger llows the use of emultor trgets. The DSP In Circuit Emultor (ICE) is development tool for debugging progrms running in rel time on DSP trget system hrdwre. The emultor reds executble files nd lods them into the DSP. The ICE provides controlled environment for observing, debugging, nd testing ctivities in trget system by connecting directly to the trget processor through its JTAG interfce. For the MP system emultion, the Summit- ICE Universl Emultor system ws used. As first step, the MP pltform must be configured using the VisulDSP ICE Configurtor. The Configurtor is used to describe the user s hrdwre pltform to the JTAG emultor. Once pltform hs been described, n emultor trget session cn be bsed upon it. The following steps should be followed when configuring the MP pltform: 1. Open the Visul DSP ICE Configurtor. 2. Crete new pltform. 3. Specify the nme, number nd type of devices to be included s prt of the pltform. These steps re illustrted in Figure 4. Plese be wre of the Initil Reset on Strtup option, which ppers in the Device Properties Introduction to TigerSHARC Multiprocessor Systems Using VisulDSP++ (EE-167) Pge 8 of 12

9 window shown in Figure 4. Enbling this option will perform complete reset on the selected device every time the emultor session is initited. In systems where some settings my need to be preserved (i.e. SDRCON register) this option should be clered. Note: there is lso similr option in the debugger itself, reset before loding executble, which performs complete reset of ll devices in the system upon downloding code to the DSPs. This option cn be found under Settings/Trget Options/. Figure 4 VisulDSP ICE Configurtor ICE Test Utility nd JTAG Scn Test Before getting into the ctul system debugging, the ICE must be tested to mke sure tht hs been properly configured. The ICE Test Utility (Figure 5) is used for this purpose. Open the utility, select the proper emultor I/O ddress, check the continuous scn box nd strt testing. The scn test will then be performed nd the output window would look s follows fter successfully completed scn test: Introduction to TigerSHARC Multiprocessor Systems Using VisulDSP++ (EE-167) Pge 9 of 12

10 Figure 5 VisulDSP ICE Test Utility In cse the test does not complete successfully, n error messge will be displyed with possible solution for the problem. Here is description of some issues tht should be kept in mind for the system design: 1. In multiprocessor system it is impertive tht the JTAG heder is buffered. This will keep the signls clen nd void noise problems tht occur with longer signl trces (ultimtely resulting in relible emultor opertion). 2. In one scn chin, it is not recommended to use more thn eight physicl devices (lthough, theoreticlly, the devices tht cn be supported in one JTAG scn chin by the softwre is bout 50). The recommendtion of not more thn eight physicl devices is mostly due to the trnsmission line effects tht pper in long signl trces, nd bsed on some field-collected empiricl dt. 3. The recommended power-up procedure for the trget nd emultion system is s follows: Power up PC with POD connected to the PC but not the trget. Power up the trget with jumpers on /TRST nd TCK of the JTAG heder. Remove jumpers on /TRST nd TCK from the JTAG heder of trget. Connect POD to JTAG heder of trget. Open VisulDSP++ IDDE. Similrly, the recommended power-down procedure is s follows: Close VisulDSP++ IDDE. Disconnect POD from JTAG heder of trget. Power-down the trget. Replce jumpers on /TRST nd TCK of the JTAG heder of trget (for next power up). Plese refer to EE- 68 Anlog Devices JTAG Emultion Technicl Reference (2.5) for more detiled description on this topic. MP System Emultion Now tht the MP project hs been creted nd the emultor pltform is redy for debugging, we cn begin with the hrdwre emultion. Figure 6 Lod Multiprocessor Processor Window First of ll, the DSP executble files (.DXE s) re downloded to the corresponding DSPs. For MP emultion, Lod Multiprocessor Confirmtion window (Figure 6) ppers. This window enbles the user to select which.dxe file is loded into which DSP. Once the code hs been successfully loded into ech DSP, the system cn be fully evluted using the MP fetures previously described. Introduction to TigerSHARC Multiprocessor Systems Using VisulDSP++ (EE-167) Pge 10 of 12

11 After running the code in both DSPs the user cn view the contents in the dt memory windows nd should be ble to verify tht ll dt trnsfers between the two DSPs hve completed successfully. Figure 7 illustrtes clssicl exmple of some of the MP debugger windows tht cn be viewed when evluting the system. Running code in the DSP trgets (synchronously in both DSPs or independently), setting up brek points, viewing the memory contents, nd system registers re just some of VisulDSP++ Multiprocessor debugger cpbilities. Figure 7 VisulDSP++ Multiprocessor Session Introduction to TigerSHARC Multiprocessor Systems Using VisulDSP++ (EE-167) Pge 11 of 12

12 References [1] TigerSHARC Processor Hrdwre Reference, First Edition, Mrch Anlog Devices Inc. [2] VisulDSP++ Linker & Utilities Mnul for TigerSHARC DSPs, Anlog Devices Inc. [3] VisulDSP++ Emultion Tools Instlltion Guide for Windows 95/98/NT/2000, Anlog Devices Inc. [4] Anlog Devices JTAG Emultion Technicl Reference (2.5) (EE-68), Anlog Devices Inc. [5] Understnding DMA on the ADSP-TS101S TigerSHARC (EE-143), Anlog Devices Inc. Document History Version April 04, 2003 by Mikel Kokly-Bnnourh June 26, 2002 by Mikel Kokly-Bnnourh Description Updted trdemrk usge nd upgrded code exmple ccording to VisulDSP++ relese 3.0 Initil Relese Introduction to TigerSHARC Multiprocessor Systems Using VisulDSP++ (EE-167) Pge 12 of 12

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