Engineer To Engineer Note

Transcription

1 Engineer To Engineer Note EE-148 Technicl Notes on using Anlog Devices' DSP components nd development tools Contct our technicl support by phone: (800) ANALOG-D or e-mil: Or visit our on-line resources nd Introduction to SHARC Multiprocessor Systems Using VisulDSP++ Contributed by Mikel Kokly-Bnnourh April 01, 2003 Introduction The following Engineer-to-Engineer note is intended to give n introduction to Multiprocessor (MP) systems using VisulDSP++ The explntion will be bsed on code exmple written for n MP system, which consists of two ADSP-21160s (2 x ADSP EZ-Kit Bords) using VisulDSP SHARC DSP Multiprocessor systems cn be configured in different wys: Severl DSPs shring the externl bus Link Port point-to-point communiction Use of the DSP s seril ports in multi-chnnel mode. This note will discuss the implementtion of n MP system with the DSPs shring the externl bus. For more detils on other implementtions plese refer to the ADSP SHARC DSP Hrdwre Reference Mnul. Linker Description File (LDF) for MP Systems The very first step in setting up n MP system is to crete multiprocessor project using the multiprocessing cpbilities of the linker, nd n LDF file to describe the system. The LDF describes the multiprocessor memory offsets, shred memory, nd ech processor s memory. The following LDF commnds must be considered when writing n MP LDF: MPMEMORY{}, it defines ech processor s offset within multi-processor memory spce (MMS). The linker uses the offsets during multiprocessor linking. MEMORY{}, it defines memory for ll processors present in the system. PROCESSOR{} nd SECTIONS{} commnds define ech processor nd plce progrm sections for ech processor s output file, using the memory definitions. SHARED MEMORY{}, it is needed when externl shred memory is used in the system. This commnd identifies the output for the shred memory items nd genertes Shred Memory executble files (.SM) tht reside in the shred memory of the MP system. The.SM file is generted from source code file (.ASM,.C or.cpp), which must be included with the project files. This file contins the vrible definitions for the dt tht will be plced in the externl shred memory. LINK_AGAINST(), it resolves symbols within multiprocessor memory nd directs the linker to check specified executbles (.DXEs nd.sms) to resolve vribles nd lbels tht hve not been resolved loclly. Whenever expressions or vribles re defined in the MMS (i.e. internl memory of nother processor in the system) the LINK_AGAINST() commnd must be used in the LDF. Note: if.sm files nd DXE files re included in the commnd line, the.sm file must be plced Copyright 2003, Anlog Devices, Inc. All rights reserved. Anlog Devices ssumes no responsibility for customer product design or the use or ppliction of customers products or for ny infringements of ptents or rights of others which my result from Anlog Devices ssistnce. All trdemrks nd logos re property of their respective holders. Informtion furnished by Anlog Devices Applictions nd Development Tools Engineers is believed to be ccurte nd relible, however no responsibility is ssumed by Anlog Devices regrding technicl ccurcy nd topiclity of the content provided in Anlog Devices Engineer-to-Engineer Notes.

2 first, followed by ll other DXE s, for the linker to be ble to resolve the vribles correctly. The mximum number of processors tht cn be declred in one LDF is rchitecture-specific (i.e. mximum of 6 ADSP s or 2 ADSP L s). Also note tht combintion of different DSPs with different rchitectures (i.e. ADSP nd ADSP-21160) in the sme LDF is not supported by VisulDSP++. However, combintion of DSPs from the sme rchitecture fmily (i.e. ADSP-2106x members such s ADSP-21060, ADSP nd ADSP ) is supported lthough some memory segments definitions considertions must be mde. An MP LDF exmple where ll the bove commnds re used is shown in Figure 1. The reminder of the LDF file is bsiclly the sme s the defult one provided with the tools (plese refer to the Linker nd Utilities Mnul for ADSP-21xxx Fmily of DSPs or to EE-69 Understnding nd Using Linker Description Files (LDFs) for generl description on LDF files). In the following exmple, 2 ADSP nd externl shred memory system is defined. Figure 1 Excerpt from n MP LDF exmple Introduction to SHARC Multiprocessor Systems Using VisulDSP++ (EE-148) Pge 2 of 13

3 Now tht the different sections of the LDF hve been discussed, we cn exmine the exmple code tht explores some of the MP cpbilities of the DSP. For MP system hrdwre configurtion plese refer to chpter 7 of ADSP SHARC DSP Hrdwre Reference. Also for informtion on how to configure cluster system using two ADSP evlution bords refer to the ADSP EZ-KIT Lite User s Guide. Multiprocessor Memory Spce (MMS) The multiprocessor memory spce is divided into number of ddress regions (this number is processor specific) tht correspond to the internl memory of the DSPs in n MP system. The ADSP s multiprocessor memory spce ppers in Figure 2. Note: progrms my only use Norml word ddressing in multiprocessor memory spce. Other ddressing schemes my corrupt vlid dt. Depending on the ddress rnge used, the internl memory of prticulr DSP in the multiprocessor system will be ccessed s source or destintion. Writes to the Brodcst region ccess the memory of ll DSPs in the multiprocessing system. For instnce, ccessing memory loction within the ddress rnge 0x x3FFFFF, is equivlent to ccessing the internl memory of the DSP in the MP system with ID 3. A DSP cn lso use the MMS to ccess its own internl memory by ccessing the corresponding memory region. Note tht in this cse, the DSP reds/writes from/to its own internl memory nd does not mke n ccess on the externl system bus. Figure 2 ADSP Multiprocessor Memory Spce The following is n exmple from the code where the MMS is used to ccess memory loction of nother DSP in the system. In this cse DSP with ID1 ccesses the externl port buffer 1 (EPB1) of DSP with ID2: Exmple 1: r0=0x200006; dm(ei11)=r0; In exmple 1, the MMS ddress for ID2 is 0x200000, which is then dded to the ddress corresponding to the EPB1 (0x6). Therefore, this will result in write ccess to ID2 s EPB1 by n externl device (DSP or host). Note: In DSP multiprocessor systems DSP with ID=001 must be present, since this is the DSP responsible for driving the externl bus control lines stble during reset. Introduction to SHARC Multiprocessor Systems Using VisulDSP++ (EE-148) Pge 3 of 13

4 Externl Memory Externl memory is widely used in MP systems. An importnt point to keep in mind is tht ll DSPs in the system must initilize their own control registers before trying to ccess the externl memory (i.e. WAIT register in cse of SBSRAM). The ADSP cn be gluelessly interfced to synchronous nd synchronous SRAM devices, however the use of DRAM requires n externl controller. It is very importnt to set up the proper ccess mode for the type of memory used in the hrdwre system. The ccess mode is progrmmed vi the WAIT register. Defult power up/reset settings for the System Control (SYSCON) nd WAIT registers re detiled in the ADSP Hrdwre Reference Mnul. User defined settings must support the externl memory ddress rnges tht the user intends to use in their code nd hrdwre systems s well s the ccess mode pproprite to the memory device(s) in use (i.e. synchronous or synchronous ccesses). The MSIZE setting must lso not exceed the size of the ctul physicl memory connected in the user s system. Note tht SDRAM is gluelessly supported by certin devices like the ADSP-21065L nd the ADSP For these cses, specific registers must be initilized prior to ccessing the externl memory. The SDRDIV nd IOCTL, for the ADSP-21065L, nd the SDRDIV nd SDCTL, for the ADSP-21161, registers of ll processors in the system must be initilized to the sme vlue. Once the DSP s internl memory controller hs been configured, the externl memory cn be ccessed by the DSP vi the externl bus. In the exmple project, the shred.sm file contins the vrible definitions for the dt tht will be plced in the externl shred memory. Note: the DSP with the lowest ID number (nd therefore highest externl bus rbitrtion priority in the system) is responsible for initilizing the externl dt defined in the.asm shred memory file during the booting-up sequence. Inter Processor Messges nd Vector Interrupts The Messge Pssing registers (MSGRx) re generl-purpose memory mpped registers tht cn be used for messge pssing between the host nd DSP or between two DSPs. Similrly, Vector Interrupts re used for inter-processor communiction between the host nd DSP or between DSPs. The MSGRx nd VIRPT registers cn be used for messge pssing in the following wys: Messge Pssing. The host (or mster DSP) cn use ny of the 8 messge registers, MSGR0 through MSGR7, to communicte with the DSP. Vector Interrupts. The host (or mster DSP) cn issue vector interrupt to the DSP by writing the ddress of n interrupt service routine to the VIRPT register. When serviced, this high priority interrupt cuses the DSP to brnch to the service routine t tht ddress. Exmple 2: // Excerpt from ID2: VIRPT Genertion I0=0x100001; // VIRPT reg. ddress in ID1 R0=0x40080; // ISR t SFT0I ddress in ID1 will be executed DM(I0,M0)=R0;// write to VIRPT reg.in ID1 [...] // Excerpt from ID1: VIRPT Service Routine // in SFT0I user softwre interrupt vector // ddress BIT SET IMASK VIRPTI; // VIRPT enbled [...] // In vector interrupt tble R0=0x2f2f2f2f; // Vlue for msg. Pssing RTI (DB);// Serve VIRPTI generted by ID2 I0=MSGR0;// Lod ddress of MSGR0 nd write vlue in ID2 DM(MMS_ID2,I0)=R0; [...] Introduction to SHARC Multiprocessor Systems Using VisulDSP++ (EE-148) Pge 4 of 13

5 In exmple 2, ID2 triggers vector interrupt in ID1 by writing the ddress of the service routine to be served in ID1 (0x40080 = SFTOI) to VIRPT (0x = 0x1 VIRPT ddress + 0x MMS ID1). Then, the service routine in ID1 writes test vlue to the MSGR0 register of ID2, using previously defined offset vlue (MMS_ID2 = 0x200000). This is just n exmple of how inter-processor messge pssing nd VIRPT interrupts cn be used s flgs or just to indicte progrm execution completion in MP systems. Bus Lock nd Semphores Semphores re useful for synchronizing tsks performed in n MP system. A semphore is flg tht cn be ccessed by ny of the DSPs present in the system. In criticl tsks (i.e. should not be interrupted), when ttempting red-modify-write opertion on semphore, the DSP must hve bus mstership for the durtion of the opertion. This cn be chieved by using the DSP s bus lock feture, which retins mstership of the bus nd prevents other processors from simultneously ccessing the semphore. A red-modify-write opertion is ccomplished with the following steps (Exmple 3): 1. Request bus lock by setting the BUSLK bit in MODE2. 2. Wit for bus mstership to be cquired. 3. Wit until Direct Write Pending (DWPD) is zero. 4. Red the semphore, test it, nd write to it. The following is n Excerpt from ID1 s code demonstrting the use of Bus Lock nd Brodcst write: Exmple 3: // Excerpt ID1 code: BROADCAST write using // Bus Lock BIT SET MODE2 BUSLK; if NOT BM jump(pc,0); ustt1 = DM(SYSTAT); BIT TST USTAT1 12; if TF jump(pc,-2); b1 = Brodcst_dt; l1 = N; m1 = 1; b8 = MMS_Brodcst; l8 = N; m8 = 1; lcntr = 10; do brodcst_trnsfer until lce; brodcst_trnsfer: r2 = dm(i1,m1); pm(i8,m8) = r2; BIT CLR MODE2 BUSLK; pm(i8,m8) = r2; While the BUSLK bit is set, the DSP cn determine if it hs cquired bus mstership by executing conditionl instruction with the Not Bus Mster (Not BM) condition code. If it hs become the bus mster, the DSP cn proceed with the externl red or write. If not, it cn cler its BUSLK bit nd try gin lter. After bus mstership is cquired, the Direct Write Pending (DWPD) bit s sttus in SYSTAT must be checked to ensure tht semphore write by nother processor is not pending. Bus lock cn be used in combintion with brodcst writes to implement reflective semphores in multiprocessing system. The reflective semphore (i.e. locted in the DSP s internl memory or n I/O processor register) must be locted t the sme ddress of ech DSP. Once the DSP hs become the bus mster, it performs brodcst write to the specified ddress on every DSP, including itself. Lstly, the BUSLK bit must be clered to free the bus fter the brodcst trnsfer hs finished. Multiprocessor Dt Trnsfers Throughout the code, severl types of dt trnsfers hve been implemented: 1. Mster nd Slve Direct Memory Access (DMA) between ID1 nd ID2, Introduction to SHARC Multiprocessor Systems Using VisulDSP++ (EE-148) Pge 5 of 13

6 2. Mster DMA from externl memory, 3. Core trnsfer, 4. Brodcst Write to ll DSPs in the system. Let s now exmine the different types of dt trnsfers performed. Note tht the Brodcst Write hs lredy been discussed in the previous sections Mster nd Slve Direct Memory Access (DMA) between ID1 nd ID2 Setup Mster ID1 A chnnel in this mode cn independently initite internl or externl memory trnsfers. Mster mode pplies to ll externl port DMA chnnels: 10, 11, 12, nd 13. In exmple 4, DMA chnnel 11 ws used to perform Mster DMA trnsfer from ID1 to ID2 s follows: Exmple 4: // Excerpt from ID1:Mster DMA,DMA chnnel // 11, trnsfer from ID1 to ID2 r0=0; dm(dmac11)=r0;// cler DMA Contr Reg r0=dma_source_id1;dm(ii11)=r0;// source ID1 r0=1; dm(im11)=r0; // modifier = 1 r0=10; dm(c11)=r0; // counter = 10 r0=0x200006; dm(ei11)=r0; // write to slve EPB1 r0=0; dm(em11)=r0; // ext. modifier = 0 r0=10; dm(ec11)=r0; // ext. counter = 10 ustt1=0x0404; dm(dmac11)=ustt1; // trnsmit dt ustt1=dm(dmac11); bit set ustt1 0x1; // enble DMA chnnel dm(dmac11)=ustt1; ID1 sets up the chnnel s prmeter registers. The I/O processor uses the EI, EM, nd EC registers to ccess MMS of ID2 in mster mode DMA. ID1 will write to the FIFO (EPB1) in ID2. Note tht the externl modifier is set to zero. To initite mster mode DMA trnsfer ID1 sets the chnnel s DMA enble (DEN) bit. The DSP will then strt trnsferring dt to the EPB1 buffer FIFO, where the slve DSP, in this cse ID2, cn ccess it. ID2 needs to set up the Slve DMA before the dt cn be trnsferred to its own internl memory. Setup Slve ID2 In slve mode DMA chnnel, when the dt trnsfer direction is externl to internl, slve mode DMA chnnel does not initite ny DMA trnsfers until the externl device (in this cse ID1) writes dt to the chnnel s EPB1 buffer FIFO. The Slve DMA trnsfer exmple looks s follows: Exmple 5: // Excerpt from ID2:Slve DMA, DMA chnnel // 11,receive dt trnsmitted by ID1 r0=0; dm(dmac11)=r0;// cler DMA Control Reg. r0=dma_dest_id2; dm(ii11)=r0; // destintion ID2 r0=1; dm(im11)=r0; // modifier = 1 r0=10; dm(c11)=r0; // counter = 10 r0=0x01; dm(dmac11)=r0; // enble to receive dt Note tht the I/O processor does not use the EI, EM, nd EC registers in slve mode DMA. From the previous Mster DMA trnsfer, ID1 trnsmits dt to EPB1 buffer FIFO. ID2 detects tht the dt is present nd performs the DMA trnsfer to internl memory, emptying the EPB1 buffer FIFO. Mster DMA from Externl SBSRAM Note tht in the previous DMA trnsfer, where FIFO (EPB1) is used, mster nd slve DMA need to be configured. A type of Mster DMA where no slve needs to be set up is when the mster writes/reds directly (without use of the EPBx slve FIFOs) from/to Introduction to SHARC Multiprocessor Systems Using VisulDSP++ (EE-148) Pge 6 of 13

7 externl memory. The dvntge of using this type of trnsfer is tht only one DSP needs to be configured. Sme setup cn be used when reding/writing from/to internl memory of the MMS. Note: direct red/write from/to internl memory of the MMS it s not supported by certin devices (ADSP-21065L nd ADSP-21161). These devices ccess internl memory indirectly with the use of DMA. In exmple 6, DMA chnnel 10 ws used to perform the Mster DMA trnsfer from externl SBSRAM to ID1 s internl memory s follows: Exmple 6: // Excerpt from ID1: Mster DMA, DMA chnnel 10, trnsfer from SBSRAM to ID1 r0=0; dm(dmac10)=r0;// cler DMA Control Reg. r0=ext_mem_dt; dm(ei10)=r0; // source SBSRAM r0=1; dm(em10)=r0; // modifier = 1 r0=10; dm(ec10)=r0; // counter = 10 r0=dma_dest_id1; dm(ii10)=r0; // dest. in ID1 s int. mem. r0=1; dm(im10)=r0; // modifier = 1 r0=10; dm(c10)=r0; // counter = 10 ustt1=0x0400; dm(dmac10)=ustt1; // receive dt ustt1=dm(dmac10); bit set ustt1 0x1; // enble DMA chnnel dm(dmac10)=ustt1; Like before, the DSP sets up the chnnel s prmeter registers. The only difference with respect to the previous exmple is tht there is no need to set up slve DMA. The SBSRAM mster mode DMA trnsfer to the internl memory will initite once the chnnel s DMA enble (DEN) bit is set. Core trnsfer Core trnsfer is different wy of hndling dt where no DMA is used. In this cse, the Dt Address Genertors (DAGs) re used to directly trnsfer dt from internl memory of ID2 to internl memory of ID1. An exmple of this is shown below: Exmple 7: // Excerpt from ID2: Core trnsfer,id2 to ID1. b1=dag_source_id2; // Source in ID2 l1=0;m1 = 1; b8=dag_dest_id1;// Dest. in ID1 l8=0; m8 = 1; r2=dm(i1,m1); lcntr = N-1,do DAG_trnsfer until lce; DAG_trnsfer: //Dul ccess in 1 cycle r2 = dm(i1,m1),pm(i8,m8) = r2; pm(i8,m8) = r2; Two dt rrys re declred, one in ech DSP s internl memory. In exmple 7, ID2 ccesses the rry stored in ID1 through the MMS spce. The DAG registers re used to ccess the two dt buffers to perform direct dt trnsfer. Note tht vlues re fetched from both progrm nd dt memory, resulting in dul memory ccess nd executing in just one cycle. Some Considertions Performnce Core dt trnsfers re nice nd fst wy of trnsferring words of dt since the code cn be optimized to trnsfer word of dt per cycle. However, DMA is better choice when lrge mounts of dt need to be trnsferred since the core cn be utilized for computtionl processing. Remember tht DMA trnsfers operte in the bckground freeing up the core. Also, mster DMA trnsfer cn be configured by the slve DSP (or host), incresing performnce in pplictions where the mster DSP might be overloded with processing ctivity. For more detils on DMAs nd dt trnsfer, plese refer to EE-84 SHARC DMA Modes of Opertion nd the I/O Processor Introduction to SHARC Multiprocessor Systems Using VisulDSP++ (EE-148) Pge 7 of 13

8 chpter in the ADSP SHARC DSP Hrdwre Reference Mnul. ID Checking This routine cn be used to check whether the executble file generted gets loded into the correct DSP in the system. This code ensures tht no ID mismtch occurs. Exmple 8: // Excerpt from ID2: ID Checking R0=DM(SYSTAT); // get SYSTAT vlue R1=FEXT R0 BY 8:3; // get the IDC vlue R2=0x2; // ID=2 R1=R1-R2; // is this DSP ID2? IF NE JUMP incorrect_id; // if incorrect jump to endless loop Bsiclly, it reds the DSP ID vlue from the SYSTAT register nd it compres it with the theoreticl vlue of the DSP ID. In this cse, the code hs been written for ID2, so it mkes sure it hs been loded into the correct trget, which is DSP 2. If flse, it will enter n endless loop indicting tht n error hs occurred. Note: loding executble file into wrong DSP will cuse the progrm not to work properly since ll MMS offset vlues will not correspond to the correct ones nd therefore, inter-processor ccesses will fil. Multiprocessor Debugger Support VisulDSP++ Multiprocessor Debugger provides the user with full system evlution using the Emultor. The Emultor llows code testing nd evlution on the hrdwre pltform. I/O inter-processor communictions s well s MMS dt trnsfers re supported. MP debugger opertions like MP lod, run or reset provide the user with the cpbility of testing the system with full synchroniztion of ll DSPs. Note: The VisulDSP++ Simultor llows to fully test the lgorithms nd core code for ech DSP in the system independently. Some of the MP debugger fetures re: Multiprocessor debug commnds llow the user to downlod, reset, restrt, run nd step through the code just like with single-processor commnds, except tht they work synchronously on ll ctive DSPs in the selected MP group. The Debugger provides Multiprocessor Sttus window. This window displys the current sttus of ech DSP in the system: Running, Hlted, or Unknown. The contents of ech debugger window within n MP emultion debugger session reflects the selected DSP, i.e. the window in Focus. By defult, the contents of ech window will chnge depending on which DSP is in focus. The debugger supports Pinning windows (Memory, Registers, etc.) dedicting them to specific DSP in the MP system. This will llow the user to dedicte prticulr debugger window to only disply informtion from one prticulr DSP in the system, s opposed to hving the contents of the window chnge whenever new processor is selected vi the MP Sttus window. The debugger provides Multiprocessor Group window from which the processors cn be grouped into multiple, logicl units upon which ll MP commnds re pplied. This window is prticulrly useful when mny processors re present in system nd the user wishes to control/debug subsets of these processors together. Introduction to SHARC Multiprocessor Systems Using VisulDSP++ (EE-148) Pge 8 of 13

9 Figure 3 Multiprocessor Debugger Support Use pinning, nd the processor sttus items in the Multiprocessor window, in conjunction with single-processor debug commnds to debug individul processors in n MP session. VisulDSP ICE Configurtor The Debugger llows the use of emultor trgets. The DSP In Circuit Emultor (ICE) is development tool for debugging progrms running in rel time on DSP trget system hrdwre. The emultor reds executble files nd lods them into the DSP. The ICE provides controlled environment for observing, debugging, nd testing ctivities in trget system by connecting directly to the trget processor through its JTAG interfce. For the MP system emultion, the Summit-ICE Universl Emultor system ws used. As first step, the MP pltform must be configured using the Visul DSP ICE Configurtor. The Configurtor is used to describe the user s hrdwre pltform to the JTAG emultor. Once pltform hs been described, n emultor trget session cn be bsed upon it. The following steps should be followed when configuring the MP pltform: 1. Open the VisulDSP ICE Configurtor. 2. Crete new pltform. 3. Specify the nme, number nd type of devices to be included s prt of the pltform. These steps re illustrted in Figure 4. Introduction to SHARC Multiprocessor Systems Using VisulDSP++ (EE-148) Pge 9 of 13

10 Plese be wre of the Initil Reset on Strtup option, which ppers in the Device Properties window shown in Figure 4. Enbling this option will perform complete reset on the selected device every time the emultor session is initited. In systems where some settings my need to be preserved (i.e. WAIT register) this option should be clered. Note: there is lso similr option in the debugger itself, reset before loding executble, which performs complete reset of ll devices in the system upon downloding code to the DSPs. This option cn be found under Settings/Trget Options/. Figure 4 VisulDSP ICE Configurtor ICE Test Utility nd JTAG Scn Test Before getting into the ctul system debugging, the ICE must be tested to mke sure tht hs been properly configured. The ICE Test Utility (Figure 5) is used for this purpose. Open the utility, select the proper emultor I/O ddress, check the continuous scn box nd strt testing. The scn test will then be performed nd the output window would look s follows fter successfully completed scn test: Figure 5 VisulDSP ICE Test Utility. Introduction to SHARC Multiprocessor Systems Using VisulDSP++ (EE-148) Pge 10 of 13

11 In cse the test does not complete successfully, n error messge will be displyed with possible solution for the problem. Here is description of some issues tht should be kept in mind for the system design: 1. In multiprocessor system it is impertive tht the JTAG heder is buffered. This will keep the signls clen nd void noise problems tht occur with longer signl trces (ultimtely resulting in relible emultor opertion). 2. In one scn chin, it is not recommended to use more thn eight physicl devices (lthough, theoreticlly, the devices tht cn be supported in one JTAG scn chin by the softwre is bout 50). The recommendtion of not more thn eight physicl devices is mostly due to the trnsmission line effects tht pper in long signl trces, nd bsed on some fieldcollected empiricl dt. 3. The power-on sequence for the trget nd emultion system is s follows: Apply power to the emultor first, then to the trget bord. This ensures tht the JTAG signls re in the correct stte for the DSP to run free. Plese refer to EE-Note 68 Anlog Devices JTAG Emultion Technicl Reference (2.5) for more detiled description on this topic. MP System Emultion Now tht the MP project hs been creted nd the emultor pltform is redy for debugging, we cn begin with the hrdwre emultion. First of ll, the DSP executble files (.DXE s) re downloded to the corresponding DSPs. For MP emultion, Lod Multiprocessor Confirmtion window (Figure 6) ppers. This window enbles the user to select which.dxe file is loded into which DSP. Figure 6 Lod Multiprocessor Processor Window. Once the code hs been successfully loded into ech DSP, the system cn be fully evluted using the MP fetures previously described. After running the code in both DSPs the user cn view the contents in the dt memory windows nd should be ble to verify tht ll dt trnsfers between the two DSPs hve completed successfully. Figure 7 illustrtes clssicl exmple of some of the MP debugger windows tht cn be viewed when evluting the system. Running code in the DSP trgets (synchronously in both DSPs or independently), setting up brek points, viewing the memory contents, nd system registers re just some of VisulDSP++ MP debugger cpbilities. Introduction to SHARC Multiprocessor Systems Using VisulDSP++ (EE-148) Pge 11 of 13

12 Figure 7 VisulDSP++ Multiprocessor Session Introduction to SHARC Multiprocessor Systems Using VisulDSP++ (EE-148) Pge 12 of 13

13 References ADSP SHARC DSP Hrdwre Reference, Anlog Devices Inc. ADSP EZ-KIT Lite User s Guide, Anlog Devices Inc. VisulDSP++ Linker & Utilities Mnul for ADSP-21xxx Fmily of DSPs DSPs, Anlog Devices Inc. VisulDSP++ Users Guide for ADSP21xxx Fmily DSPs, DSPs, Anlog Devices Inc. VisulDSP++ Emultion Tools Instlltion Guide for Windows 95/98/NT/2000, Anlog Devices Inc. Anlog Devices JTAG Emultion Technicl Reference 2.5 (EE-68), Anlog Devices Inc. Understnding nd Using Linker Description Files (LDFs) (EE-69), Anlog Devices Inc. SHARC DMA Modes of Opertion (EE-84), Anlog Devices Inc. Document History Version Mrch 31, 2003 by M.Kokly-Bnnourh October 11, 2001 by M.Kokly-Bnnourh Description Updted document nd code (VisulDSP comptible) Initil Relese Introduction to SHARC Multiprocessor Systems Using VisulDSP++ (EE-148) Pge 13 of 13