Engineer-to-Engineer Note

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1 Engineer-to-Engineer Note EE-179 Technicl notes on using Anlog Devices DSPs, processors nd development tools Visit our eb resources nd or e-mil or for technicl support. ADSP-TS20xS TigerSHARC System Design Guidelines Contributed by Greg F. & John A. Rev 6 July 19, 2006 Introduction This EE-Note discusses specific hrdwre issues when implementing system design, which incorportes ny of the ADSP-TS20xS TigerSHARC processors. This document is provided s n id to hrdwre engineers for designing systems using processors with silicon revisions of 1.0 nd higher. All of the guidelines provided in this EE-Note pply to ADSP-TS201S, ADSP-TS202S, nd ADSP-TS203S TigerSHARC embedded processors. Power Supplies The ADSP-TS20xS processor hs four power supply domins V DD (Internl), V DD_A (Anlog PLL), V DD_IO (Externl I/O) nd V DD_DRAM (DRAM) domin. The V DD_A supply is filtered version of the V DD supply. Refer to the ADSP-TS20xS TigerSHARC Embedded Processor Dt Sheet [1] for more specific detils. VDD Power Supply The V DD power supply pins re used to power ll internl logic except for the internl DRAM, I/O s nd PLL. VDD_A Power Supply The two V DD_A power supply pins re used to directly power the PLL. These pins re isolted from the internl V DD supply pins so dditionl decoupling nd filtering circuits cn be dded to reduce noise. For multiprocessor designs ADI recommends keeping the V DD_A supplies seprte for ech processor. Refer to the V DD_A supply decoupling section for further detils. VDD_IO Power Supply The V DD_IO power supply pins provide power to ll the I/O s including ll the link port LVDS pins. VDD_DRAM Power Supply The V DD_DRAM power supply pins provide power to the internl embedded DRAM logic. Ground (V SS ) Supply The ADSP-TS20xS processor contins single ground supply V SS. The V SS pins re ground returns for the V DD, V DD_A, V DD_DRAM nd V DD_IO supply pins. Power Supply Current The V DD, V DD_A, V DD_DRAM nd V DD_IO power supply currents cn be clculted with the formuls specified in the ppliction note Estimting Power For The ADSP-TS201S (EE-170) [5]. Power Supply Sequencing There re no power sequencing requirements other thn the V DD_DRAM voltge must occur lst. Refer to the ADSP-TS201S TigerSHARC Embedded Processor Dt Sheet [1] for more informtion. Supply Bypss Cpcitors The ADSP-TS20xS processor requires bypss cpcitors on ech supply. In mny cses it is difficult to plce lots of supply bypss cpcitors close to the pckge pins, especilly on the bottom side of the PCB. ADI recommends tht PCB designers prioritize decoupling cpcitor plcement in the following order: 1. V DD_A to V SS bypss cpcitors 2. V DD to V SS bypss cpcitors Copyright , Anlog Devices, Inc. All rights reserved. Anlog Devices ssumes no responsibility for customer product design or the use or ppliction of customers products or for ny infringements of ptents or rights of others which my result from Anlog Devices ssistnce. All trdemrks nd logos re property of their respective holders. Informtion furnished by Anlog Devices Applictions nd Development Tools Engineers is believed to be ccurte nd relible, however no responsibility is ssumed by Anlog Devices regrding technicl ccurcy nd topiclity of the content provided in Anlog Devices Engineer-to-Engineer Notes.

2 3. V DD_DRAM to V SS bypss cpcitors 4. V DD_IO to V SS bypss cpcitors Low-ESR/low-ESL 0.1 µf cpcitors re recommended for proper bypssing. For higher-frequency filtering, 0.01 µf nd µf cpcitors cn lso be used (in ddition to the 0.1 µf cpcitors), provided their inductnce is smll enough. Enough bulk cpcitors must be used to prevent power supply ripple tht exceeds mx/min power supply tolernces (refer to the dt sheet for the pproprite supply tolernces) cused by current trnsients in the system. Severl prllel electrolytic nd/or tntlum cpcitors re preferred in order to minimize ESR nd to provide sufficient cpcitnce. Creful cpcitor plcement nd performing supply ripple nlysis (SPICE nlysis) for ll power supplies (V DD, V DD_A, V DD_DRAM & V DD_IO ) is recommended to ensure dequte decoupling. V DD_A Supply Decoupling The two nlog (V DD_A ) supply pins power the clock genertor PLLs. To produce good stble clock, systems must provide clen power supply to the V DD_A domin. Therefore, the system designer must py criticl ttention to bypssing nd filtering of the V DD_A supply. The decoupling cpcitor plcement for V DD_A should be given first priority over the other supplies. Figure 1 shows the recommended design of the V DD_A filtering circuit. The components used in this circuit should be plced s close s possible to the V DD_A pins to minimize inductnce nd stry cpcitnce. V DD V SS 10uH 1uF Plce s close to pins s possible 1nF HF SMD TS20xS #1 V DD_A V DD_A V SS V DD V SS 10uH 1uF Plce s close to pins s possible 1nF HF SMD TS20xS #N V DD_A V DD_A Figure 1. V DD_A Supply Decoupling It is recommended tht the V DD_A decoupling circuit be duplicted for ech processor in multiprocessor systems. Plce 10 µh inductor nd 1 µf cpcitor together with good connections to V DD, V SS, nd V DD_A. Plce one (minimum) or two 1 nf HF SMD cpcitors s close to the V SS nd V DD_A pckge pins s possible. Mke sure tht the V DD_A PCB trce isn t close to ny noise-generting signls. V SS Mke sure tht the V DD_A PCB trce is isolted from other supply plnes such s V DD_IO nd V DD to minimize noise coupling tht could ffect sensitive nlog circuits. If V DD_A plne exists, it should not be plced directly bove or below V DD_IO /V DD plnes in the PCB lyer stck-up. VDD Supply Decoupling High frequency noise on internl supplies cn dversely ffect the speed of ny device. It is lwys importnt to provide robust supply bypssing for internl supplies especilly for products whose internl voltges re less thn 1.5 V. It is recommended tht s mny highfrequency cpcitors s possible be connected to the V DD supplies s close to the pckge pins s possible. A minimum of 470 µf of bulk low ESR (less thn 25 mω) cpcitors for ech processor connected to the V DD supply is recommended. These cpcitors re used to reduce power supply ripple during high pek trnsient currents. 1. Minimum of six 1 nf high frequency bypss cpcitors locted s close to the pckge pins s possible. 2. At lest two 10 nf bypss cpcitor locted s close to the pckge pins s possible. 3. At lest four 0.1 µf bypss cpcitors locted s close to the pckge pins s possible. 4. A minimum of 470 µf of bulk low ESR (less thn 25 mω) cpcitors for ech processor connected to the V DD supply is recommended. These cpcitors re used to reduce power supply ripple during high pek trnsient currents. Single Electrolytic: Pnsonic FK Series or Snyo OS-CON series Single tntlum: AVX TPS III series Multiple gnged MLC cpcitors: AVX Y5V series Proper V DD supply design is criticl to ensure opertion within the dt sheet specifictions under ll operting conditions. Adhering to the dt sheet V DD nd I DD specifictions will ensure tht no run time system errors will occur due to specifiction violtions. V DD_DRAM Supply Decoupling Below re the miniml recommended bypss cpcitor requirements for single processor s V DD_DRAM supply. All cpcitors should be duplicted for ech processor in the system. ADSP-TS20xS TigerSHARC System Design Guidelines (EE-179) Pge 2 of 13

3 1. Minimum of six 1 nf high frequency bypss cpcitors locted s close to the pckge pins s possible. 2. At lest two 10 nf bypss cpcitor locted s close to the pckge pins s possible. 3. At lest four 0.1 µf bypss cpcitors locted s close to the pckge pins s possible. 4. A minimum of 47 µf of bulk low ESR (less then 100 mω) cpcitors for ech processor connected to the V DD_DRAM supply is recommended. These cpcitors re used to reduce power supply ripple during high pek trnsient currents. Single Electrolytic: Pnsonic FK Series or Snyo OS-CON series Single tntlum: AVX TPS III series Multiple gnged MLC cpcitors: AVX Y5V series V DD_IO Supply Decoupling It is importnt to provide proper decoupling on the V DD_IO supply. Enough bypss nd bulk cpcitors s recommended below must be used to ensure tht the V DD_IO supply specifictions (mx nd min) re not violted. 1. Minimum of six 1 nf high frequency bypss cpcitors locted s close to the pckge pins s possible. 2. At lest two 10 nf bypss cpcitor locted s close to the pckge pins s possible. 3. At lest four 0.1 µf bypss cpcitors locted s close to the pckge pins s possible. 4. A minimum of 100 µf of bulk low ESR (less thn 100 mω) cpcitors for ech processor connected to the V DD_IO supply is recommended. These cpcitors re used to reduce power supply ripple during high pek trnsient currents. Single Electrolytic: Pnsonic FK Series or Snyo OS-CON series Single tntlum: AVX TPS III series Multiple MLC cpcitors: AVX Y5V series V REF Pin The ADSP-TS20xS contins single V REF voltge reference pin. This pin sets the input reference voltge for certin input pins. For the exct list of pins whose threshold is set by V REF refer to the ADSP-TS201S TigerSHARC Embedded Processor Dt Sheet [1]. The V REF voltge should be set to the vlue specified in the dt sheet with recommended circuit in Figure 2 below. All resistor tolernces must be 1%. (For vlues of R1 nd R2, refer to Figure 6 of the ADSP-TS201S TigerSHARC Embedded Processor Dt Sheet [1].) Figure 2. Recommended V REF Circuit In multiprocessor (cluster bus) designs V REF should be shred between ll DSPs. It is importnt to mke sure tht ech processor hs t lest one (preferbly more) 1 nf high speed decoupling cpcitor locted close to the V REF pin. It is lso importnt to keep noise sources from coupling into the V REF signl. SCLK_V REF Pin The ADSP-TS20xS contins single SCLK_V REF voltge reference pin. This pin sets the input reference voltge for the SCLK input pin. The SCLK_V REF voltge should be set to the vlue specified in the dt sheet with the recommended circuit in Figure 3. All resistor tolernces must be 1%. (For vlues of R1 nd R2, refer to Figure 7 of the ADSP-TS201S TigerSHARC Embedded Processor Dt Sheet [1].) Figure 3. Recommended SCLK_V REF Circuit In multiprocessor (cluster bus) designs, SCLK_V REF should be shred between ll DSPs. It is importnt to mke sure tht ech processor hs t lest one (preferbly more) 1 nf high frequency decoupling cpcitor locted close to the SCLK_V REF pin. It is lso importnt to keep ny noise source from coupling into the SCLK_V REF signl. No-Connect (NC) Pins The ADSP-TS20xS contins severl No-Connect (NC) pins. These pins must not connect to ny supply or ground (V DD, V DD_IO, V DD _ A, V DD _ DRAM, or V SS ) nd they must not connect to ny other NC pin. All NC pins must be left totlly unconnected. ADSP-TS20xS TigerSHARC System Design Guidelines (EE-179) Pge 3 of 13

4 Configurtion Pins The ADSP-TS20xS configurtion pins SCLKRAT2-0, ID2-0, CONTROLIMP1-0 nd DS2-0 re used to select vrious chip functions such s PLL clock rtio, chip-id nd output impednce. These pins typiclly hve either n internl pull-up or pull-down resistor. All configurtion pins must hve constnt vlue while the ADSP-TS20xS is powered. hen using the defult configurtion, no externl connection is needed; the pin should be treted s NC (No Connect). For ll other configurtions (non defult), the pin must be connected to V DD_IO or V SS directly or through sufficiently strong resistor. In multi-processor designs where configurtion pins re likely to be wired together (SCLKRAT2-0 connected to severl processor s) mke sure tht proper vlue of resistor is used to override the defult pull-down/up. Note tht the totl resistor vlue is divided by the number of processors. For initil or prototype designs it is dvntgeous to hve pds on the PCB for populting strp resistors to chnge the defult setting for ll the SCLKRAT2-0, CONTROLIMP1-0 nd DS2-0 pins. Configurtion pins, which hve defult pull-ups, should hve resistor pds between the pin nd V SS nd defult pull-downs should hve resistor pds between the pin nd V DD_IO. CONTROLIMP1-0 Configurtion Pins The CONTROLIMP0 pin hs n internl pull-down resistor nd CONTROLIMP1 hs n internl pull-up resistor. These pins control output driver impednce. Refer to Tble 12 of the ADSP-TS201S TigerSHARC Embedded Processor [1] Dt Sheet for more informtion on the CONTROLIMP1-0 pin vlues. For ll designs it is recommended to set the CONTROLIMP1-0 pins to vlue of 00 (Norml), since this is the only mode supported by IBIS model simultion. DS2-0 Configurtion Pins The DS2 nd DS0 pins contin n internl pull-up resistor. DS1 contins n internl pull-down resistor. These pins control the drive strength of the ADSP-TS20xS output drivers. For further informtion refer to the ADSP-TS201S TigerSHARC Embedded Processor Dt Sheet [1] nd the ppliction note User Guide to ADSP-TS201S TigerSHARC processor IBIS files (EE-198) [7]. SCLKRAT2-0 Configurtion Pins The SCLKRAT2-0 pins contin n internl pull-down resistor. These pins set the PLL multiplier, which genertes the core clock from the SCLK input. For more informtion on the mximum SCLK duty cycle specifictions, nd mx/min SCLK frequency specifictions, refer to the ADSP-TS201S TigerSHARC Embedded Processor Dt Sheet [1]. ID2-0 Configurtion Pins The ID2-0 pins hve n internl pull-down resistor. In single processor systems nd in multiprocessor designs where the cluster bus is not connected to ny other ADSP- TS20xS device, the ID pins should be set to the defult vlue (000). This is becuse internl pull-up/pull-downs on certin pins, like memory interfce nd bus rbitrtion re enbled only when the ID2-0 = (000). Setting the processor ID2-0 pins to (000) elimintes the need for externl resistors. Refer to ADSP-TS201S TigerSHARC Embedded Processor Dt Sheet [1] for more detils. Note tht ID2-0=[000] is the only processor which cn enble SDRAM nd strt the MRS sequence. In multiprocessor designs where the cluster bus is shred between TS20xS devices, ech processor must be progrmmed to unique device ID strting with ID2-0 = (000) nd incrementing upwrds. Tble 1 nd the figures below describe the vrious configurtions nd ID2-0 ssignments. ID2-0 Multiprocessor ID 000 (defult) Tble 1. ID2-0 Configurtion Options ADSP-TS20xS TigerSHARC System Design Guidelines (EE-179) Pge 4 of 13

5 Figure 4. No Cluster Bus Connection Between TS20x Processors. (All Processor ID s Must Be 0) Figure 5. Cluster Bus Connection Between TS20x Processors. (All Processor ID s Must Be Unique) Strp Pins: /BMS,/BM,TMR0E,/BUSLOCK The ADSP-TS20xS processor contins four dul-purpose strp pins /BMS, /BM, TMR0E nd /BUSLOCK. These strp pins select the boot-mode, SYSCON/SDRCON write enble, link port width nd interrupt (edge/level). These strp pins lso hve dditionl functionlity fter reset. hen the defult configurtion is used, no externl resistor is needed. For ll other configurtions, sufficiently strong resistor (typiclly 500 Ω) connected to V DD_IO is required. Do not strp these pins directly to ny supply or ny other pin. Due to the lck of determinism in the smple point nd output enble for the strp pins, they must not be driven by n FPGA, ASIC, or other device. An externl pullup or pulldown of sufficient strength must be used to set the desired vlue. Refer to Tble 16 ( Pin Definitions I/O Strp Pins ) nd Tble 17 ( Strp Pin Internl Resistors ) of the ADSP-TS20xS TigerSHARC Embedded Processor Dt Sheet [1] for more informtion. Test Mode Strp Pins (Link Port) There re three specil test strp pins /L1BCMPO, /L2BCMPO nd /L3BCMPO, which enble test mode functions. These pins re the Link Port 1, 2, nd 3 s Block Completion output signls. All FPGAs nd some ASICs three-stte their pins before they re progrmmed. During this time, some FPGAs nd/or ASICs typiclly turn on n internl pull-up or pulldown resistor. These resistors re used to keep signls from floting to mid-scle before progrmming. It is importnt to mke sure tht the FPGA or ASIC which connects to Link Port 1, 2, or 3 s Block Completion pins doesn t hve ny internl pull-down resistors ctive while /RST_IN is sserted (low). If the FPGA or ASIC hs pull-up this is ok. Note tht only link ports 1, 2, nd 3 hve specil test mode strps. (Plese note tht the ADSP-TS203S processor does not hve link port 2 nd 3.) If only one link port requires connection to n FPGA or ASIC, use link port 0 since this Link Port Block Completion signl doesn t hve ny test mode strps ssocited with it. Due to the lck of determinism in the smple point nd output enble for the strp pins, they must not be driven by n FPGA, ASIC, or other device. An externl pullup or pulldown of sufficient strength must be used to set the desired vlue. If under ny circumstnces, t the rising edge of reset (dessertion edge), if ny of the 3 test mode Block Completion signls hs vlue other thn logic-1 processor test mode will be enbled. Refer to Tble 16 ( Pin Definitions I/O Strp Pins ) of the ADSP-TS20xS TigerSHARC Embedded Processor Dt Sheet [1] for more informtion. To ssist in debugging it is recommend tht designers include n option for plcing three optionl pull-down resistors (typiclly 500 Ω) between the Test Mode Strp pins nd V SS. It is lso recommended tht designers include n option for plcing three optionl pull-up resistors (typiclly 500 Ω) between the Test Mode Strp pins nd V DD_IO. These resistors cn be dded or removed to enble nd disble ech specific test mode signl. ADSP-TS20xS TigerSHARC System Design Guidelines (EE-179) Pge 5 of 13

6 Test Mode Description TM1 TM2 TM3 CCLK/4 on pin /L0BCMPO SOCCLK/2 on pin /L1BCMPO SCLK on pin /L2BCMPO Strp Pin /L1BCMPO /L2BCMPO /L3BCMPO Tble 2. Link Port Test Mode Strp Options (ADSP-TS201/ADSP-TS202) Test Mode Description TM1 TM2 TM3 CCLK/4 on pin /L0BCMPO SOCCLK/2 on pin /L1BCMPO SCLK on pin TM2 Strp Pin /L1BCMPO TM2 TM3 Tble 3. Link Port Test Mode Strp Options (ADSP-TS203) SCLK Pin After power-up the SCLK signl should not stop running unless the reset signl (/RST_IN) is sserted. If SCLK needs to stop following the power-up sequence, /RST_IN must lso get sserted. hen re-strting the SCLK from this condition, follow the sme guidelines s the power-up sequence. SCLK Distribution In single nd multiprocessor designs creful clock design nd distribution is required to ensure proper nd full-speed internl nd externl opertion. Listed below re some guidelines for clock distribution. PCB connections should be point-to-point from the clock buffer output to ll clock inputs. Trce lengths should be mtched (+/- 125 mils) to minimize skew. Cpcitnce on ll clock signls should be mtched within 5%. Minimize the number of PCB vis. Mintin sme number of vis on ech clock signl. Do not run clock signls close to other signls on sme lyer. Keep t lest 4x minimum spcing to other signls. Do not run ny signls directly bove or below the clock signls. Use high qulity low-jitter clock source for generting the clock reference. Use low-jitter clock buffer driver. Use low output-to-output skew clock buffer driver. All clock signls from the clock buffer outputs to the SCLK inputs should be crefully reviewed. A single, multiple-output clock buffer should be used to drive the clock signls to ll devices including DSPs, FPGAs, ASICs nd Memories. Using multiple clock buffer chips increses the clock-to-clock skew between clock signls nd is not recommended. Single Mtched PCB Length CLOCK BUFFER CLOCK CLK#0 TigerSHARC ID=0 SOURCE CLK#1 TigerSHARC ID=1 CLK#7 CLK#8 TigerSHARC ID=7 Other Devices (Memory, Host) Figure 6. Recommended Clock Distribution Method CLOCK SOURCE Two or more CLOCK BUFFERS Mtched PCB Length CLK#0 CLK#5 CLK#6 CLK#8 TigerSHARC ID=0 TigerSHARC ID=5 TigerSHARC ID=6 Other Devices (Memory, Host) Figure 7. Clock Distribution SCLK Design Considertions Creful nlysis is required when choosing components for generting, buffering nd distributing the SCLK signls on PCB. Refer to the ADSP-TS20xS dt sheet specifiction for SCLK input jitter requirements. Single-stge or dul-stge clock tree designs re typiclly used to crete clock distribution network. Figure 8 shows couple of exmples of these types of designs. OSC Dul-Stge BUF CLK1 CLKn Single-Stge CLKGEN & BUF Figure 8. Clock Genertion Exmples CLUSTER BUS CLUSTER BUS CLK1 CLKn ADSP-TS20xS TigerSHARC System Design Guidelines (EE-179) Pge 6 of 13

7 In most instnces single stge clock designs provide lower jitter specifictions nd tighter duty-cycle control thn dul or multi-stge clock designs. It is very importnt to simulte ll designs, however dul nd multi-stge designs require specil ttention when nlyzing totl jitter (OSC jitter & BUF jitter) nd duty cycle impct. In some cses jitter is dditive, therefore 100 ps OSC jitter ps BUF jitter could result in 250 ps totl pek-to-pek jitter. In some BUF products, however, some input jitter is filtered out resulting in only frction of the input jitter being dded to the inherent BUF jitter. Designers should review mnufcturer dt sheets nd ppliction notes before choosing Oscilltors, Crystls nd clock driver components to ensure they meet the jitter, rise/fll time, nd duty cycle requirements for the SCLK of the ADSP- TS20xS. It is importnt to ensure tht the SCLK_V REF reference voltge complies with the dt sheet specifiction. It is importnt to note tht the duty cycle of SCLK is dependent upon the SCLK_V REF voltge setting. Other fctors to consider: hen selecting components, the output-to-output skew between vrious clock buffer outputs should be s smll s possible to ensure high speed opertion of the externl bus interfce. Mke sure the output rise nd fll times of clock drivers re symmetricl. Review power supply grid nd supply decoupling for ll clock genertion components. Signl integrity nlysis should be run on ll clock signls to ensure no externl coupling nd they meet or exceed the SCLK specifictions. Reset Pins There re four externl pins /RST_IN, /RST_OUT, /POR_IN nd /TRST ssocited with the reset circuitry of the ADSP-TS20xS. Three of the pins /RST_IN, /RST_OUT nd /POR_IN re ssocited with resetting the core nd internl DRAM. These pins must be configured s shown in Figure 9 below. The /TRST pin is the JTAG nd Emultor reset pin. ADI recommends designers plce 0 Ω resistor between /RST_OUT nd /POR_IN. This provides useful plce for connecting trigger to logic-nlyzer or oscilloscope for debugging potentil system problems. RESET CIRCUIT 0 Ohm /RST_IN /RST_OUT /POR_IN DSP #1 /RST_IN /RST_OUT /POR_IN DSP #N Figure 9. Hrdwre Reset Pin Connections /RST_IN is the chip hrdwre reset pin, /RST_OUT is delyed nd synchronized internl version of /RST_IN nd /POR_IN is used to reset the internl DRAM. In multiprocessor designs, the /RST_IN signl must be connected to ll devices to provide common reset sequence. Ech processor should connect its /RST_OUT pin to its /POR_IN pin. It is required tht the circuit supplying /RST_IN should hold the signl sserted (low) when the power supply is rmping up to its stble vlue. The ADSP-TS20xS hs four types of resets; Power-Up Reset, Norml Reset, Core Reset nd JTAG/Emultor Reset. Power-Up Reset Refer to the Power-Up Reset Timing nd Norml Reset Timing sections of the ADSP-TS201S TigerSHARC Embedded Processor Dt Sheet [1] for specific timing on the /RST_IN nd SCLK pins. All strp nd test mode pins re smpled 14 SCLK cycles fter /RST_IN is de-sserted. Refer to the ADSP-TS201S TigerSHARC Embedded Processor Dt Sheet [1] for exct timing when theses pins re ltched. Norml Reset Norml Reset is defined s ny chip reset (ssertion of /RST_IN) following the initil Power-Up Reset. The supplies, SCLK nd other signls must be stble. Core Reset hen setting the SRST bit in the register EMUCTL, the processor core is reset, but not the externl ports or I/O. This is sometimes referred to s softwre reset. /TRST Boundry Scn nd Emultor Reset The /TRST reset pin not only resets the IEEE Boundry Scn port but it lso provides the reset signl for ADSP-TS20xS TigerSHARC System Design Guidelines (EE-179) Pge 7 of 13

8 the Emultor interfce. This signl requires specil considertions if the Emultor or Boundry Scn port is being used. Refer to ppliction note Anlog Devices JTAG Emultion Technicl Reference (EE-68) [4] for more informtion. Boundry Scn nd Emultor Pins The ADSP-TS20xS hs six pins ssocited with the Boundry Scn nd Emultor interfce. The pins, /EMU, TCK, TDI, TDO, TMS nd /TRST should be connected to Boundry Scn pod connector if the ADSP-TS20xS emultor is used. To get detiled nd updted informtion on this subject, plese refer to engineering note Anlog Devices JTAG Emultion Technicl Reference (EE-68) [4]. Cluster Bus Pins In single processor system, the ID2-0 pins of the single processor must be set to 000. In multiprocessor system, the processor IDs must be uniquely ssigned strting from 000 up to 111 ; single TigerSHARC cluster cn gluelessly support up to 8 DSPs. For both single nd multiple processor topologies, it is impertive to include processor ID2-0 = 000 in the system, since this processor supports the following fetures upon reset: Hs ctive internl pull-ups or pull-downs on certin externl signls when ID2-0= 000 (processor ID 0). See ADSP-TS201S TigerSHARC Embedded Processor Dt Sheet [1] for detils. Is the defult bus mster, nd cn therefore provide ctive bus rbitrtion signls to n externl host processor. Hs n on-chip SDRAM controller, which provides n MRS sequence to ny externl SDRAM present in the system. If there is n externl host on the cluster bus nd common dt re shred between the host nd the TigerSHARC processor(s), the endiness on both sides must be mtched to ech other. Note, the TigerSHARC processor is only little endin nd does not support big endin. processor nd host. Floting in this cse mens tht these inputs re not driven by ny source. The ADSP-TS20xS contins internl pull-up resistors to ensure busses don t flot under these conditions. If either the host or externl memory bus widths re configured s 64-bits, then the multiprocessing memory spce must be configured s 64-bits s well. If externl wit-stte mode is used, plese ensure tht no contention on the ACK signl occurs. Link Ports Pins The ADSP-TS201S nd ADSP-TS202S contin four full-duplex Link Ports, wheres the ADSP-TS203S contins only two full-duplex Link Ports. Ech link port s receive nd trnsmit sections operte independently nd my or my not be used or connected to other link prtners. If link ports re used then ll link port pins must be connected between link prtners. The only exception is for 1-bit dt mode opertion. Refer to the following sections for connecting or terminting the trnsmit nd receive link port. Trnsmit Link Port Connections The trnsmit link port connections should follow the guidelines provided in the ADSP-TS20x dt sheet. Note tht the /LxBCMPO pins for trnsmit link ports 1, 2 nd 3 cn lterntely be used for test mode strps. Refer to the Test Mode Strp Pins (Link Port) section of this document for more detils. In cses where only one dt trnsmit signl pir is used, the remining 3 trnsmit pirs should be left unconnected. Pin Nme LxDATO3-0P/N LxCLKOUTP/N LxACKI Pin Connection Link Prtner Link Prtner Link Prtner /LxBCMPO Link Prtner * Tble 4. 4-bit Trnsmit Link Port The TigerSHARC processor s ddressing is word-oriented (32-bit). Some host processors ddressing is byteoriented. Therefore, for connecting to these processors the lest-significnt bit of the TigerSHARC processor s ddress bus should be connected to the third lest-significnt bit of the host processor s ddress bus, regrdless if 32-bit or 64-bit bus width is specified. The ddress nd dt busses my flot for severl cycles during bus-mstership trnsitions between TigerSHARC ADSP-TS20xS TigerSHARC System Design Guidelines (EE-179) Pge 8 of 13

9 Pin Nme LxDATO3-1P/N LxDATO0P/N LxCLKOUTP/N LxACKI Pin Connection NC Link Prtner Link Prtner Link Prtner /LxBCMPO Link Prtner * Tble 5. 1-bit Trnsmit Link Port * Refer to Test Mode strp section for informtion on providing PCB pds for optionl resistor plcement for system debug. The Link Ports on revision 1.2 silicon incorporte n internl 100 Ω terminting resistor cross the LVDS P/N clock nd dt pin pirs on the link port input pins (i.e. the receiver pin pirs). For silicon revision 1.2 nd newer, if the system requires link port operting frequency bove 400 MHz, it is recommended to include the option for externl terminting resistors. These resistors llow for PCB design risk reduction in pplictions with link port operting frequency bove 400 MHz, nd should therefore not be populted initilly. Receive Link Port Connections The receive link port connections should follow the guidelines provided in the ADSP-TS20x dt sheet. If receive link port is used, ll pins must be connected with the exception of the three unused dt pin pirs when using 1-bit wide dt port. These three unused dt pin pirs should be terminted s explined in the dt sheet. Pin Nme LxDATI3-0P/N LxCLKINP/N LxACKO /LxBCMPI Pin Connection Link Prtner Link Prtner Link Prtner Link Prtner For silicon revisions 1.0 nd 1.1, ech LVDS receive pir tht is connected to link prtner requires n externl 100 Ω 1% terminting resistor. These resistors must be plced s close to the receiving link port pins s possible. Tble 6. 4-bit Receive Link Port Pin Nme Pin Connection LxDATI3-1P/N V DD_IO LVDS Tx P N 100 Ohm 1% Externl LVDS Terminting Resistor P N LVDS Rx LxDATI0P/N LxCLKINP/N LxACKO /LxBCMPI Link Prtner Link Prtner Link Prtner Link Prtner Link Trnsmitter PCB Routing Link Receiver Tble 7. 1-bit Receive Link Port Figure 10. LVDS Receive Termintion (For Silicon Revisions 1.0 nd 1.1) For silicon revisions 1.2 nd newer with frequency of link port opertion t or below 400 MHz, the externl 100 Ω 1% terminting resistor is not required. Using FPGAs with Link Ports Some pplictions my require the initiliztion of n FPGA before inititing Link Port trnsmission. An FPGA should not drive the /LxBCMPI input high to the processor until the LxCLKIN is stble nd in logic high stte. It is recommended to include n externl pulldown in the design to override ny pullup resistor internl to the FPGA tht my be enbled during its initiliztion. Link Port LVDS PCB Guidelines Figure 11. LVDS Receive Termintion (For Silicon Revisions 1.2 nd Newer with Frequency of Link Port Opertion At or Below 400MHz) PCB trces should be optimized for 100 Ω differentil impednce. Connections should be point-to-point from the Link Port source to the Link Port destintions. Trce ADSP-TS20xS TigerSHARC System Design Guidelines (EE-179) Pge 9 of 13

10 lengths should be mtched to minimize skew. All trce lengths should be +/- 250 mils. This limits PCB trce delys to +/- 50 ps. For high-speed 4-bit Link Port opertion, plce the Link Port clock signls between the four sets of LVDS dt signls DATA0-P DATA0-N DATA1-P DATA1-N VDD or VSS Plne CLK-P CLK-N DATA2-P DATA2-N DATA3-P DATA3-N Figure Bit Link Port Clock Plcement Minimize the number of PCB vis. Vis reduce signl integrity. Additionl stub length cn cuse unwnted reflections. No signls or vis between LVDS pirs. SIGNAL Supply/Gnd plne VIA Supply/Gnd plne Figure 13. No Signls Between LVDS Signl Do not plce ny closely spced signls or vis between djcent LVDS pirs unless creful nlysis is done. VDD or VSS Plne SIGNAL or VIA Figure 14. No Signls Between LVDS Pirs No 90 degrees ngles for LVDS routing. Use 45- degree bends nd mintin constnt width nd spce between ll LVDS pirs nd spcing between djcent LVDS pirs. 90 degrees not recommended S S S 45 degrees recommended Figure 15. No 90-Deg Angles for LVDS signls Do not run ny signls under or bove LVDS pirs. LVDS "P" SIGNAL LVDS "N" SIGNAL SIGNAL SIGNAL SIGNAL LVDS "P" SIGNAL LVDS "N" SIGNAL Figure 16. No Signls Above/Below LVDS Signls Plce LVDS differentil signls on the top or bottom lyer of the PCB if possible. A solid supply or ground plne directly underneth the LVDS signls is lso required. This configurtion is typiclly referred to s MicroStrip. LVDS "P" "MicroStrip" Supply/Gnd Plne LVDS "N" Figure 17. MicroStrip Exmple If plcement of LVDS signls is not possible on the top or bottom lyers of the PCB, it is cceptble to sndwich the LVDS lyers in between supply nd/or ground plnes. This configurtion is referred to s StripLine. VDD or VSS Plne "StripLine" AC ground Plnes Figure 18. StripLine Exmple ADSP-TS20xS TigerSHARC System Design Guidelines (EE-179) Pge 10 of 13

11 Although the StripLine topology significntly reduces EMI, it does hve some drwbcks. (Supply / Ground Plne) 1. Difficulty mintining constnt impednce 2. Higher propgtion dely (~1 ½ times) 3. My require dditionl vis nd lyers S D S It is recommended tht the supply nd/or ground plne extend pst the edges of ll LVDS signls. P N H P N Supply/Gnd Plne LVDS "P" LVDS "N" Figure 19. Supply Plne Overlp of LVDS Signl If Non-LVDS (single ended) signl must run on the sme plne s LVDS signls, ground or supply trce should be inserted between the LVDS signl nd the Non-LVDS signl. LVDS "P" Supply/Gnd Plne LVDS "N" Supply/Gnd Signl Stripline (Supply / Ground Plne) Figure 22. StripLine PCB Guidelines = idth of PCB trce S = Spce between LVDS pir. D = Distnce between LVDS pirs D = Spce to ground or supply plne edge D = Distnce to neighboring supply trce H = Height between signl nd next lyer Note: The following PCB (S, D nd H) Rtios re lso required. Optimize the differentil impednce of 100 Ω. S < 2 D, D >= 2S H > S Figure 20. Non LVDS Signl to LVDS Distnce Below re some industry stndrd guidelines for LVDS signl routing. LVDS Pir S LVDS Pir D S Booting To understnd the booting process for ech of the boot modes in further detil, plese refer to TigerSHARC processor engineering note ADSP-TS20x TigerSHARC Processor Boot Loder Kernels Opertion (EE-200) [8]. After reset, the ADSP-TS20xS hs four boot options for beginning opertion: EPROM Boot, Host Boot, Link Port Boot, nd No Boot. P N P N H Microstrip (Supply / Ground Plne) Figure 21. MicroStrip PCB Guidelines EPROM Boot Mster Boot Mode, TigerSHARC processor strts ctively fetching externlly. The ADSP-TS20xS processor defults to EPROM booting depending on the vlue of the /BMS strp pin. hen the processor is configured to boot from EPROM, /BMS is ctive during the boot sequence nd should be connected to the chip select signl of the EPROM. For dditionl informtion refer to the /BMS strp pin section. ADSP-TS20xS TigerSHARC System Design Guidelines (EE-179) Pge 11 of 13

12 Host Boot Slve Boot Mode: TigerSHARC processor expects code to be plced internlly. The ADSP-TS20xS processor supports booting from n externl mster (host or nother ADSP-TS20xS). Any mster on the cluster bus cn boot the ADSP-TS20xS through writes to its internl memory or through uto DMA. For host boot, plce sufficiently strong resistor (typiclly 500 Ω) between /BMS nd V DD_IO. Link Port Boot Slve Boot Mode: TigerSHARC processor expects code to be plced internlly. All four receive link port DMA chnnels re initilized fter reset to trnsfer 256-word block to internl memory ddresses 0 through 255, nd to issue n interrupt t the end of the block (similr to n externl port DMA). The corresponding DMA interrupts re set to ddress zero. For dditionl informtion refer to the /BMS nd TMR0E strp pin sections. For Link Port boot plce sufficiently strong resistor (typiclly 500 Ω) between /BMS nd V DD_IO. No Boot Mster mode: TigerSHARC processor will strt from IRQ vector (externlly or internlly) fetching dt. The ADSP-TS20xS processor will begin execution from the memory ddress selected with one of the /IRQ3-0 interrupt signls. Using the no boot option, the ADSP- TS20xS will strt running from memory when one of the interrupts is sserted. For dditionl informtion refer to the /BMS nd /BM strp pin sections. For No boot (boot from memory ddress) plce sufficiently strong resistor (typiclly 500 Ω) between /BM to V DD_IO nd plce sufficiently strong resistor (typiclly 500 Ω) between /BMS to V DD_IO. Miscellneous Items It is importnt to run PCB signl integrity nlysis for ll signls in single or multiprocessor ADSP-TS20xS bsed systems. References [1] ADSP-TS201S TigerSHARC Embedded Processor Dt Sheet, Anlog Devices, Inc. ADSP-TS202S TigerSHARC Embedded Processor Dt Sheet, Anlog Devices, Inc. ADSP-TS203S TigerSHARC Embedded Processor Dt Sheet, Anlog Devices, Inc. [2] ADSP-TS201S TigerSHARC Processor Hrdwre Reference, Anlog Devices, Inc. [3] ADSP-TS201S TigerSHARC Processor Progrmming Reference, Anlog Devices, Inc. [4] Anlog Devices JTAG Emultion Technicl Reference (EE-68). Anlog Devices, Inc. [5] Estimting Power For The ADSP-TS201S (EE-170), Anlog Devices, Inc. [6] Therml Relief Design for the ADSP-TS20xS TigerSHARC Processor (EE-182), Anlog Devices, Inc. [7] User Guide to ADSP-TS201S TigerSHARC processor IBIS files (EE-198) [8] ADSP-TS20x TigerSHARC Processor Boot Loder Kernels Opertion (EE-200), Anlog Devices, Inc. [9] Considertions for Porting Code from the ADSP-TS101S TigerSHARC Processor to the ADSP-TS201S TigerSHARC Processor (EE-205), Anlog Devices, Inc. ADSP-TS20xS TigerSHARC System Design Guidelines (EE-179) Pge 12 of 13

13 Document History Version Rev 6 July 19, 2006 by Greg F. & Steve F. Rev 5 August 12, 2005 by Greg F. & Steve F. Rev 4 Jnury 5, 2005 by Greg F. Rev 3 My 19, 2004 by John A. & Phil G. Rev 0.6 October 23, 2003 by Phil G. Rev 0.5 October 22, 2003 by Greg F., John A. & Phil G. Description Modified Strp Pins section Modified Test Mode Strp Pins section Added Using FPGAs ith Link Ports section Modified Supply Bypss Cpcitors section Modified Link Port Pins Section Modified Trnsmit Link Port section Modified Receive Link Port section Modified for production silicon. Updted link port section for rev 1.2 silicon. Updted SCLK_Vref informtion per dt sheet spec Discussing Rev 1.0 Silicon Revised title from ADSP-TS201S TigerSHARC System Design Guidelines to ADSP-TS20xS TigerSHARC System Design Guidelines First relesed version ADSP-TS20xS TigerSHARC System Design Guidelines (EE-179) Pge 13 of 13