Design Rules for PCB Layout Using Altium Designer

Transcription

1 Design Rules fr PCB Layut Using Altium Designer 1.0 Intrductin The Department currently has an in-huse facility fr making PCBs which permits bards t be made relatively quickly at lw cst. This facility des have sme limitatins, thugh, which in turn places sme cnstraints upn PCB layut. This dcument utlines these cnstraints and hw t implement them. It als discusses hw t check yur wrk, hw t save it, as well as what yu need t d in rder t have yur PCB design made. Depending n wh will manufacture yur PCB there will be certain manufacturing limitatins, which in turn will place cnstraints n yur PCB layut. These cnstraints can be easily satisfied by altering sme f the default design rules in Altium. This dcument utlines sme f the mst imprtant cnstraints and hw t implement them. It als discussed hw t check yur wrk, hw t save it, as well as what yu need t d in rder t have yur PCB design made. Subsequent sectins f this dcument discuss the fllwing aspects: Minimum clearance between all tracks, pads and cmpnents. Interactive ruting track width & via sizes Track widths fr different nets (supply nets, signal nets etc) Ruting via style Plygn prperties if using a plygn plane Silk t slder mask & silk t silk clearance Cmpnent pad sizes PCB utline, munting requirements and identificatin Design rule checking Saving yur wrk Submitting yur design 2.0 Additinal Things t nte if PCB is Made In-Huse If yu wish t use ECE department s an in-huse PCB facility, a few aspects need t be clarified. It des have a simple setup hwever there are sme additinal limitatins impsed n yur PCB layut. Firstly, the department s in-huse facility can nly make single-sided PCBs r duble-sided (using bth tp layer & bttm layers) PCBs. Hwever, we currently des nt have the capability t d plated thrugh hles (PTH). Fr duble-sided bards this means that any required cnnectin between a bttm-layer track and a tp-layer track happens by means f either a wire r a cmpnent lead sldered n bth the tp & bttm layers. In the latter case, ne needs

2 t ensure that sldering n the tp layer is actually pssible. This is nt the case fr many cmpnents, including cnnectrs & electrlytic capacitrs. S it is imprtant t ensure that any cmpnent that cannt be sldered n the tp layer des nt have a tp layer track cnnected t it. Secndly, the Department des nt have the facility t autmatically drill yur bard nce it has been made. Yu will need t d this yurself using drilling facilities available in the Department. 3.0 Minimum Clearance between all tracks, PADs and cmpnents. T tggle between Metric and Imperial units press Q. In the PCB editr windw select Design >> Rules & then duble click n Electrical categry t expand it). Then duble click n Clearance type t display clearance rules. Finally click n the rule named Clearance - see Figure 1. If using metric units, Minimum Clearance shuld be 0.5 mm. If using Imperial units, Minimum Clearance shuld be 20 mil. Change the minimum clearance value accrdingly. It may be a gd idea t setup a separate design rule fr minimum clearance between plygn purs and tracks/pads (fr example 0.8mm) t make it easier t slder (especially if there is n slder mask). Mre infrmatin can be fund in the Altium help files Figure 1 Setting the Minimum Clearance value

3 4.0 Track Widths fr different nets (e.g., supply nets, signal nets) Select Design >> Rules & then duble click n Ruting categry t expand it. Then duble click n Width t display width rules. Finally click n the rule named Width - see Figure 2. If using metric units set minimum track width t 0.5mm & preferred & maximum width t whatever yu want (may be.7 & 5mm, respectively) If using imperial units set minimum track width t 20 mil & preferred & maximum width t whatever yu want (may be 30 & 200 mil, respectively) Yu can select different track widths fr different nets (e.g. yu culd make supply tracks large & all thers set t the minimum width). Mre infrmatin can be fund in the Altium help files. Figure 2 Setting track widths Once this rule is set up, yur default track width will be always same as yur preferred track width. Otherwise by default the track width will be minimum track width & this may nt be preferred in mst f the cases.

4 5.0 Ruting Via Style Select Design >> Rules & then duble click n Ruting categry t expand it. Then duble click n ruting via style t display width rules. Finally click n the rule named Ruting Via, see Figure 3. Set the minimum via diameter t 1.2mm, preferred via diameter t 1.7mm & maximum via diameter t 2.2mm Set the minimum via hle size t 0.6mm, preferred via hle size t 0.7mm & maximum via hle size t 1mm Figure 3 Setting via size

5 6.0 Plygn Prperties if using a plygn plane Select Design >> Rules & then duble click n Plane categry t expand it. Then duble click n Plygn Cnnect Style categry. Then click n Plygn Cnnect. In this menu change Cnnect Style t Relief Cnnect - see Figure 3. Change Cnnectr Width t 0.5mm and Air Gap Width t 0.5mm. If yu have used planes fr ruting high pwer tracks then yu may add anther rule t have these use Direct Cnnect style. Figure 4 Setting Plygn prperties

6 7.0 Silk Clearances Select Design >> Rules & then duble click n Manufacturing categry t expand it. Then duble click n Silk T Slder Mask Clearance and then click SilkTSlderMaskClearance In this menu change the clearance value t 0.1mm Then Duble click n Silk T Silk Clearance and then click SilkTSilkClearance In this menu als change the clearance value t 0.1mm Nte that yu can make bth f these values t 0mm if yu want t ignre all the silk errrs in yur design. Figure 5 Setting Silk Clearance 8.0 Hle size Be default the hle size (diameter) is 2.54mm which is nt enugh fr munting hles. This setting needs t be changed in design rules.

7 Select Design >> Rules & then duble click Manufacturing categry t expand it. Then duble click n Hle Size and then click n Hle Size. In this menu change the maximum hle size t 6mm. Figure 6 Setting hle size 9.0 Cmpnent Pad Sizes Generally yu need t make sure that PAD sizes are as large as pssible. This is imprtant when it cmes t drilling the PCB nce it has made as well as when the bard is being sldered. Make use f the fllwing guidelines fr selecting PAD sizes: If using axial resistrs with a 0.8 mm drill hle, then the PAD diameter shuld be at least 1.6mm r mre. if using a cnnectr with a lead diameter f 0.9 mm, yu will need a drill hle size f 0.9mm and a PAD diameter f at least 1.7mm (i.e., if using circular pads). Or yu can select the PAD shape t suit yur design. Fr a hle size larger than 1mm, use a PAD diameter f 2mm.

8 Fr ICs, the hle size is nrmally 0.8 mm, but because the pins f an IC are adjacent t each ther, in rder t get maximum clearance between PADs, use val shaped PADs rather than rund. This can be achieved by setting the X size dimensin f a PAD t be larger than the Y size. Fr example, fr a 14 pin DIP package, use PAD X size = 2mm and PAD Y seize = 1.5mm, with a hle dimensin = 0.8mm. Fr ther cmpnents which are placed very clse t each ther, yu shuld als select val PADs in rder t ensure maximum clearance between pads If yu are using cmpnents frm the manufacturer s Libraries, make sure that the PAD sizes are mdified t suit the abve guidelines. In rder t change the PAD parameters, duble click n the PAD yu want t change and then change the parameters accrdingly - see Figure 4. Yu can change multiple PADs at the same time using the Inspectr Panel. Fr further details, use Altium help n Inspectr panel. Figure 7 Changing the parameters f a PAD

9 10.0 PCB Outline, Munting Requirements and Identificatin The fllwing precautins shuld be taken when designing a PCB. PCB Outline Make sure that this is well defined and drawn in the Keep Out layer PCB Munting Requirements Yu need t give careful thught as t hw yur PCB will be munted and factr this int yur design. This may be by way f munting hles (use sizes f 3mm r 4mm typically). But ther methds f PCB munting are als acceptable. PCB Identificatin T facilitate in identifying & distributing PCBs nce they are made, make sure that yur PCB is identified in the fllwing manner: Part IV prject students: Curse Number / Prject N. examples: EE 401 / Prj 95, CS 401 / Prj 83, SE 401 / Prj 16 Part III design students: Curse N. / Grup N. examples: EE 310 / Grp 12, CS 301 / Grp 5 All thers: write their UPI r PCB title (whichever is cnvenient) The text used fr identificatin can be placed either n the tp r bttm layers. If placed n the Bttm layer, it shuld be mirrred, but if n the Tp layer, it shuld nt Design Rule Checking Once yu have cmpleted yur PCB design, yu need t verify that it cmplies with the design rules. D this as fllws: Chse Tls >> Design Rule Check & then click n Run Design Rule Check Design Rule check highlights any design vilatins in yur design. If yu have cmplied with all the design rules, there shuld be n rule vilatins. Hwever, if in yur design yu have rule vilatins make sure t fixe these issues befre submitting yur PCB Submitting Yur Design fr Manufacture Befre submitting yur design fr manufacture, yu shuld cmplete the check list cntained in Appendix A. Once yu have cmpleted yur PCB design, yu need t send the PCB file (.pcbdc) t the prject technician/submit via drp-bx setup fr the curse s that yur PCB can be made.

10 APPENDIX A Design Check List Make sure that yu have ticked each item in the fllwing check list befre yu submit the PCB. If yur PCB des nt cmply with any f these requirements it will nt be accepted fr manufacturing. Clearance (set t 0.5mm r 20mil) Track width set t minimum f 12mil r mre Plygn Setting (if used) Silk Clearance Cmpnent PAD sizes used as per the guide PCB Outline dne PCB Munting Methd PCB Identificatin Design Rule checked