CS359: Computer Architecture. The Processor (A) Yanyan Shen Department of Computer Science and Engineering
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1 CS359: Computer Architecture The Processor (A) Yanyan Shen Department of Computer Science and Engineering
2 Eecuting R-type Instructions 7 Instructions ADD and subtract add rd, rs, rt sub rd, rs, rt OR Immediate: ori rt, rs, imm6 LOAD and STORE lw rt, rs, imm6 sw rt, rs, imm6 BRANCH: beq rs, rt, imm6 JUMP: j target op rs rt rd shamt func 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits op rs rt immediate 6 bits 5 bits 5 bits 6 bits 3 26 op target address 6 bits 26 bits 2
3 Datapath of RR(R-type) op rs rt rd shamt func 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits RTL:R[rd] R[rs] op R[rt] Eample: add rd, rs, rt RegWr busw Clk rd rs rt Rw Ra Rb -bit Registers busa busb ctr:add/sub Result Ra, Rb, Rw correspond to rs, rt, rd ctr,regwr: control signal What are controls signals for add rd, rs, rt? ctr=add,regwr= 3
4 I-type instruction(ori) ADD and subtract add rd, rs, rt sub rd, rs, rt OR Immediate: ori rt, rs, imm6 LOAD and STORE lw rt, rs, imm6 sw rt, rs, imm6 BRANCH: beq rs, rt, imm6 JUMP: j target op rs rt rd shamt func 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits op rs rt immediate 6 bits 5 bits 5 bits 6 bits 3 26 op target address 6 bits 26 bits 4
5 RTL: The OR Immediate Instruction op rs rt immediate 6 bits 5 bits 5 bits 6 bits ori rt, rs, imm6 M[PC] Instruction Fetech R[rt] R[rs] or ZeroEt(imm6) zero etension of 6 bit constant or R[rs] PC PC + 4 update PC Zero etension ZeroEt(imm6) bits immediate 6 bits 5
6 Datapath of Immediate Instruction R[rt] R[rs] op ZeroEt[imm6]] Eample: ori rt, rs, imm op rs rt immediate 6 bits 5 bits 5 bits 6 bits Write the results of R-Type instruction to Rd Why need multipleor here? Rd Rt RegDst Mu Don t Care RegWr 5 Rs 5 5 (Rt) ctr busw busa Rw Ra Rb -bit Result Registers Clk busb imm6 ZeroEt 6 Ori control signals:regdst=?;regwr=?;ctr=?;src=? Ori control signals:regdst=; RegWr=;str=or; Src= Mu Src 6
7 Datapath for lw (memory access instruction) ADD and subtract add rd, rs, rt sub rd, rs, rt OR Immediate: ori rt, rs, imm6 LOAD and STORE lw rt, rs, imm6 sw rt, rs, imm6 BRANCH: beq rs, rt, imm6 JUMP: j target op rs rt rd shamt func 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits op rs rt immediate 6 bits 5 bits 5 bits 6 bits 3 26 op target address 6 bits 26 bits 7
8 RTL: The Load Instruction 3 lw rt, rs, imm op rs rt immediate 6 bits 5 bits 5 bits 6 bits M[PC] Instruction Fetch Addr R[rs] + SignEt(imm6) Compute the address R[rt] M [Addr] PC PC + 4 Load Data to rt Update PC Why using signed etension rather than zero etension? bits bits immediate 6 bits immediate 6 bits 8
9 Datapath for Load Instruction R[rt] M[ R[rs] + SignEt[imm6] ] Eample: lw rt, rs, imm op rs rt immediate 6 bits 5 bits 5 bits 6 bits Rd Rt RegDst Why? Mu Don t Care Rs RegWr ctr (Rt) MemtoReg busa Rw Ra Rb busw -bit Clk Registers busb MemWr WrEn Adr Data In imm6 Data 6 Clk Memory Src Et Mu EtOp :zero etension,: sign etension What RegDst=, are control RegWr=, signals ctr=add, -- RegDst, EtOp=, RegWr, ctr, Src=, EtOp, MemWr=, Src, MemWr, MemtoReg= MemtoReg? Mu 9
10 SW instruction ADD and subtract add rd, rs, rt sub rd, rs, rt OR Immediate: ori rt, rs, imm6 LOAD and STORE lw rt, rs, imm6 sw rt, rs, imm6 BRANCH: beq rs, rt, imm6 JUMP: j target op rs rt rd shamt func 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits op rs rt immediate 6 bits 5 bits 5 bits 6 bits 3 26 op target address 6 bits 26 bits
11 RTL: The Store Instruction op rs rt immediate 6 bits 5 bits 5 bits 6 bits sw rt, rs, imm6 M[PC] Addr R[rs] + SignEt(imm6) Mem[Addr] R[rt] PC PC + 4
12 Datapath for SW M[ R[rs] + SignEt[imm6] R[rt] ] Eample: sw rt, rs, imm6 RegDst busw RegWr Clk Rd Rt Mu imm Rs 5 Rw Ra Rb -bit Registers op rs rt immediate 6 bits 5 bits 5 bits 6 bits Why add this? Rt ctr MemWr busa busb Data In WrEn Adr Data Src Clk Memory Et Mu MemtoReg Mu EtOp RegDst=, RegWr=, ctr=add, EtOp=, Src=, MemWr=, MemtoReg= 2
13 Beq ADD and subtract add rd, rs, rt sub rd, rs, rt OR Immediate: ori rt, rs, imm6 LOAD and STORE lw rt, rs, imm6 sw rt, rs, imm6 BRANCH: beq rs, rt, imm6 JUMP: j target op rs rt rd shamt func 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits op rs rt immediate 6 bits 5 bits 5 bits 6 bits 3 26 op target address 6 bits 26 bits 3
14 RTL: The Branch Instruction op rs rt immediate 6 bits 5 bits 5 bits 6 bits beq rs, rt, imm6 M[PC] Cond R[rs] - R[rt] Compare rs and rt if (COND eq ) Calculate the net instruction s address PC PC ( SignEt(imm6) 4 ) else PC PC + 4 4
15 Datapath for beq beq rs, rt, imm6 We need to compare Rs and Rt! op rs rt immediate 6 bits 5 bits 5 bits 6 bits Branch Clk PC Rd Rt RegDst Mu imm6 Net Addr Rs Rt RegWr ctr Logic busa Rw Ra Rb busw -bit Zero To Instruction Clk Registers busb Memory imm6 Q: How to design the addressing logic? 6 EtOp Src Et Mu RegDst=, RegWr=, ctr=sub, EtOp=, Src=, MemWr=, MemtoReg=, Branch= 5
16 Instruction Fetch Unit at the End of Branch op rs rt immediate 6 if (Zero == ) then PC = PC SignEt[imm6]*4 ; else PC = PC + 4 Branch Inst Memory Adr Instruction<3:> Zero imm6 4 PC Et Adder Adder MUX ctrl PC Mu clk busw Clk RegWr Rs Rt Rw Ra Rb -bit Registers busb busa ctr Zero 6
17 Jump Operation ADD and subtract add rd, rs, rt sub rd, rs, rt OR Immediate: ori rt, rs, imm6 LOAD and STORE lw rt, rs, imm6 sw rt, rs, imm6 BRANCH: beq rs, rt, imm6 JUMP: j target op rs rt rd shamt func 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits op rs rt immediate 6 bits 5 bits 5 bits 6 bits 3 26 op target address 6 bits 26 bits 7
18 Eecuting Jump Operations Jump operation involves replace the lower 28 bits of the PC with the lower 26 bits of the fetched instruction shifted left by 2 bits Add 4 4 PC Instruction Memory Read Address Instruction 26 Shift left 2 28 Jump address 8
19 Single Cycle Datapath (Without Jump) 4 Add Op Instr[3-26] Control Unit Branch Src Shift left 2 Add PCSrc MemRead MemtoReg MemWrite PC Read Address Instruction Memory Instr[3-] RegDst Instr[25-2] Instr[2-6] Instr[5 -] Read Addr Register Read Read Addr 2 Data File Write Addr Write Data RegWrite Read Data 2 ovf zero Address Data Memory Write Data Read Data Instr[5-] Sign 6 Etend control Instr[5-] 9
20 Step 4: Adding the Control Selecting the operations to perform (, Register File and Memory read/write) Controlling the flow of data (multipleor inputs) Observations op field always in bits 3-26 R-type: addr of registers J-type: to be read are always specified by the op target address rs field (bits 25-2) and rt field (bits 2-6); for lw and sw rs is the base register addr. of register to be written is in one of two places in rt (bits 2-6) for lw; in rd (bits 5-) for R-type instructions offset for beq, lw, and sw always in bits op rs rt rd shamt funct I-Type: op rs rt address offset
21 R-type Instruction Data/Control Flow 4 Add Op Instr[3-26] Control Unit Branch Src Shift left 2 Add PCSrc MemRead MemtoReg MemWrite PC Read Address Instruction Memory Instr[3-] RegDst Instr[25-2] Instr[2-6] Instr[5 -] Read Addr Register Read Read Addr 2 Data File Write Addr Write Data RegWrite Read Data 2 ovf zero Address Data Memory Write Data Read Data Instr[5-] Sign 6 Etend control Instr[5-] 2
22 Load Word Instruction Data/Control Flow 4 Add Op Instr[3-26] Control Unit Branch Src Shift left 2 Add PCSrc MemRead MemtoReg MemWrite PC Read Address Instruction Memory Instr[3-] RegDst Instr[25-2] Instr[2-6] Instr[5 -] Read Addr Register Read Read Addr 2 Data File Write Addr Write Data RegWrite Read Data 2 ovf zero Address Data Memory Write Data Read Data Instr[5-] Sign 6 Etend control Instr[5-] 22
23 Branch Instruction Data/Control Flow 4 Add Op Instr[3-26] Control Unit Branch Src Shift left 2 Add PCSrc MemRead MemtoReg MemWrite PC Read Address Instruction Memory Instr[3-] RegDst Instr[25-2] Instr[2-6] Instr[5 -] Read Addr Register Read Read Addr 2 Data File Write Addr Write Data RegWrite Read Data 2 ovf zero Address Data Memory Write Data Read Data Instr[5-] Sign 6 Etend control Instr[5-] 23
24 Adding the Jump Operation 4 Add Instr[25-] 26 Op Instr[3-26] Shift left 2 Control Unit 28 Branch PC+4[3-28] Jump Src Shift left 2 Add PCSrc MemRead MemtoReg MemWrite PC Read Address Instruction Memory Instr[3-] RegDst Instr[25-2] Instr[2-6] Instr[5 -] Read Addr Register Read Read Addr 2 Data File Write Addr Write Data RegWrite Read Data 2 ovf zero Address Data Memory Write Data Read Data Instr[5-] Sign 6 Etend control Instr[5-] 24
25 Assemble Control Logic Instruction<3:> Inst Memory Adr <:5> <:5> <6:2> <2:25> <2:25> Op Fun Rt Rs Rd Imm6 Decoder npc_sel RegWr RegDst EtOp Src ctr MemWr MemtoReg Equal DATA PATH 25
26 A Summary of the Control Signals func We Don t Care :-) op add sub ori lw sw beq jump RegDst Src MemtoReg RegWrite MemWrite Branch Jump EtOp ctr<2:> Add Subtr Or Add Add Subtr R-type op rs rt rd shamt func add, sub I-type op rs rt immediate ori, lw, sw, beq J-type op target address jump 26
27 The Concept of Local Decoding Two levels of decoding: Main Control and Control RegDst Src MemtoReg RegWrite MemWrite Branch Jump EtOp ctr op op 6 How many bits will N need? R-type ori lw sw beq jump Add/Subtr Or Add Add Subtr Main Control R, or, +, -, and, func 6 op N=? 3, why? Control (Local) ctr 3 ctr is determined by op and func, while other control signals are determined by op 27
28 The Decoding of the func Field op 6 Main Control Encoding op as follows func 6 op N Control (Local) ctr R-type ori lw sw beq jump op (Symbolic) R-type Or Add Add Subtr op<2:> R-type rs rt rd shamt func func<5:> Instruction Operation ctr ctr<2:> Operation add Add subtract Subtract and or And Or set-on-less-than Subtract 28
29 The Truth Table for ctr R-type Instructions determined by funct Non-R-type Instructions determined by op op R-type ori lw sw beq (Symbolic) R-type Or Add Add Subtr op<2:> funct<3:> Instruction Op. add subtract and or set-on-less-than op func bit2 bit bit bit<3> bit<2> bit<> bit<> Operation ctr bit<2> bit<> bit<> Add Subtract Or Add Subtract And Or Subtract 29
30 The Logic Equation for ctr<> Choose the rows with ctr[]= op func bit<2> bit<> bit<> bit<3> bit<2> bit<> bit<> ctr<> This makes func<3> a don t care ctr<> =!op<2> & op<> + op<2> &!func<2> & func<> &!func<> 3
31 The Logic Equation for ctr<> Choose the rows with ctr[]= op func bit<2> bit<> bit<> bit<3> bit<2> bit<> bit<> ctr<> ctr<> =!op<2> & op<> &! op<> + op<2> &!func<3> & func<2> &!func<> 3
32 The Logic Equation for ctr<2> Choose the rows with ctr[2]= op func bit<2> bit<> bit<> bit<3> bit<2> bit<> bit<> ctr<2> ctr<2> =!op<2> & op<> &!op<> + op<2> &!func<3> & func<2> &!func<> & func<>
33 Summary of Control Logic of Local Control func 6 op 3 Contro l (Local) ctr 3 ctr<> =!op<2> & op<> + op<2> &!func<2> & func<> &!func<> ctr<> =!op<2> & op<> &!op<> + op<2> &!func<3> & func<2> &!func<> ctr<2> =!op<2> & op<> &!op<> + op<2> &!func<3> & func<2> &!func<> & func<> 33
34 The Truth Table for the Main Control op 6 Output of Main Control Input of main control Main Control RegDst Src : op 3 func 6 Control (Local) op R-type ori lw sw beq jump RegDst Src MemtoReg RegWrite MemWrite Branch Jump EtOp op (Symbolic) R-type Or Add Add Subtr op <2> op <> op <> ctr 3 34
35 The Truth Table for RegWrite op R-type ori lw sw beq jump RegWrite RegWrite = R-type + ori + lw =!op<5> &!op<4> &!op<3> &!op<2> &!op<> &!op<> (R-type) +!op<5> &!op<4> & op<3> & op<2> &!op<> & op<>(ori) + op<5> &!op<4> &!op<3> &!op<2> & op<> & op<>(lw) op<5>.. op<5>.. op<5>.. op<5>.. op<5>.. op<5>.. <> <> <> <> <> op<> Decoder R-type ori lw sw beq jump RegWrite 35
36 Assemble Main Control (PLA) op<5>.. op<5>.. op<5>.. op<5>.. op<5>.. op<5>.. <> <> <> <> <> op<> Decoder R-type ori lw sw beq jump RegWrite Src RegDst MemtoReg MemWrite Branch Jump EtOp op<2> op<> op<> 36
37 The Complete Single Cycle Data Path with Control op 6 Instr<3:26> RegDst busw Clk RegWr Main Control Rd Mu imm6 Instr<5:> Rt 5 5 Rs 5 Rw Ra Rb -bit Registers 6 op RegDst Src : Rt busb Et Branch Jump Clk busa 3 Instr<5:> Mu ctr Src func Instruction Fetch Unit Data In 6 Clk Zero Instruction<3:> Rt <2:25> Control WrEn Rs MemWr Data <6:2> Adr Memory ctr Rd <:5> 3 <:5> Imm6 MemtoReg Mu EtOp 37
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