Routers implementations

Transcription

1 Routers implementtions Switching Technology S L - Router implementtions Generl of routers Functions of n IP router Router rchitectures Introduction to routing tble lookup L - 2

2 Generl of routers Router is network equipment, which performs pcket switching opertions opertes t network lyer of the OSI protocol reference model switches/routes vrible length pckets routing decisions bsed on ddress informtion crried in pckets Router is used to connect two or more networks tht my or my not be similr Routers communicte with ech other by mens of routing messges to exchnge routing informtion resolve next hop ddresses mintin network topology to mke routing decisions L - 3 IPv4 pcket structure Version - IP version number IHL - Internet heder length in 32- bit words (min. size = 5) TOS - type of service (guidnce to end-system IP modules nd router long trnsport pth) Length - totl length (heder + pylod) of IP pcket in octets Identifier - sequence number, which together with ddress nd protocol fields identify ech IP pcket uniquely 2 octets Ver. IHL TOS Length Identifier Flg Frgment offset Time to live Protocol Heder checksum Source ddress (32 bits) Destintion ddress (32 bits) Options + pdding Dt field Flg - used in connection with frgmenttion: more bit indictes whether this frgment is the lst one of frgmented pcket nd don t frgment bit inhibits/prohibits pcket frgmenttion Frgment offset - indictes where in the originl user dt messge this frgment belongs, mesured in 64-bit units (ll but lst the frgment hs dt field tht contins multiple of 64-bit pylod) Time-to-live - defines the mximum time in seconds pcket cn be in trnsit cross the Internet (decremented by ech visited router by defined mount) Protocol - indictes the type of protocol (TCP, UDP, etc.) crried by the IP pcket Heder checksum - crries checksum clculted over the heder bits L - 4

3 IPv6 pcket structure Version - version number of IP protocol Trffic clss - Clss-of-service (CoS) priority of the pcket Flow lbel - identifies ll pckets belonging to specific flow (requiring specific CoS), nd routers cn identify these pckets nd hndle them in similr fshion. A flow is uniquely identified by the combintion of source ddress nd non-zero flow lbel. 4 octets Version Trffic clss Flow lbel Pylod length (6) Next heder (8) Source ddress (28 bits) Destintion ddress (28 bits) Dt field Hop limit (8) Pylod length - indictes the number of octets in the pylod field Next heder - indictes the type of dditionl (extension) heder following the min heder Hop limit - vlue for the mximum number of hops the pcket is llowed to trvel in network L - 5 Router implementtions Generl of routing Functions of n IP router Router rchitectures Introduction to routing tble lookup L - 6

4 Mjor tsks of router F In_port C... F... S Out_port F C - Clssify (clssifiction, filtering nd routing) F - Forwrd (trnsfer of pckets from input interfces to ddressed output interfces) S - Scheduling (trnsmission of dt pckets bsed, e.g. on priority) L - 7 Min functionl blocks of router Generic router rchitecture Input Interfce Input Interfce Crd # Input Crd port # # Switch fbric Input Interfce Input Interfce Crd # Output Crd port # # Network processor L - 8

5 Input port functionlity Lyer termintion of incoming physicl links (e.g. SDH, Ethernet) Lyer 2 frme decpsultion to inter-operte with dt-link protocols of connected networks (e.g. AAL5/ATM/SDH nd PPP/SDH) Forwrding of control pckets, e.g. routing informtion pckets (RIP, OSPF, IGMP), to network processor to updte routing tble nd network topology Some implementtions distribute copy of routing tble nd tble lookup to ech input port, while some other implementtions forwrd ll incoming pckets to centrlized routing processor Input port functionlity Lyer func. Line termintion Lyer 2 func. Protocol decpsultion Lookup/ forwrding/ queuing L - 9 Output port functionlity Buffering of outbound pckets Scheduling of buffered pckets to gurntee required QoS Lyer 2 frme genertion nd encpsultion of pckets into frmes (e.g. AAL5/ATM/SDH, PPP/SDH nd Ethernet) Lyer physicl signl genertion Output port functionlity Buffer mngement/ queuing Lyer 2 func. Protocol encpsultion Lyer func. Line termintion L -

6 Switch fbric functionlity Min function is to route dt pckets from input ports to ddressed output ports Depending on the switch fbric implementtion, pckets re trnsported through the fbric either s uniform vrible length pckets or they re frgmented to fixed size dt units In either cse, extr informtion is dded in front of the pckets to direct them through the fbric switching of whole pckets is usully pplied in low-speed routers switching of frgments is normlly used in high-speed routers Mjority of switch fbrics re bsed on three bsic rchitectures: bus bsed, memory bsed nd interconnection network bsed L - Network processor functionlity Mintennce of routing tble Execution of routing protocols Mintennce of routing topology Performnce of network mngement Wire-speed opertion obtined by implementing key functions in hrdwre Processing of pckets - clssifiction - order mngement - ccelertion of lookup - queue mngement - QoS engine Network processor functionlity Clssifier Clssifier Clssifier Embedded processor Incoming pckets Order mngement Embedded processor Embedded processor Lookup Lookup Lookup Queue mngement QoS QoS QoS Outgoing pckets L - 2

7 Router clssifiction Access routers link homes nd smll business to ISPs (Internet Service Provider) need to support vriety of ccess technologies, e.g. high-speed modems, cble modems nd xdsl Enterprise/metropolitn routers used s cmpus nd office interconnects QoS gurntees for locl trffic support of severl network lyer protocols (e.g. IP nd IPX) support of dditionl fetures, such s firewlls, security policies nd virtul LANs Bckbone/long hul routers interconnect enterprise routers huge number of pckets per second => very-high-speed requirement criticl components for interworking => relibility of utmost concern L - 3 Router implementtions Generl of routing Functions of n IP router Router rchitectures Introduction to routing tble lookup L - 4

8 Bsic types of router rchitecture Router with forwrding engines Router with dded processing power in interfces Forwrding Engine Line Interfce Line Int. + Forwrding Line Int. + Forwrding Forwrding Engine Line Interfce Line Int. + Forwrding Line Int. + Forwrding Forwrding Engine Line Interfce Line Int. + Forwrding Line Int. + Forwrding Network processor Network processor L - 5 First genertion router rchitecture Network lyer protocols were constntly chnging => dptble solution ws needed => single nd common purpose processor structure ws resonble one in which operting system in centrl role Low throughput (pckets trnsferred twice through the bus) did not scle well with incresing line speeds Shred bus, single processor crd nd line interfce crds CPU Interfce Interfce crd Interfce # crd # crd # L - 6

9 Second genertion router rchitecture Ech line crd implemented processor => distributed nd prllel routing becme vilble Min processing unit took cre of delivery of routing informtion to line interfce crds Operting system still in centrl role Cche memories were introduced to speed up routing decisions (most recently used routing entries kept in cche) Incresed throughput, but shred bus still bottleneck Solution did not scle with incresing line speeds Shred bus nd processor on ech line interfce crd Min CPU Interfce crd Interfce # crd # # + CPU L - 7 Third genertion router rchitecture Shred bus replced with more powerful switch fbrics (e.g. multistge nd crossbr) Prllel processing units (bsed on generl purpose processors) Cche memories to enhnce routing decision mking Operting system still plyed n importnt role Communiction between line interfces no more problem QoS increses processing power requirement (IP/TCP/ppliction) Did not scle well enough with the most dvnced line speeds Switch fbric nd more processing power CPU CPU # Interfce crd Interfce # crd crd # # + CPU + cche L - 8

10 Support of differentited services Trditionl routers re limited in terms of their qulity of service nd differentition fetures. Advnces in reserch nd hrdwre cpbilities hve provided mechnisms to overcome these limittions. Following opertions, possible tody to crry out in high speed, llow provisioning of differentited services: Pcket clssifiction - distinguish pckets nd group them ccording to their different requirements Buffer mngement - determine how much buffer spce should be given to certin kinds of network trffic nd which pckets should be discrded in cse of congestion Pcket scheduling - decide tht the pcket servicing order meets the bndwidth nd dely requirements of different types of trffic L - 9 DiffServ routing Appl. Appl. TCP/UDP TCP/UDP TCP/UDP TCP/UDP IP IP IP IP Eth. MAC Eth. MAC Eth. MAC Eth. MAC Eth. MAC Eth. MAC MbE MbE GbE GbE MbE MbE Phys. (twisted pir) Phys. (opticl) Phys. (twisted pir) Host Host 2 Router Router 2 L - 2

11 DiffServ routing (cont.) Appl. TCP/UDP Appl. TCP/UDP Appl. TCP/UDP Appl. TCP/UDP IP IP IP IP Eth. MAC Eth. MAC Eth. MAC Eth. MAC Eth. MAC Eth. MAC MbE MbE GbE GbE MbE MbE Phys. (twisted pir) Phys. (opticl) Phys. (twisted pir) Host Host 2 Router Router 2 L - 2 Shring of processing resources nd pipelining DiffServ-optimized router rchitecture Interfce crd # + multiple Interfce specil crd # purpose + multiple Interfce CPUs specil crd # purpose + multiple Interfce CPUs specil crd # purpose + multiple CPUs specil purpose CPUs Concentrtor Scheduler Filtering Route Lookup Buffering L - 22

12 Shring of processing resources nd pipelining (cont.) Pcket processing divided into number of consecutive processes - ech process hs dedicted processing unit (buffering, filtering, routing, etc.) Pipelined processes shred by severl interfces to increse number of line interfces - concentrtor schedules pckets for processes QoS-bsed scheduler tkes cre of pcket trnsmission from buffers to outbound interfces L - 23 Pcket processing cpcity Pcket processing cpcity of router is given s the number of forwrded pckets/second nd/or forwrded bits/second Tsks ffecting forwrding speed - link protocol processing dely (input nd output) - ddress lookup time - switching of pckets from input ports to outputs ports - queuing t output ports nd possibly t input ports Other tsks tht my hve n impct on forwrding speed - routing tble mngement/updtes - network nd router mngement In high cpcity routers, routing tble lookups re mjor problem Queuing is the min component of routing ltency Routing cpcity requirement determined by the shortest pckets L - 24

13 Future chllenges Increse of line speeds - Mbit/s => Gbit/s => Gbit/S => 4/ Gbit/s QoS-support => incresed processing need - DiffServ, IntServ, MPLS,... From best effort service to controlled use of network resources => progrmmble network nodes Different needs in the core nd edge networks - huge routing cpcity in the core network ( > million pckets/s) - lot of functionlity nd intelligence in the edge routers L - 25 Speedup mechnisms for routing tble lookup Cching routing tble entries of most ltely rrived pckets or entries most frequently ccessed re stored in cche memory Pipelining different phses of routing tble lookup re executed by different pipelined processing units Distribution of lookup to interfces or to severl routing engines network processor tkes cre of routing tble updtes nd distributes updted tbles to seprte interfce/routing engines In centrlized routing solutions only pcket heders re sent to routing processor Implementtion of lookup functionlity in hrdwre (t the expense of flexibility) L - 26

14 Cching to speedup pcket processing nd forwrding When pcket with new destintion ddress rrives to n input port, it psses through the conventionl routing process (slow pth) nd its routing entry is stored in cche memory Subsequent pckets crrying the sme destintion ddress re routed using the routing entry in the cche memory (fst pth) A routing entry is removed from cche when predefined conditions to keep it in cche expire, e.g. pcket rrivl rte declines or time since the lst pcket becomes too long Slow pth Fst pth Slow pth N Fst pth N L - 27 High speed router exmples GSR /Cisco - first gigbit router on the mrket - switching cpcity of 27.5 Gbits/s - equipped with POS (Pcket Over Sonet) nd ATM interfces 2 Terbit System /Cisco - initil switching cpcity of 5 Gbits/s, but sclble up to 5 Tbits/s - cn be equipped with OC92/STM-64 ( Gbits/s) interfces NX64 /Lucent (Nexbit) - one of the highest cpcity routers (6.4 Tbits/s) - supports interfce rtes up to OC92/STM-64 - distributed progrmmble hrdwre bsed forwrding engine - million routing entries on ech line crd - 4 ms dely gurntee for vrible size pckets L - 28

15 High speed router exmples (cont.) MGR (Multi-Gigbit Router) /BBN Technologies - forwrding rte up to 2 million pckets per second - switching bckplne cpcity of 5 Gbits/s - multiple line crds nd seprte forwrding engine crds plugged into high-speed switch - only pcket heders re directed to forwrding engines - pylods queued on line crds TSR (Terbit Switch-Router) / Avici - designed to be sclble from 6 Mbit/s to severl Tbits/s - hrdwre bsed routing, forwrding, multi-csting nd QoS service - ech line crd implements 7 Gbit/s router nd 2 such line crds fit into dul-shelf chssis => totl switching cpcity is.4 Tbits/s L - 29 Exmple of routing tble lookup speed determintion In distributed routing tble lookup solution, ech input port implements routing tble. Wht is the mximum llowed routing decision dely if the input link is Mbit/s Ethernet link or Gbit/s link nd the router should operte t wire-speed? Solution: In both exmple cses, the routing decision dely requirement corresponds to mximum pcket rrivl rte t these interfces The mximum pcket rrivl rte is encountered when there is constnt strem of minimum size Ethernet frmes The minimum size MbE frme is 64 octets nd there re 8 octets of premble nd SFD informtion in front of ech frme nd dditionlly there is lwys.96 µs time gp between successive frmes L - 3

16 Exmple of routing tble lookup determintion (cont.) Solution (cont.): Time required to trnsmit 72 octets (64+8) t the speed of Mbit/s is 5.76 µs => minimum time intervl between successive frmes is 5.76 µs +.96 µs = 6,72 µs, which is lso the mximum llowed routing decision dely for MbE input port => forwrding cpcity is bout 49 pckets/s The minimum size GbE frme is 52 octets nd there re 8 octets of premble nd SFD informtion in front of ech frme nd there is 96 ns time gp between successive frmes Time required to trnsmit 52 octets (52+8) t the speed of Gbit/s is 4.6 µs => minimum time intervl between successive frmes is µs = µs, which is lso the mximum llowed routing decision dely for GbE input port (frme bursting excluded) => forwrding cpcity is bout 235 pckets/s L - 3 / MbE frme octets Premble S F D DA SA T/L Pylod CRC Premble - AA AA AA AA AA AA AA (Hex) SFD - Strt of Frme Delimiter AB (Hex) DA - Destintion Address SA - Source Address T/L - Type (RFC894, Ethernet) or Length (RFC42, IEEE 82.3) indictor CRC - Cyclic Redundncy Check Inter-frme gp 2 octets (9,6 µs / MbE) L - 32

17 GbE frme octets Premble S F D DA SA L Pylod CRC Extension Premble - AA AA AA AA AA AA AA (Hex) SFD - Strt of Frme Delimiter AB (Hex) DA - Destintion Address SA - Source Address T/L - Type (RFC894, Ethernet) or Length (RFC42, IEEE 82.3) indictor CRC - Cyclic Redundncy Check Inter- frme gp 2 octets (96 ns / GbE) Extension - for pdding short frmes to be 52 octets long L - 33 Router implementtions Generl of routing Functions of n IP router Router rchitectures Introduction to routing tble lookup L - 34

18 Clssful ddressing scheme In IPv4, ddresses re 32 bits long - broken up into 4 groups of 8 bits nd represented usully s four deciml numbers seprted by dots, e.g., = IP intended for interconnecting networks => routing bsed on network is nturl choice (rther thn bsed on host) IP ddress scheme initilly used simple two level hierrchy - networks t the top level nd hosts t the bottom level Network prt (i.e. ddress prefix) corresponds to the fist bits Prefixes written s bit strings up to 32 bits in IPv4 followed by * - e.g. * represents ll the 2 6 ddresses tht begin with bit pttern - n lterntive wy is to use dotted-deciml expression, i.e., 3.86/6 (number fter the slsh indictes length of prefix) L - 35 Clssful ddressing scheme With the two level hierrchy, IP routers forwrded pckets bsed on the network prt, until pckets reched their destintion network Forwrding tble only needed to store single entry to forwrd pckets to ll hosts ttched to the sme network - technique is clled ddress ggregtion nd llows prefixes to represent group of ddresses Three different network sizes were defined: A, B nd C (see figure) Clss A Clss B 2 8 Clss C L - 36

19 Clssful ddresses Clssful ddressing scheme worked well in the erly dys of the Internet Two bsic problems ppered when the number of hosts nd networks grew ddress spce ws not efficiently used (only three possible network sizes vilble) nd ws getting exhusted very rpidly forwrding tbles in the bckbone routers grew rpidly, becuse routers mintin n entry in the forwrding tble for every llocted network ddress => lrger memory requirement => long lookup times L - 37 Clssless InterDomin Routing (CIDR) CIDR ws introduced to llow more efficient use of IP ddress spce nd to slow down growth of bckbone routing tbles CIDR llows prefixes to be of rbitrry length, not just 8, 6 or 24 bits s in clssful ddress scheme A network tht hs identicl routing informtion for ll sub-nets, except for single one, requires only two entries in the routing tble In CIDR, ech IP route is represented by route_prefix / prefix_length pir prefix length indictes the number of significnt bits in route prefix e.g. routing tble my hve prefixes /32, /24 nd 2.../6. If pcket is destined for ddress , the second prefix mtches L - 38

20 Difficulties with longest mtch prefix serch In clssful ddressing scheme, prefix length is coded in the most significnt bits of n IP ddress => ddress lookup is reltively simple opertion - prefixes re orgnized in three seprte tbles (A, B nd C) => n exct prefix mtch could be found using stndrd serch lgorithms bsed on hshing or binry serch CIDR llows reduced size of forwrding tbles, but ddress lookup problem becomes more complex => prefixes re of rbitrry length nd no longer correspond to the network prt => serch in the forwrding tble cn no longer be performed by exct mtching, becuse the length of the prefix cnnot be derived from the ddress itself => serching in two dimensions: bit pttern vlue nd length L - 39 Route lookup Primry gol in designing dt structure to be used in forwrding tble is to minimize lookup time, i.e. - minimize number of memory ccesses required during lookups - minimize size of dt structure (to fit prtly or entirely into cche) Secondry gols of dt structure - s few instructions during lookup s possible - keep the entities nturlly ligned s much s possible to void expensive instructions nd cumbersome bit-extrction opertions A binry tree, spnning the entire IPv4 ddress spce hs height of 32 nd number of leves is 2 32 Depth leves (IP ddresses) L - 4

21 Route lookup (cont.) A prefix of routing tble entry defines pth in the tree ending in some point nd ll IP ddresses (leves) in sub-tree, rooted t tht node, should be routed ccording to tht routing entry, i.e. ech routing tble entry defines rnge of IP ddresses with identicl routing informtion If severl routing entries cover n IP ddress, the longest mtching rule is pplied, i.e. the longest pplicble prefix should be used In the figure below, e2 represents longer mtch thn e for ddresses in rnge r e e2 r L - 4 Route lookup bsed on binry trie A trie is tree-bsed structure llowing to orgnize prefixes on digitl bsis by using the bits of prefixes to direct the brnching In trie, node on level k represents the set of ll ddresses tht begin with the sme k bits tht lbel the pth from the root to tht node, e.g. node c in the figure on the next slide is t level 3 nd represents ll ddresses beginning with the sequence Nodes tht correspond to prefixes re shown in drker shde - these nodes contin the forwrding informtion or pointer to it Some ddresses my mtch severl prefixes, e.g. ddresses beginning with will mtch prefixes c nd => prefix c is preferred becuse it is more specific (longest mtch rule) L - 42

22 A binry trie for set of prefixes Informtion stored by node: Prefixes: - * b - * c - * d - * e - * f - * g - * h - * I - * d c e f g h i Next-hop pointer (if prefix) Left-ptr Right-ptr b L - 43 Address spce of 5-bit long ddresses Prefixes: - * b - * c - * d - * e - * f - * g - * h - * i - * d c e f g h i b c c c c e e e e d d d d f f g g h h i i L - 44

23 Route lookup bsed on binry trie Tries llow finding the longest prefix tht mtches given destintion ddress nd the serch is guided by the bits of the destintion ddress While trversing the trie nd visiting node mrked s prefix, this prefix is mrked s the longest mtch found so fr The serch ends when no more brnches to tke exist nd the longest mtch is the prefix of the ltest visited prefix node An exmple ddress from root move to the right (st bit vlue = ) to node d mrked s prefix, i.e. st found prefix is * then move to the left (2nd bit vlue = ) to node not mrked s prefix => prefix d still vlid 3rd ddress bit =, but t this point there is no brnch to the right => serch stops => d is the lst visited prefix node nd prefix of d is the longest mtch L - 45 Route lookup bsed on binry trie (cont.) Going trough trie is sequentil prefix serch by length when trying to find better mtch begin looking in the set of length- prefixes, locted t level then proceed in the set of length-2 prefixes t level 2, then proceed to level 3 nd so on While stepping through trie, the serch spce reduces hierrchiclly t ech step, the set of potentil prefixes reduces nd the serch ends when this set is reduces to one Updte opertions re strightforwrd inserting new prefix proceeds s norml serch nd when rriving to node with no brnch to tke, insert the necessry node deleting prefix proceeds lso s serch nd when finding the required node, unmrk it s prefix node nd delete it if necessry L - 46

24 Pth-compressed tries In binry tries, long sequences of one-child nodes my exist nd these bits need to be inspected even though the ctul brnching decision hs been mde => serch time cn be longer thn necessry => one-child nodes consume dditionl memory Lookup time of binry trie is O(W) nd memory requirement O(NW) W is the ddress length in bits nd N the number of entries in tble Pth-compression technique cn be used to remove unnecessry one-wy brnch nodes nd reduce serch time nd memory consumption L - 47 Pth-compressed tries (cont.) Pth-compression ws first introduced in scheme clled Ptrici, which is n improvement of the binry trie structure it is bsed on the observtion tht n internl node, which does not contin prefix nd hs only one child, cn be removed removl of internl nodes requires informtion of missing nodes to be dded in remining nodes so tht serch opertions cn be performed correctly, e.g. simple mechnism is to store number, which indictes how mny nodes hve been skipped (skip vlue) or the number of the next ddress bit to be inspected There re mny wys to exploit pth-compression technique, n exmple is shown on the next slide Lookup time is O(W) nd worst cse storge requirement O(NW) L - 48

25 A pth-compressed trie exmple Prefixes: - * b - * c - * d - * e - * f - * g - * h - * I - * b Uncompressed binry trie c e d f g h i Informtion stored by node: Bit string Left-ptr Next-hop ptr (if prefix) Compressed binry trie 3 6 b c 4 4 e Bit position Right-ptr 2 d f g h i L - 49 A pth-compressed trie exmple (cont.) Two nodes preceding b hve been removed Since prefix ws locted t one child node, it ws moved to the nerest descendnt, which is not one-child node If severl one-child nodes, in pth to be compressed, contin prefixes, list of prefixes must be mintined in some of the nodes Due to removl of one-child nodes, serch jumps directly to n ddress bit where significnt decision is to be mde => bit position of the next ddress bit to be inspected must be stored => bit strings of prefixes must be explicitly stored L - 5

26 Serch in pth-compressed trie Serch goes s follows: Strt from the root nd descent in the trie under the guidnce of the ddress bits, but this time only inspect bit positions indicted by the bit position number in the nodes trversed When node mrked s prefix is encountered, comprison with the ctul prefix is performed - this is needed, becuse during the descent in the trie, we my skip some bits If mtch is found, we proceed trversing the trie nd keep the prefix s the best mtch prefix (BMP) so fr Serch ends when lef is encountered or mismtch found BMP is the lst mtching prefix encountered L - 5 A pth-compressed trie exmple (cont.) In the previous exmple cse, tke n ddress beginning with strt from root nd since its bit position number is, inspect the first bit of the ddress => st bit is => go to the left => since this node is mrked s prefix, compre prefix ( ) with the corresponding prt of the ddress => they mtch => keep s the BMP so fr => bit position number of the new node is 3 so skip the 2nd ddress bit nd inspect the 3rd one, which is => proceed left => next node includes prefix so compre prefix b with the corresponding prt of ddress => no mtch => stop serch => the lst recorded BMP is L - 52

27 Multibit trie Drwbck of binry (-bit) trie is tht one bit t time is inspected nd the number of memory ccesses (in the worst cse) cn be 32 for IPv4 Number of lookups cn be substntilly decresed by using the multibit trie structure, i.e. severl bits re inspected t time for exmple, inspecting four bits t time would led to only 8 memory ccesses in the worst cse for n IPv4 ddress Number of bits (K) to be inspected is clled stride nd the stride cn be constnt or vrible In K-bit trie, ech node hs 2 K pointers (children) If route prefix is not multiple of K, it needs to be expnded to K or its multiples Lookup time is O(W/K) nd storge requirement O(2 (K-) NW/K) L - 53 Multibit trie exmple Prefixes nd d re expnded to length 2 nd prefix c hs been expnded to length 4 (rest of the prefixes remin unchnged) Height of the trie hs been decresed nd so hs the number of memory ccesses when doing serch Uncompressed binry trie Vrible stride multibit trie d d d b c e f g h i b c c e f g h i Informtion stored by node: Next-hop pointer (if prefix) Ptr Ptr Ptr Ptr L - 54

28 Multibit trie exmple 2 An lterntive multibit trie of the previous exmple cse - prefixes nd d hve been expnded to length 3 - rest of the prefixes remin the sme s before expnsion When n expnded prefix collides with n existing one, forwrding informtion of the existing one must be mintined (to respect the longest mtch) Fixed stride multibit trie c e d d d b f f g g h h i i L - 55 Serch in multibit trie Serch in multibit trie is essentilly the sme s serch in binry (-bit) trie - successively look for longer prefixes tht mtch nd the lst one found is the longest mtch prefix for given ddress Multibit tries do liner serch on length s do the binry tries, but the serch is fster becuse the trie is trversed using lrger strides A multibit trie is fixed stride system, if ll nodes t the sme level hve the sme stride size, otherwise it vrible stride system Fixed strides re simpler to implement thn vrible strides, but usully consume more memory L - 56

29 Choice of stride size nd updte of tries Choice of stride size is trde-off between serch speed nd memory consumption in the extreme cse, trie with single level could be mde (stride size = 32) nd serch would tke only one memory ccess, but huge mount of memory would be required (2 32 entries for IPv4) nturl wy to choose stride size nd memory consumption is to let the binry trie structure determine this Updte bounds determined by stride size multibit trie with severl levels llows, by vrying stride K, n interesting trde-off between serch time, memory consumption nd updte time - lrger strides mke fster serch => memory consumption increses nd updtes will require more entries to be modified (due to expnsion) L - 57 Level compression (LC) trie Pth-compressed trie is n effective wy to compress trie when nodes re sprsely populted LC-tries were developed to compress densely populted tries LC-tries combine the pth-compression nd multibit trie compression to optimize binry trie structures first, binry trie is developed to compct pth-compressed trie second, the lrgest full binry sub-trie with multilevels is trnsformed into corresponding one-level multibit sub-trie this process strts from the root node nd repets recursively on ech child node of the obtined multibit sub-trie ll bit strings tht re proper prefixes of other ones re removed from the LC-trie mening tht only lef nodes contin prefixes L - 58

30 LC-trie exmple Prefixes: - * b - * c - * d - * e - * f - * g - * h - * I - * Compressed binry trie 3 b c e 2 d f g h i Uncompressed binry trie b b c LC-trie c e e d f g h i f g h i L - 59 Level compression trie (cont.) To sve memory, ll nodes in LC-trie re stored in single node rry first root, then ll nodes t the second level, then ll nodes t third level, nd so on ll the descendnts of n internl nodes re stored in consecutive memory loctions => n internl node only needs to point to its first descendnt Informtion stored in ech node brnch number of descendnts of node (lwys power of 2) skip number number of bits to be skipped t this node during serch opertion pointer n internl node points to its first descendnt (given s the index vlue of the first child node) nd lef node points to one entry of nother bse vector tble, where the rel prefix nd next-hop informtion re stored Index /root /b 2 /c 3 /e 4 5 /f 6 /g 7 /h 8 /i Brnch 2 2 Skip 3 Pointer b c e 5 f g h i L - 6

31 Level compression trie (cont.) Ech entry of the bse vector tble includes complete string of the prefix next-hop informtion specil prefix vector, which contins informtion of strings tht re proper prefixes of other strings is needed becuse internl nodes of n LC-trie do not contin pointers to the bse vector tble this informtion implies whether there exists longer prefix mtching the IP Index b c e f g h i Prefix bit string ddress nd gives the next-hop informtion in cse of mtch Next hop ptr_b ptr_c ptr_e ptr_g ptr_h Lookup time is O(W/K) nd memory requirement is O(2 K NW/K) ptr_f ptr_i Specil prefix vector =/ptr_ =/ptr_ d=/ptr_d d=/ptr_d d=/ptr_d d=/ptr_d d=/ptr_d L - 6 Multibit tries in hrdwre In core network routers, lookup times re very short nd lookup lgorithms re implemented in hrdwre to obtin required speed Bsic scheme uses two level multibit trie with fixed strides - 24 bits t the first level nd 8 t the second level In bckbone routers, most of the entries hve prefix length of 24 bits or less => longest mtch prefix found in one memory ccess in the mjority of cses Only smll number of sub-entries t the 2nd level To sve memory, internl nodes not llowed to store prefixes => prefixes corresponding to internl nodes expnded to 2nd level => result is multibit trie with disjoint expnded prefixes - st level hs 2 24 nodes nd is implemented s tble with the sme number of entries L - 62

32 Multibit tries in hrdwre (cont.) An entry t the st level contins either the forwrding informtion or pointer to the corresponding sub-trie t the 2nd level - two bytes needed to store pointer/forwrding informtion => memory bnk of 32 Mbytes is needed to store 2 24 entries Destintion ddress st memory bnk 24 2nd memory bnk Forwrding informtion entries entries L - 63 Multibit tries in hrdwre (cont.) Number of sub-tries t the 2nd level depends on the number of prefixes longer thn 24 bits 2nd level stride is 8 bits => sub-trie t the 2nd level hs 2 8 =256 leves Size of 2nd memory bnk depends on the expected worst cse prefix length distribution, e.g. 2 2 one byte entries ( memory bnk of Mbytes) supports mximum of 2 2 = 496 sub-tries t the 2nd level Lookup requires mximum of two memory ccesses - memory ccesses cn be pipelined or prllelized to speed up performnce Since the first stride is 24 bits nd lef pushing is used, updtes my tke long time in some cses L - 64

33 New directions in IP lookup More efficient lookup schemes hve been developed to improve the verge lookup performnce nd storge complexity Exmples of new methods re Binry serch on trie levels, which decomposes the longest prefix opertion into W exct mtching opertions, ech performed on prefixes of equl length Multiwy or K-wy rnge serch, which pplies binry serch to best mtching prefixes by using two routing entries per prefix nd with some precomputtion Ternry CAM uses specil CAM (Content Addressble Memory), which performs prllel comprisons internlly. TCAM stores ech W-bit field s [vl, msk] pir nd when bit string is presented to the input, TCAM outputs the loction (or ddress) where mtch is found. L - 65 New directions in IP lookup (cont.) Conventionl routers offer the best-effort service by processing ech incoming pcket in the sme wy. New pplictions require different QoS levels nd to meet these requirements new mechnisms, such s dmission control, resource reservtion nd per-flow queuing, need to be implemented in routers. Routers re required to distinguish nd clssify incoming trffic into different flows Flows re specified by rules nd ech rule consists of opertions for compring pcket fields with certin vlues Pcket fields to be inspected re collected from different protocols => pcket clssifiction L - 66

34 Comprison of some lookup schemes Scheme Binry trie Worst cse lookup O(W) Memory O(NW) Updte O(W) Pth compressed trie O(W) O(N) O(W) K-stride multibit trie O(W/K) O(2 K NW/K) O(W/K+2 K ) LC-trie O(W/K) O(2 K NW/K) - Binry serch on tries level O(log 2 W) O(Nlog 2 W) O(log 2 W) K-wy rng serch TCAM O(log 2 W) O() W - length of ddress in bits, N - number of prefixes in prefix set, K - stride size Source: Proceedings of the IEEE, vol. 9, No. 9, 22 O(N) O(N) O(N) - L - 67 Lookup sclbility nd IPv6 On sclbility point of view, importnt spects re the number of entries in lookup tble nd the prefix length Multibit tries improve lookup speed with respect to binry tries, but only by constnt fctor on the length dimension => multibit tries scle bdly to longer ddresses (28 bit in IPv6) Binry serch on tries level hs logrithmic complexity with respect to prefix length => sclbility very good for IPv6 Rnge serch hs logrithmic lookup complexity with respect to the number of entries, but independent of prefix length => if the number of entries does not grow excessively, rnge serch is sclble for IPv6 L - 68