Numonyx JSPCM128A00B85ES 128 Mbit Phase Change Memory 90 nm BiCMOS PCM Process

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1 Numonyx JSPCM128A00B85ES 90 nm BiCMOS PCM Process Structural Analysis For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor technology, please call Sales at Chipworks Richmond Road, Suite 500, Ottawa, ON K2H 5B7, Canada Tel: Fax:

2 Structural Analysis Some of the information is this report may be covered by patents, mask and/or copyright protection. This report should not be taken as an inducement to infringe on these rights Chipworks Inc. This report is provided exclusively for the use of the purchasing organization. It can be freely copied and distributed within the purchasing organization, conditional upon the accompanying Chipworks accreditation remaining attached. Distribution of the entire report outside of the purchasing organization is strictly forbidden. The use of portions of the document for the support of the purchasing organization s corporate interest (e.g., licensing or marketing activities) is permitted, as defined by the fair use provisions of the copyright act. Accreditation to Chipworks must be attached to any portion of the reproduced information. SAR CYRK Revision 1.0 Published: May 27, 2009

3 Structural Analysis Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Company Profile 1.4 Introduction 1.5 Device Summary 1.6 Process Summary 2 Device Overview 2.1 Package and Die 2.2 Die Features 3 Layout and Topology Analysis 3.1 Die Utilization Analysis 3.2 Layout of Selected Die Features 4 Process Analysis 4.1 General Device Structure 4.2 Bond Pads 4.3 Dielectrics 4.4 Metallization 4.5 Vias and Contacts 4.6 Transistors and Poly 4.7 Phase-Change Memory Layers 4.8 Isolation 4.9 Wells and Substrate 5 PCM Cell Analysis 5.1 Overview 5.2 Plan View Analysis 5.3 Cross-Sectional Analysis 6 Materials Analysis 6.1 Materials Analysis Overview 6.2 TEM-EDS Analyses of the Dielectrics 6.3 TEM-EDS Transistors and Poly 6.4 TEM-EDS Metallization

4 Structural Analysis 7 Critical Dimensions 7.1 Horizontal Dimensions 7.2 Vertical Dimensions 8 References 9 Statement of Measurement Uncertainty and Scope Variation About Chipworks

5 Overview Overview 1.1 List of Figures 2 Device Overview Top Package View Lead TSOP Pinout (Numonyx 256 Mbit P33 NOR Flash) Package X-Ray (Top View) JSPCM128 Die Die Markings Die Markings Mask Markings Die Cross Sections Die Corner Die Corner Die Corner Die Corner Minimum Pitch Bond Pads Bond Pad in Detail 3 Layout and Topology Analysis Poly Die Photograph PCM Tile Dummy PCM Lines Die Delayered to PCM Dummy PCM Lines in Detail Die Delayered to PCM Dummy PCM Lines Delayered to Polysilicon Optical Dummy PCM Lines Delayered to Polysilicon SEM Cross Section Through Dummy PCM Line NOR Cell Bipolar Transistor ROM Memory Block Single Cell of ROM Memory ROM Memory Delayered to Polysilicon Cross Section of ROM Memory 4 Process Analysis General View of JSPCM Die Edge Die Edge in Detail General Structure Beyond Scribe Lane Bond Pad Left Bond Pad Edge Right Bond Pad Edge TEM of Passivation Passivation Over Closely Spaced Metal 4 Lines ILD ILD 2

6 Overview ILD PMD Periphery PMD Memory Array to Periphery Transition Minimum Pitch Metal Metal 4 Edge TEM Minimum Pitch Metal Metal 3 TEM Minimum Pitch Metal Metal 2 TEM Minimum Pitch Metal 1 TEM Metal 1 in Detail TEM Metal 1 Bottom and Liner in Detail TEM Minimum Via 3s Via 3 to Metal 3 Interface TEM Minimum Pitch Via 2s Minimum Pitch Via 1s Via 2 in Detail TEM Via 1 in Detail TEM Contacts to Poly Contact to Poly TEM Minimum Pitch of Contact 1 (Contact 0) to Contact 0 (Diffusion) Contact Bottom TEM Minimum Pitch Contacts to PCM Minimum Gate Length NMOS Transistors Minimum Gate Length PMOS Transistors Peripheral Transistor TEM Sidewall Spacer TEM Peripheral Transistor Gate Oxide TEM PCM Cell Schematic PCM Cell Beveled View Cross Section of PCM Cell Length Cross Section of PCM Cell Si Stain Cross Section of PCM Cell TEM PCM Top Electrode Contact PCM Top Electrode Contact TEM PCM Length TiN Top Electrode TEM-EDS GST TEM-EDS PCM Bottom Contact (Contact 0) Interface Between Thick and Thin Regions of Contact 0 Plug Buffer Oxide and Salicide Exclusion Mask for Vertical PNP BJT Buffer Oxide and Salicide Exclusion Mask for Vertical PNP BJT in Detail

7 Overview PCM Cell TEM (Width) PCM Cell STEM (Width) PCM Cell Over Nitride Pedestal in Detail Width PCM Cell Over Filler Oxide in Detail Width Dummy PCM Cell with Uncontacted Heater PCM Cap, Heater Definition Pedestal, and PCM Seal TEM-EDS Filler Oxide Below PCM TEM-EDS Heater Left Side Heater Right Side Uncontacted Heater Heater TEM-EDS Heater TEM-EELS HRTEM of PCM Active Region Poly Over Isolation Minimum Width STI Wells Periphery to PCM Transition SCM P-epi and P + Sub Collector SEM (Si Stain) Wells PNP BJT SCM Epi and Substrate SRP Array P-Well SRP N- Base SEM (Perpendicular to PCM Line) N + Base and P + Emitter Contact SEM (Perpendicular to PCM Line) Peripheral P-Well 1 SCM Peripheral N-Wells SCM Peripheral N-Well SRP 5 PCM Cell Analysis PCM Schematic Circuit Metal 3 Ground (Collector) Lines Metal 2 Bit and Wordlines Metal 2 Bitlines in Detail Metal 1 Wordlines Metal 1 Wordlines in Detail M1 Wordlines to PCM Line Transition PCM Line Overview PCM Line Detailed Contacts to Base (Wordline) and Emitter of BJT Contacts to Base (Wordline) and Emitter of BJT Detail PCM at Diffusion PCM Cross Section (Parallel to Horizontal Metal 2 and Metal 1 Wordlines) PCM Cross Section (Parallel to Vertical Metal 2 Bitlines) PCM Cross Section (Edge of PCM Line)

8 Overview Materials Analysis Passivation 2, ILD 3-2, ILD 2-1, and ILD Passivation 1, ILD 3-2, ILD 2-2, and ILD ILD 1-3 and ILD PMD PMD 5 and PMD PMD 6, PMD 4, PMD 2, PMD 3, and PMD SWS, CESL, and Salicide Exclusion Mask Layers Oxide Filled STI Poly Gate Gate and Source/Drain Silicides Metals 3 through 1 Liner Metal Contact 1 and Contact 0 Liner

9 Overview List of Tables 1 Overview Device Summary Process Summary 2 Device Overview Package, Die, and Bond Pad Sizes 3 Layout and Topology Analysis Functional Block Sizes Die Feature Sizes 4 Process Analysis Dielectric Thicknesses Metallization Vertical Dimensions Metallization Horizontal Dimensions Via and Contact Horizontal Dimensions Transistor Horizontal Dimensions Transistor and Polycide Vertical Dimensions PCM Cell Vertical Dimensions PCM Cell Horizontal Dimensions STI Measured Dimensions Die Thickness and Well Depths 5 PCM Cell Analysis PCM Cell Dimensions 7 Critical Dimensions Package, Die, and Bond Pad Sizes Die Feature Sizes Metallization Horizontal Dimensions Via and Contact Horizontal Dimensions Transistor Horizontal Dimensions PCM Cell Horizontal Dimensions STI Measured Horizontal Dimensions Dielectric Thicknesses Metallization Vertical Dimensions Transistor and Polycide Vertical Dimensions PCM Cell Vertical Dimensions STI Measured Vertical Dimensions Die Thickness and Well Depths

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