SanDisk Flash Memory Controller. Partial Circuit Analysis
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1 SanDisk Flash Memory Controller Partial Circuit Analysis For questions, comments, or more information about this report, or for any additional technical needs concerning semiconductor technology, please call Sales at Chipworks Richmond Road, Suite 500, Ottawa, ON K2H 5B7 Canada Tel:
2 SanDisk Flash Memory Controller Table of Contents - Overview - IVC and Oscillator - Schematics and Symbol Conventions - Signal Cross Reference List - Single-Port SRAM - Schematics and Symbol Conventions - Signal Cross Reference List - Dual-Port SRAM - Schematics and Symbol Conventions - Signal Cross Reference List - I/O Buffer and ESD - Schematics and Symbol Conventions - Signal Cross Reference List - Naming Conventions - Report Evaluation
3 SanDisk Flash Memory Controller Overview List of Figures... Page 1 List of IVC and Oscillator Schematics... Page 2 List of Single-Port SRAM Schematics... Page 3 List of Dual-Port SRAM Schematics... Page 4 List of I/O Buffer and ESD Schematics... Page 5 Introduction... Page 6 Device Summary Sheet... Page 9
4 SanDisk Flash Memory Controller Page 1 List of Figures Package Markings Package X-Ray Package X-Ray with Pin Configuration Die Markings Die Photograph Annotated Die Photograph Metal 1
5 SanDisk Flash Memory Controller Page 2 List of IVC and Oscillator Schematics Partial Analog Block Bandgap Reference Programmable Current Bias Generator and Voltage Buffer Internal Voltage Generator Comparator Power Up/Down Level Shifter H-to-L Transition Delay Circuit H-to-L Transition Delay Level Shifter Voltage Level Detector Voltage Level Detector Internal Voltage Generator Comparator Comparator Bandgap Reference Programmable Current Bias Generator and Voltage Buffer Oscillator Bias Circuit Current Cell Internal Voltage Generator Comparator Level Shifter Block Level Shifter 1 A.1.0 Symbol Conventions - 1 A.1.1 Symbol Conventions - 2
6 SanDisk Flash Memory Controller Page 3 List of Single-Port SRAM Schematics Kbit SRAM Macro Data Path Data Input Registers Bitline Access Bitline Sense Amplifiers Data Output Drivers Kbit Memory Array Address Path Primary Row Decoders Secondary Row Decoders Wordline Drivers Column Decoders Column Decoders and Read Write Access Control Command Registers Write Command Register Clock Generator Precharge and BLSA Access Control A.1.0 Symbol Conventions - 1 A.1.1 Symbol Conventions - 2
7 SanDisk Flash Memory Controller Page 4 List of Dual-Port SRAM Schematics bit Dual-Port SRAM Macro Data Path Data Input Registers Bitline Access Bitline Sense Amplifiers Data Output Drivers bit Memory Array Address Path Primary Row Decoders Secondary Row Decoders Wordline Drivers Column Decoders Column Decoders and Read Write Access Control Command Registers Clock Generator Precharge and BLSA Access Control Spare Cells Control Circuitry Control Circuitry Control Circuitry Power Up A.1.0 Symbol Conventions - 1 A.1.1 Symbol Conventions - 2
8 SanDisk Flash Memory Controller Page 5 List of I/O Buffer and ESD Schematics Level Shifter I/O + ESD I/O Buffer Type Output Driver Output Pre-Driver Input Buffer I/O Buffer Type Output Driver Output Pre-Driver Input Buffer Pull down Circuit I/O Buffer Type 2A (Test Pad) I/O Buffer Type Disabled Output Driver Input Buffer I/O Buffer Power Protection Circuits Power Protection Circuit Power Protection Circuit 2 A.1.0 Symbol Conventions - 1 A.1.1 Symbol Conventions - 2
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