Qualification for Reliability and other programs at the
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1 Qualification for Reliability and other programs at the Maryland/Israel Center for Nano -Product Realization Joseph B. Bernstein University of Maryland Bar Ilan University Microelectronics Device Reliability Maryland/Israel Joint Center 1
2 Collaboration on Product Quality and Reliability State of Maryland University of Maryland Government Labs (NIST, Navair) Industry (Honeywell, Northrop Grumman) Maryland JOINT CENTER Israel Israeli Ministries (MAFAT) Israeli Universities (TAU, Bar- Ilan) Industry (Rafael, Motorola) ISQ Maryland/Israel Joint Center 2
3 PURPOSE 1. Improve the competitiveness of Israeli as well as Maryland and US based companies. 2. Generate qualification tools to enhance the competitiveness of their newest products. 3. Provide expertise in research, teaching and training in the area of Reliability and Quality Engineering to service Israeli Industry and companies in the State of Maryland. Maryland/Israel Joint Center 3
4 Areas of Focus for the MD/Israel Center Reliability assessment and qualification for Silicon MOS and SiC devices and systems. Modeling techniques for reliability prediction. Electrical and electro-optical measurements of nano- device parameters. Characterization of reliability phenomena and assessment of physical failure mechanisms. Advanced micro- and nano-scale processing and metrology technologies for product realization. Maryland/Israel Joint Center 4
5 Experimental Mechanics at Nanoscale: Biaxial Microtensile Tester Testing Maryland/Israel Joint Center 5 H. Jin, PhD Thesis UMD (2004)
6 Experimental Mechanics at Nanoscale: Scanning Nonlinearity Scanning Probe Microscope Conventional Grating DIC d f ( xi ) = ui xi i MP!(" 1( ) /) 1 2 " 1 2 ( 1 1 % + ui xi ii & # 2( ) /) ) " dx ' ) i1 ) i2 $ x1 position error (pixels) & 1 micron 0.5 & 2 micron 1 & 2 micron SPIP SPIP (curve fit) Jin and Maryland/Israel Bruck, Nanotechnology Joint Center 6 (2005) x1 position (pixels)
7 Nanostructured Graded Solar Cells Vary pressure 500 nm Maryland/Israel Joint Center 7 Cole and Bruck, Proc. of 2005 SEM Ann. Conf. (2005)
8 PURPOSE Apply Reliability Principles to Evaluate High- Reliability Nano-Technology. Collaboration between Semiconductor Manufacturers, Military, Aerospace, Telecom and other High-Reliability End-Users. Establish Industry Wide Guidelines for De- Rating and High Reliability Operation for COTS in Various Environments. Serve as a Resource for Reliability Studies between Israeli and US Industry. Maryland/Israel Joint Center 8
9 EE Times: 4, Sept Chipping away at design for Reliability at 65 nanometers and below, current densities go through the roof, exacerbating electromigration. Problems such as hot-carrier degradation loom larger. Ultra-thin gate oxides are prone to breakage. Without DFR, many 65- and 45-nm chips will ultimately break. That may not matter for a volume consumer product with a short life. But it matters a lot for chips that go into airplanes, pacemakers or cars. - Richard Goering EE Times Maryland/Israel Joint Center 9
10 Conclusion from the same article There's a need for high-level models that allow designers to evaluate reliability concerns early in the design cycle, while architectures are still being defined. There's a need for strong analysis tools that can identify potential problem areas, as well as for automatic optimization and repair tools that can improve reliability. The Focus of our MD/Israel Collaborative Center! Maryland/Israel Joint Center 10
11 Manufacture s Data (Normalized) 65 nm 90 nm 180 nm ?? Equivalent Burn-In time. Acceptable for Commercial Applications? 2007 Intel Data 2006 Freescale NBTI Data Start of AVSI #17 Pre-Mature Wear-out Required for Avionics, Medical, Telecom industries Industry Data showing both increasing failure rate and decreasing product lifetime!! Maryland/Israel Joint Center 11
12 Qualification for Reliability Should consider all known failure mechanisms Optimal qualification method should consider different combinations of accelerated temperature and voltage Suggestions to improve qualification method: Appropriate voltage, high temperature: EM High voltage, high temperature: TDDB and NBTI Appropriate voltage, low temperature: HCI Temperature Cycles (HALT): Packaging High Speed Stress: System Integration Maryland/Israel Joint Center 12
13 Failure Rate Estimation at System Level Circuit SPICE simulation: Stress parameters for each transistor at operating conditions Accelerated testing: Failure rates of each failure mechanism Acceleration models and parameters. Transistor Level λtddb λhci λnbti λem λpackage Chip Level TDDB: SUM(λTDDB) HCI: N*MAX(λHCI) NBTI: N*MAX(λNBTI) EM: SUM(λEM ) Package: SUM(λpkg) λchip = TDDB+NBTI +EM +(HCI+PGK) n Maryland/Israel Joint Center 13
14 Reliability Simulation Assume equal contribution of TDDB, HCI, EM and NBTI 130 nm Technology Accelerated Test 125 C 75 C 25 C Nominal Operation Reported FIT NOTE: Lower temperature has greater acceleration at Higher voltage!! Maryland/Israel Joint Center 14
15 Reliability Center Work Accelerated testing: coordinating the tests at Freescale, Intel, JPL, Tower, Rafael, etc. Reliability System Simulation: SRAM, SDRAM, Microprocessor, Analog device Wearout trend analysis: Nanometrics, HCI, NBTI, TDDB, EM, SEU, Packaging, Pb-free. Qualification through Reliability Simulation Handbooks: To be completed with results. Coordination of Future tests with member companies through Reliability Center. Maryland/Israel Joint Center 15
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