Compact Modeling for PV and Aging Effects. Correlated PV and Aging corner models. ESE MOS-AK Rome. a leap ahead. in Compact Modeling

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1 Compact Modeling for PV and Aging Effects Correlated PV and Aging corner models ESE MOS-AK Rome a leap ahead in Compact Modeling

2 This work is funded by: Granted Medea+ Project

3 Motivation General constraint between device performance and lifetime Design is very limited within the specified operating conditions without any information of parameter shifts. Can we handle Aging effects with corner models similar to PV??

4 Presentation Overview PV Corner Modeling Reliability Effects in State of the art Design Kit SOA Check LTacc Aging parameter modeling Correlated Corner modeling for PV and Reliability Effects.

5 Process Variability Intra-Die Variation or Mismatch Inter-Die Variation

6 Process Variability Simulation/Modeling Modeling of Process Variability WC Model Pass/Fail criteria Sensitivity analyses No parameter correlation & No Yield estimation Corner Model With statistical Methods multivariate methods: PCA, PFA non-parametric Analyze Boundary Models, BPV Parameters are correlated MC Model Corner & Mismatch simulation Yield estimation parameter/device correlation

Worst Case Corner Modeling Device performance variation is described by SPICE models fs Uncorrelated WC Corner MOS transistors Min/Max IDSAT, VT, Correlated Parameter/Device

(slow NMOS, slow PMOS) Kocher, MOS-AK UPS 2001) fs (fast NMOS, corner slow PMOS) Correlated Correlated corner sf (slow NMOS, fast ff (fast NMOS, fastpmos) PMOS) Corner Models

7 Worst Case Corner Modeling Device performance variation is described by SPICE models fs Uncorrelated WC Corner MOS transistors Min/Max IDSAT, VT, Correlated Parameter/Device IOFF Realistic Worst Cases IDSAT, VT, MOS transistors Min/Max ff (fast NMOS, fast PMOS) IOFF ss (M. (slow NMOS, slow PMOS) Kocher, MOS-AK UPS 2001) fs (fast NMOS, corner slow PMOS) Correlated Correlated corner sf (slow NMOS, fast ff (fast NMOS, fastpmos) PMOS) Corner Models device groups sscorner (slow NMOS, slow PMOS) Models forfor device groups fs (fast NMOS, slow PMOS) Permutation not necessary necessary sfpermutation (slow NMOS, fast PMOS) Corner Models for device groups Permutation necessary ss UC L LC L ff LC L sf UC L

8 State of the Art AMS PDK Including Reliability Effects in Compact Models/Design Kit SOA Check LTacc Simulation

9 SOA (Save Operating Area) Hot Carrier induced stress (HCS) for analog operation: Transistors are stressed at VDSmax and VGS=Vt+Voverdrive. Vt, IDSAT, IDlin and GMmax are used as degradation parameters. The maximum allowed shift e.g. 10% for analog applications within extrapolated target lifetime (10 years with Duty Factor of 100). Biased temperature high gate stress (BTS-VGS): PMOS transistors are stressed at high temperature (e.g. T=125 C) and maximum Gate voltage. The shift in threshold voltage (BMi) is used as degradation parameter for this effect. The maximum allowed shift e.g. 10% for analog applications within extrapolated target lifetime (10 years with Duty Factor of 100).

10 Safe Operating Area NMOS50 H: D NFET G B S SOAC Vgs [V] 20 Each Device has to operate inside its Safe Operating Area for the whole lifetime 10 Safe Operating Area Vds [V] H. Gensinger

11 Safe Operating Area Checker (SOAC) Verilog-A Watchdog which reports voltage levels outside the SOA and forward-biased parasitic diodes SOAC is necessary for robust High Voltage Design Available within the PDK (implemented in Spectre) No Change in Schematic Longer Simulation Time No information of parameter changes H. Gensinger

12 SOAC Tool Waveforms Schematic SOAC Tool SOA-Checker output All Violations are listed Selected violation H. Gensinger HGE

13 SOA LTacc Vgs [V] Safe Operating Area 0 Max allowed shift of 10% Vt, IDanalog and GMmax With LTacc=100 Is LTacc=100 applicable for analog applications? What is the lifetime outside the SOA? Overdesign within the SOA?.

LTacc LifeTime Acceleration Factor for Simulation LTacc defined in the Process

VGB [V] [V] 1.8 34 [V] LTacc Device length [µm] Note 0.5 Q1,Q4,Q5 1 2.

VDB max. VSB [V] [V] 50 0.8 50 1.0 20 1.2 20 3.6 (5) 50 (55) 3.6 (5) 50 (55) 3.6 600 NMOS50T 3.

14 LTacc LifeTime Acceleration Factor for Simulation LTacc defined in the Process Parameter Document: HV NMOS Transistors Device name max. VGS max. VDS max. VGB [V] [V] [V] LTacc Device length [µm] Note 0.5 Q1,Q4,Q Q2,Q4,Q Q1,Q4,Q High voltage NMOS with thin gate oxide max. VDB max. VSB [V] [V] (5) 50 (55) 3.6 (5) 50 (55) NMOS50T 3.6 (5) Digit al Analo g Digit al Analo g Digit al H. Gensinger * Taken a very bad device a example

15 LTacc LifeTime Acceleration Factor Definition Lifetime Acceleration Factor defines the degradation of a device within a specific operating area Turned Off devices have LTacc=1; this means a lifetime of 10years A device operating at LTacc=100 will have 1/100 of its nominal lifetime: => LT = 87600(*)/100 = 876 hours LTacc = 2000 => LT = 87600/2000 = 43.8 hours No direct information of parameter changes H. Gensinger * 10 Years = hours = 3.15*108 sec

16 LTacc The Concept Switching the device t 4 t 3 t 2t 1 V(D, S) Switching Time: t = t1+ t2+ t3+ Device passes through t4 operating areas with different LTacc factors during Switching: t1 : LTacc1 = 1 t2 : LTacc2 = 600 t3 : LTacc3 = 2000 t4 : LTacc4 = 1 H. Gensinger

17 LTacc Features LTacctot depends on the operating area of the device Length dependences taken into account Gives the estimated Lifetime acceleration factor for one simulation Lifetime can be calculated form LTacctot: Designer has to define a simulation (or a number of simulation) which is (are) H. representative for the whole lifetime of the device Gensinger

18 Lifetime Prediction & Aging Modeling Including Reliability Effects in Compact Models/Design Kit Implementation in the PDK Flow Aging Simulation Aging Effects Aging Modeling

19 ELIAS Project : Proposed design workflow European Project: End of Life Investigations for Automotive Systems H. Gensinger

20 Aging Simulation SPICE Input dec & Schematic + Analog Simulat or Aging Parameter Model VT=f(t) RD=f(t) Aging Simulator P=f(t) Sum (p.t) Extrapolate product lifetime Analog Simulat or

Aging Modeling HC: The de facto modeling method to analyze CHC is based on substrate current Isub, R D mechanism. (a) NBTI: 1-D hydrogen species diffusion. (b) CHC: 2-D hot-carrier trapping.

21 Aging Modeling HC: The de facto modeling method to analyze CHC is based on substrate current Isub, R D mechanism. (a) NBTI: 1-D hydrogen species diffusion. (b) CHC: 2-D hot-carrier trapping. NBTI: Generation of interface traps at Si/SiO2 interface Vt degradation partial recovery HC and NBTI Modeling with Reaction Diffusion and hole trapping/detrapping mechanism : VT, U0, RON = f (Nit) =f (isub, ids) Compact Modeling and Simulation of Circuit Reliability for 65-nm CMOS Technology: Wenping Wang IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 7, NO. 4, DECEMBER 2007

22 IBULK Modeling Extraction results for saturation region (fresh,10s,100s,1000s, 10e4s) Ibulk Degradation Substrate current model Used parameters: ALPHA0 BETA0 Relative Degradation of ibulk [%] A. Steinmair

23 ID Modeling Extraction results for linear region (fresh,10s,100s,1000s,10e4s) Ron effect visible: Used parameter: RD ID Degradation Relative Degradation of ID [%] A. Steinmair

24 RelXpert Implementation A. Steinmair

25 Circuit Simulation Benchmark Circuit: Stressed Voltage Divider +1 V V g R=510 Ohm, external f=10khz NMOSIM, 10x0.5 GND 20u s 5 30us V 20us 10000s fresh 30us 2V Alpha0, beta0, RD = f(t) A. Steinmair

26 Securing Circuit Functionality with Aging Corner Models Correlated PV and Aging Corner Models Split lot production and stress measurements Aging Corner Models with E2SPICE Method

27 PV and Aging effects (FET) Inter Die PV: Variation of electrical parameters based on process variation VT, IDSAT, IDLIN WC models based on process specification = 6Sigma, 3 sigma of output parameter SPICE Models: Variation of input parameters (VTO, U0, NSUB) resulting in variation of out put parameters (IDSAT, IOFF, VTshort) Aging Modeling: Parameter shift based on HC or NBTI VT, IDSAT, IDLIN SOAC & LTacc based on lifetime specification = parameter aging/ degrading of max 10% (gm, idsat, idlin, vt) for 10 year lifetime Aging SPICE Models: WC models based on lifetime specification including PV

28 Split lot production and Corner Model check Benchmark plot for a NMOS device, W/L=10um/0.35um, Vgs=3.3V, Vbs=0V, (+) measurement of WCP (upper) and WCS (lower) corner lot wafer, (x) measurement of typical corner lot wafer, (dotted line) typical BSIM3v3 device model, (dashed lines) statistical BSIM3v3 WCP model (upper) and statistical BSIM3v3 WCS model (lower), (solid lines) common BSIM3v3 WC models

29 HC Stress 4.7V IDsat shift % IDlin shift %

30 WC Reliability Model Pessimistic WC Model failed New Aging WC Model Set Including PV and HC

31 Summary and Outlook Generation of WC aging models including PV: Further Research Temperature dependency NBTI specially for PFET HV Transistor

32 Thank you Thank you for your attention

Lecture 4a. CMOS Fabrication, Layout and Simulation. R. Saleh Dept. of ECE University of British Columbia

Lecture 4a. CMOS Fabrication, Layout and Simulation. R. Saleh Dept. of ECE University of British Columbia Lecture 4a CMOS Fabrication, Layout and Simulation R. Saleh Dept. of ECE University of British Columbia res@ece.ubc.ca 1 Fabrication Fabrication is the process used to create devices and wires. Transistors