High speed full wafer monitoring of surface, edge and bonding interface for 3D-stacking

Transcription

1 Sematech Workshop on 3D Interconnect Metrology Sematech Workshop on 3D Interconnect Metrology, July High speed full wafer monitoring of surface, edge and bonding interface for 3D-stacking Lars Markwort, Pierre-Yves Guittet, Greg Savage, Christoph Kappel Nanda Tech GmbH Anne Jourdain, Sandip Halder imec Eleonora Storace SUSS 1

2 Agenda Introduction Applications previously o o o Edge inspection Post-grinding inspection Post-recess etch inspection Applications update o o o Bond Layer inspection Post-grinding inspection Post-recess etch inspection Summary 2

3 Nanda Tech SPARK Technology Basics New Technology: No moving parts Full wafer illumination and imaging Illuminate and capture full wafer at once Design for stability & tool-to-tool matching Maximize throughput at highest sensitivity Key technology features Reflected & scattered channels Full wafer inspection in seconds Three inspection channels: Visible darkfield Visible brightfield NIR Large depth of focus inspect single or multiple bonded wafers w/o autofocus Vis/IR for surface and sub-surface defect detection Edge inspection 3

4 Combined Reflected & Scattered Light Inspection Capture reflected and scattered light images for every wafer See complementary defects in the two channels Combined analysis increases chance to detect Defects of Interest Example: Post-Grinding Inspection Reflected Scattered 4

5 Nanda in 3D Process Flow TSV formation and temporary Bonding/Thinning inspection is critical to ensure wafer-to-wafer (W2W) high yield Nanda Spark can cover a wide range of 3D integration processes on silicon and glass carriers FEOL (Frontside, Backside, Edge) TSV Formation BEOL (Passivation, Poly-Imide) Bonding Thinning Backside Processing Device Wafer Carrier Wafer Incoming inspection Particle check Edge Trimming Temp Glue spinning Clean Check Temp Glue defects Wafer to Carrier Temp bonding Wafer thinning By grinding Grinding damage Removal & clean Dry Etch (TSV exposed) CVD Debond 5

6 Bond Layer Inspection Through Si Carrier Large depth of focus: No focus adjustment needed o Inspect full thickness and thinned bonded wafer pairs Distinguish different types of bonding layer defects: o Air bubbles, embedded particles, delamination Device Wafer Carrier Wafer Nanda one-shot NIR full wafer inspection: 30 s high resolution, high contrast Fully automated, atmospheric inspection Scanning Accoustic Microscope: 30 minutes high resolution but low contrast Requires manual loading into water bath 6

7 Bond Layer Inspection Through Si Carrier Detect: Re-flow of adhesive material during grinding Prethinning Wafer 1 Wafer 2 Localized thickness variations due to particles and/or bubbles Device Wafer Device Wafer Carrier Wafer Carrier Wafer Postthinning Device Wafer Wafer 3 Wafer 4 Interference fringes due to large area thickness variations Carrier Wafer 7

8 Image Gallery Post Grind Brightfield and Darkfield image gallery of surface defects Nanda Brightfield 1 2 Nanda Darkfield

9 Topography & Edge Analysis Large dimples and edge topography detected on thinned wafer Edge analysis: [um] [um] Mercator plot 0) Thinned wafer center shifted (sinusoidal curve) 9

10 Automated Defect Inspection, TTV & Bow/Warp Nanda full wafer brightfield + local small field-of-view metrology Brightfield Wafer Bow Thinned silicon wafer topography seen in Nanda brightfield is caused by glue layer TTV Thinned Si TTV Glue TTV Glue Mean/ TTV [um] Thin silicon Mean/ TTV [um] Bow/ Warp 43.44/ / /

11 Brightfield NIR Sematech Workshop on 3D Interconnect Metrology, July Combination Full Wafer BF and NIR Inspection NIR images identifies voids at location of dimple surface defect detected in brightfield images Slot 1 Visible Brightfield Images Slot 2 NIR Images Shows voids at location of dimples seen in Brightfield Slot 1 Slot 2 Slot 9 Slot 10 Slot 9 Slot 10 11

12 SAM vs. Nanda Surface and Bond Layer Inspection SAM Inspection Nanda Tech Brightfield Inspection Nanda Tech NIR Inspection TTV Data 12

13 Bond Layer Inspection Through Si Carrier Carrier Wafer Side DRAM product wafer bonded to Si carrier Carrier Wafer Side Nanda Tech NIR Inspection Void detection 30s integration time SAM Inspection for voids High Resolution Scans 40 min scan time 13

14 Through Si Carrier Bond Layer Void Inspection Carrier Wafer Side SAM Inspection Void High Resolution Scan Nanda Tech NIR Inspection Detected Voids 14

15 Combination of Unique Capabilities for 3D/TSV Sematech Workshop on 3D Interconnect Metrology, July Post-Grinding: BF inspection of dimples, grinding topography, chipping & edge Post-Grinding: DF inspection of residual silicon thickness & exposed Cu vias Post-Bonding: NIR Inspection of voids, delamination & embedded particles Dimples Bond layer inclusion & voids Delamination Exposed Cu nails Bow/Warp Glue Layer TTV Large scale defects often missed by traditional inspection 15

16 Summary Nanda provides control solution for TSV processes in R&D and production Automatic classification of critical vs. non-critical defects High Throughput 100% lot/wafers/dies inspection Low cost of ownership Lowest $ spent per measured wafer Use Nanda data for Advanced Process Control (APC) loops o Feedforward to recess etch o Feedback loop to Bonder/Grinder/TSV etch Nanda Spark module can be directly integrated into bonder, de-bonder, grinder FEOL & BEOL TSV Formation Back-End Bonding Thinning Backside processing CD, density Defectivity Depth, Profile Incoming inspection Device Trimming Bonding quality Wafer to Wafer alignment Wafer edge defects Post-Grinding Clean Particles, Dimples, Copper Nail Exposure, Delamination, Edge, Particles in Glue Recess Etch Particles, Scratches, Edge, Exposed Copper Nails 16