MMOD-UK-XC2C Xilinx XC2C128 CPLD development kit Getting started guide
|
|
|
- August McBride
- 5 years ago
- Views:
Transcription
1 Xilinx XC2C128 CPLD development kit Ver /08/2007
2 History Version Date Changes Author /08/2007 Initial version MM99 Page 2 of /08/2007
3 Table of contents Table of Contents Table of Contents... 3 Introduction... 4 Key Features... 5 Schematics... 6 Development software Create rcgen.ise project... 8 Schematics entry Pins assignment Generate the programming file Configure the device Page 3 of /08/2007
4 Introduction Introduction MMOD-UK-XC2C is a low-cost development kit for the Xilinx Cool Runner II XC2C128 CPLD with 128 macrocells. The kit includes: MMOD-UK-SO-DIMM144-MB ultra low-cost mother board for Mental Modular SO-DIMM144 suited embedded modules MMOD-EM-XC2C XC2C128 based embedded module MMOD-DT-XPROG-LPT-III-100 Xilinx Parallel Cable III low-cost clone Page 4 of /08/2007
5 Key features Key Features Xilinx Cool Runner II CPLD - XC2C128-7VQG100C in VQFP100 package 3.3V/1A LDO voltage regulator 1.8V/1A LDO voltage regulator Power supply presence red LED JTAG connector RC group for creating a RC-oscillator Crystal clock oscillator in the range MHz (Optional) USB connector for powering the kit from the USB port Eight LEDs connected to the CPLD I/Os 4 buttons connected to the CPLD I/Os 4-way DIP switch connected to the CPLD I/Os Three jumpers for configuration of the inputs and outputs of the attached module MMOD-DT-XPROG-LPT-III-100 Xilinx Parallel Cable III low-cost clone, used to flash the CPLD Wide prototyping area Two standart SMD component footprints (SOP-16 and SOP-20) for more convenient usage of the board Easily expandable with other SO-DIMM144 embedded modules. For more details please refer to the corresponding kit s components datasheets available on our website. Page 5 of /08/2007
6 Schematics Schematics Look at the kit s components schematics. Page 6 of /08/2007
7 Schematics Development software A variety of different software development tools are available for Xilinx complex programmable logic devices (CPLD) and field programmable gate arrays (FPGA). Such are: - Altium Designer - ISE Foundation - ISE WebPACK Here we ll use Xilinx ISE WebPACK, due to its unique features: A free, downloadable PLD design environment for both Microsoft Windows and Linux! The industry's fastest timing closure with Xilinx SmartCompile technology All the tools and features of ISE Foundation, including the Xilinx CORE Generator system and FPGA Editor The easiest, lowest cost way to get started with the industry leader for price and performance Support for Xilinx industry leading CPLD and FPGA families, including the Virtex-5 Family of platform FPGAs Fmax technology, an industry-unique combination of capabilities that solve logic engineers number 1 design challenge timing closure Easily upgradeable to ISE Foundation from the Xilinx Online Store Go to Xilinx website ( download for free and register your ISE WebPACK. Here we ll not go in details about the downloading, installation and product registration, because it s quite easy and we do not consider you ll have any problems with this, but if you have any problems don t hesitate to contact us at support@mentalmod.com. Page 7 of /08/2007
8 Here we ll describe a simple project implement a low-frequency RC-oscillator and connect its output to a 8-bit counter with a 10-bit prescaler, counter outputs are connected to the 8 LEDs on the MMOD-UK- SO-DIMM144-MB-100. Create rcgen.ise project Go to Start>Programs>Xilinx ISE9.1i>Project Navigator You go to the following view Now go to File>New Project Page 8 of /08/2007
9 Enter Project Name: rcgen, Project Location and Top-Level Source Type: Schematic. Then click Next>. Page 9 of /08/2007
10 Click on New Source. Click the Next> button and Finnish in the next window. Page 10 of /08/2007
11 Click the Next> button and Finnish in the next window. Click the Finnish button. Now you go to the following view: Page 11 of /08/2007
12 The next step is: Schematics entry Use the schematic editor to enter the following schematic: Page 12 of /08/2007
13 While drawing the schematic you could go to the C:/Xilinx91i/doc/usenglish/de/libs/lib directory and browse it to find out more about the symbols which could be used. After you have entered the schematic, go to the next step: Pins assignment You could either use the PACE, by starting it in the processes explorer tree: Or by editing the text constraints in the rcgen.ucf file by clicking on Edit Constraints (Text) Page 13 of /08/2007
14 Now edit the rcgen.ucf file. Enter the following: # RC generator pins NET "H139" LOC = P37; NET "H139" IOSTANDARD = LVCMOS33; NET "H141" LOC = P39; NET "H141" IOSTANDARD = LVCMOS33 FLOAT SCHMITT_TRIGGER ; # Outputs NET "H111" LOC = P17; NET "H111" IOSTANDARD = LVCMOS33; NET "H113" LOC = P18; NET "H113" IOSTANDARD = LVCMOS33; NET "H115" LOC = P19; NET "H115" IOSTANDARD = LVCMOS33; NET "H117" LOC = P22; NET "H117" IOSTANDARD = LVCMOS33; NET "H119" LOC = P24; NET "H119" IOSTANDARD = LVCMOS33; NET "H121" LOC = P27; NET "H121" IOSTANDARD = LVCMOS33; NET "H123" LOC = P28; NET "H123" IOSTANDARD = LVCMOS33; NET "H125" LOC = P29; NET "H125" IOSTANDARD = LVCMOS33; Page 14 of /08/2007
15 Generate the programming file Double click on Generate Programming File. Configure the device Page 15 of /08/2007
Laboratory #Intro to Xilinx ISE and CR-2 Kit ECE 332
Name: G Number: 1 Introduction Laboratory #Intro to Xilinx ISE and CR-2 Kit ECE 332 The purpose of this laboratory is to introduce the design tools used in ECE 332 lab. In this lab you will learn about
Copyright 2011 R.S.R. Electronics, Inc. All rights reserved. 04/11. Ver. 1.0web
For XILINX WebPack Copyright 2011 R.S.R. Electronics, Inc. All rights reserved. 04/11 Ver. 1.0web 1 Table of Contents 1.0 INTRODUCTION...3 2.0 GENERAL DESCRIPTION...5 3.0 BRIEF DESCRIPTION Of PLDT-3 BOARD...6
Melon S3 FPGA Development Board Product Datasheet
Melon S3 FPGA Development Board Product Datasheet The Melon S3 FPGA is open-source, expandable development board perfect for the learning digital circuit design and prototyping of your unique ideas. You
Setup/Hold. Set Up time (t su ):
Lecture 10 Agenda Set Up time (t su ): Setup/Hold Minimum amount of time the data is to be held steady prior to the clock event Hold time (t h ): Minimum amount of time the data is to be held steady after
Revision: February 27, E Main Suite D Pullman, WA (509) Voice and Fax
Xilinx ISE WebPACK Schematic Capture Tutorial Revision: February 27, 2010 215 E Main Suite D Pullman, WA 99163 (509) 334 6306 Voice and Fax Overview This tutorial provides instruction for using the Xilinx
TLL5000 Electronic System Design Base Module
TLL5000 Electronic System Design Base Module The Learning Labs, Inc. Copyright 2007 Manual Revision 2007.12.28 1 Copyright 2007 The Learning Labs, Inc. Copyright Notice The Learning Labs, Inc. ( TLL )
CPLD board datasheet EB
CPLD board datasheet EB020-00-3 Contents. About this document... 2 2. General information... 3 3. Board layout... 4 4. Testing this product... 5 5. Circuit description... 6 Appendix Circuit diagram Copyright
TLL5000 Electronic System Design Base Module. Getting Started Guide, Ver 3.4
TLL5000 Electronic System Design Base Module Getting Started Guide, Ver 3.4 COPYRIGHT NOTICE The Learning Labs, Inc. ( TLL ) All rights reserved, 2008 Reproduction in any form without permission is prohibited.
Xilinx ISE Synthesis Tutorial
Xilinx ISE Synthesis Tutorial The following tutorial provides a basic description of how to use Xilinx ISE to create a simple 2-input AND gate and synthesize the design onto the Spartan-3E Starter Board
Chameleon POD Specification v1.2
Chameleon POD Specification v1.2 amt.chm.ug.000 / version v1.2 / 10.09.2002 by Laurent Gauch Amontec Logic Road 123 Sur Vigne CH-1641 Vuippens Switzerland SUMMARY This document is the official specification
Nexys 2/3 board tutorial (Decoder, ISE 13.2) Jim Duckworth, August 2011, WPI. (updated March 2012 to include Nexys2 board)
Nexys 2/3 board tutorial (Decoder, ISE 13.2) Jim Duckworth, August 2011, WPI. (updated March 2012 to include Nexys2 board) Note: you will need the Xilinx ISE Webpack installed on your computer (or you
EE 367 Logic Design Lab #1 Introduction to Xilinx ISE and the ML40X Eval Board Date: 1/21/09 Due: 1/28/09
EE 367 Logic Design Lab #1 Introduction to Xilinx ISE and the ML40X Eval Board Date: 1/21/09 Due: 1/28/09 Lab Description Today s lab will introduce you to the Xilinx Integrated Software Environment (ISE)
Revision: February 27, E Main Suite D Pullman, WA (509) Voice and Fax
Xilinx ISE WebPACK VHDL Tutorial Revision: February 27, 2010 215 E Main Suite D Pullman, WA 99163 (509) 334 6306 Voice and Fax Overview This tutorial provides simple instruction for using the Xilinx ISE
CPLD Experiment 4. XOR and XNOR Gates with Applications
CPLD Experiment 4 XOR and XNOR Gates with Applications Based on Xilinx ISE Design Suit 10.1 Department of Electrical & Computer Engineering Florida International University Objectives Materials Examining
Virtex-6 FPGA ML605 Evaluation Kit FAQ June 24, 2009
Virtex-6 FPGA ML605 Evaluation Kit FAQ June 24, 2009 Getting Started Q: Where can I purchase a kit? A: Once the order entry is open, you can purchase your ML605 kit online at: http://www.xilinx.com/onlinestore/v6_boards.htm
Virtex 6 FPGA Broadcast Connectivity Kit FAQ
Getting Started Virtex 6 FPGA Broadcast Connectivity Kit FAQ Q: Where can I purchase a kit? A: Once the order entry is open, you can purchase your Virtex 6 FPGA Broadcast Connectivity kit online or contact
Tutorial: Working with Verilog and the Xilinx FPGA in ISE 9.2i
Tutorial: Working with Verilog and the Xilinx FPGA in ISE 9.2i This tutorial will show you how to: Use Verilog to specify a design Simulate that Verilog design Define pin constraints for the FPGA (.ucf
ISE Design Suite Software Manuals and Help
ISE Design Suite Software Manuals and Help These documents support the Xilinx ISE Design Suite. Click a document title on the left to view a document, or click a design step in the following figure to
Spartan-II Demo Board User s Guide
Spartan-II Demo Board User s Guide Version.2 May 200 Overview The Spartan-II Demo Board is a low cost evaluation platform for testing and verifying designs based on the Xilinx Spartan-II family of FPGA
Xilinx ISE8.1 and Spartan-3 Tutorial EE3810
Xilinx ISE8.1 and Spartan-3 Tutorial EE3810 1 Part1) Starting a new project Simple 3-to-8 Decoder Start the Xilinx ISE 8.1i Project Navigator: Select File > New Project in the opened window 2 Select a
Guide ISE14. ISE 14.2 (Xilinx) Designflow 1/12
Guide ISE14 ISE 14.2 (Xilinx) Designflow 1/12 Inhaltsverzeichnis 1. Create a Project 3 2. Select a Device 4 3. Add the Sourcecodes 5 4. File for the Pinning 6 5. Synthesis 7 6. Implementation 8 7. Programming
Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE
FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6 ACCESS IC LAB Outline Concepts of Xilinx FPGA Xilinx FPGA Architecture Introduction to ISE Code Generator Constraints
Microbee Technology FTM-3SE
Microbee Technology FTM-3SE Freescale Tower System Compatible Field Programmable Gate Array Module TWR-K70 Demo Quick Start Guide The flexibility that programmable logic brings to hardware design has now
[Guide Subtitle] [optional]
![[Guide Subtitle] [optional]](/thumbs/76/74467225.jpg "[Guide Subtitle] [optional]")
[Guide CoolRunner-II Title] Common Evaluation UG Board Template Reference Set Manual [Guide Subtitle] [optional] UG000 UG501 (v1.0) (v5.0) May August 15, 24, 2008 2007 [optional] R R Xilinx is disclosing
Logic Implementation on a Xilinx FPGA using VHDL WWU Linux platform assumed. rev 10/25/16
1 Logic Implementation on a Xilinx FPGA using VHDL WWU Linux platform assumed. rev 10/25/16 The following is a general outline of steps (i.e. design flow) used to implement a digital system described with
MINI-CAN User Manual. Issue 1.02
MINI-CAN User Manual Issue 1.02 Kit Contents You should receive the following items in your MINI-CAN development kit: 1 - MINI-CAN Board 2 Programming Cable Figure 1 MINI-CAN Board Introduction Welcome
XILINX ISE AND SPARTAN 3AN TUTORIAL
XILINX ISE AND SPARTAN 3AN TUTORIAL SYNTETIZE AND SIMULATION------------------------------------------ This tutorial will show you how to create a simple Xilinx ISE project based on the Spartan-3 Board.
Nios Embedded Processor Development Board
Nios Embedded Processor Development Board July 2003, ver. 2.2 Data Sheet Introduction Development Board Features Functional Overview This data sheet describes the features and functionality of the Nios
Physics 623. FPGA I Construction of a Synchronous Counter Aug. 4, 2008
Physics 623 FPGA I onstruction of a Synchronous ounter Aug. 4, 2008 1 The Goal of This Experiment You will design a small digital circuit, download the design to a Field Programmable Gate Array (FPGA)
CPLD board. EB020
CPLD board www.matrixtsl.com EB020 Contents About this document Board layout General information Circuit description Protective cover Circuit diagram 2 4 5 7 Copyright About this document This document
ECEN 449: Microprocessor System Design Department of Electrical and Computer Engineering Texas A&M University. Laboratory Exercise #1 Using the Vivado
ECEN 449: Microprocessor System Design Department of Electrical and Computer Engineering Texas A&M University Prof. Sunil P Khatri (Lab exercise created and tested by Ramu Endluri, He Zhou, Andrew Douglass
Pre-Laboratory #Boolean Expressions ECE 332
Name: G Number: Pre-Laboratory #Boolean Expressions ECE 332 1 Introduction This pre-lab is divided into two parts. In part one you will build a circuit for providing inputs to your CPLD board on your breadboard.
Hardware Manual - SM2251 Evaluation Kit Board
Hardware Manual - SM2251 Evaluation Kit Board Release 1.0.0 SonMicro Elektronik Oct 08, 2017 CONTENTS 1 INTRODUCTION 1 1.1 FEATURES............................................... 1 1.2 SUPPORTED MODULES.......................................
Opal Kelly. XEM3001v2 User s Manual. A business-card sized (3.5 x 2.0 ) experimentation board featuring the Xilinx Spartan 3 FPGA.
Opal Kelly XEM3001v2 User s Manual A business-card sized (3.5 x 2.0 ) experimentation board featuring the Xilinx Spartan 3 FPGA. The XEM3001 is a small, business-card sized FPGA board featuring the Xilinx
Logic Implementation on a Xilinx FPGA using VHDL WWU Linux platform assumed. rev 11/01/17
1 Logic Implementation on a Xilinx FPGA using VHDL WWU Linux platform assumed. rev 11/01/17 The following is a general outline of steps (i.e. design flow) used to implement a digital system described with
ECEN 449: Microprocessor System Design Department of Electrical and Computer Engineering Texas A&M University. Laboratory Exercise #1 Using the Vivado
ECEN 449: Microprocessor System Design Department of Electrical and Computer Engineering Texas A&M University Prof. Sunil P. Khatri Lab exercise created and tested by: Abbas Fairouz, Ramu Endluri, He Zhou,
Board-Data Processing. VHDL Exercises. Exercise 1: Basics of VHDL Programming. Stages of the Development process using FPGA s in Xilinx ISE.
Board-Data Processing VHDL Exercises Exercise 1: Basics of VHDL Programming Stages of the Development process using FPGA s in Xilinx ISE. Basics of VHDL VHDL (Very High Speed IC Hardware description Language)
FPGA Development Board For Applications in Cosmic Rays Physics
Faculty of Mathematics & Natural Science FMNS 2013 FPGA Development Board For Applications in Cosmic Rays Physics Ivo Angelov 1, Svetla Dimitrova 2, Krasimir Damov 1 1 - South West University Neofit Rilski
Spartan-6 and Virtex-6 FPGA Embedded Kit FAQ
Spartan-6 and Virtex-6 FPGA FAQ February 5, 2009 Getting Started 1. Where can I purchase an Embedded kit? A: You can purchase your Spartan-6 and Virtex-6 FPGA Embedded kits online at: Spartan-6 FPGA :
Quick Start Guide for the Turbo upsd DK3300-ELCD Development Kit- RIDE
Contents: Circuit Board upsd DK3300-ELCD Development Board with a upsd3334d-40u6 MCU with Enhanced Graphic LCD RLINK-ST, a USB-based JTAG adapter from Raisonance for debugging with Raisonance Integrate
CPE 200L LABORATORY 4: INTRODUCTION TO DE2 BOARD UNIVERSITY OF NEVADA, LAS VEGAS GOALS: BACKGROUND:
CPE 200L LABORATORY 4: INTRODUCTION TO DE2 BOARD DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING UNIVERSITY OF NEVADA, LAS VEGAS GOALS: Getting familiar with DE2 board installation, properties, usage.
Digilab 2 XL Reference Manual
125 SE High Street Pullman, WA 99163 (509) 334 6306 (Voice and Fax) www.digilentinc.com PRELIMINARY Digilab 2 XL Reference Manual Revision: May 7, 2002 Overview The Digilab 2 XL (D2XL) development board
Compute Node Design for DAQ and Trigger Subsystem in Giessen. Justus Liebig University in Giessen
Compute Node Design for DAQ and Trigger Subsystem in Giessen Justus Liebig University in Giessen Outline Design goals Current work in Giessen Hardware Software Future work Justus Liebig University in Giessen,
SMT943 APPLICATION NOTE 1 APPLICATION NOTE 1. Application Note - SMT372T and SMT943.doc SMT943 SUNDANCE MULTIPROCESSOR TECHNOLOGY LTD.
APPLICATION NOTE 1 Application Note - SMT372T + SMT943 SMT943 SUNDANCE MULTIPROCESSOR TECHNOLOGY LTD. Date Comments / Changes Author Revision 07/07/10 Original Document completed CHG 1 Date 13/05/2010
S2C K7 Prodigy Logic Module Series
S2C K7 Prodigy Logic Module Series Low-Cost Fifth Generation Rapid FPGA-based Prototyping Hardware The S2C K7 Prodigy Logic Module is equipped with one Xilinx Kintex-7 XC7K410T or XC7K325T FPGA device
DESIGN SPECIFICATION FOR SMT318-SX55. Copyright Sundance
DESIGN SPECIFICATION FOR SMT318-SX55 Copyright Sundance All rights reserved. No part of this document may be reproduced, translated, stored in a retrieval system, or transmitted, in any form or by any
Programming Xilinx SPARTAN 3 Board (Simulation through Implementation)
Programming Xilinx SPARTAN 3 Board (Simulation through Implementation) September 2008 Prepared by: Oluwayomi Adamo Class: Project IV University of North Texas FPGA Physical Description 4 1. VGA (HD-15)
Revision: May 11, E Main Suite D Pullman, WA (509) Voice and Fax LED. Doc: page 1 of 6
Digilent XC2-XL System Board Reference Manual www.digilentinc.com Revision: May 11, 2004 215 E Main Suite D Pullman, WA 99163 (509) 334 6306 Voice and Fax Overview The Digilent XC2-XL System Board (the
ELEC 204 Digital System Design LABORATORY MANUAL
ELEC 204 Digital System Design LABORATORY MANUAL : Introductory Tutorial For Xilinx ISE Foundation v10.1 & Implementing XOR Gate College of Engineering Koç University Important Note: In order to effectively
Evaluation of the RTL Synthesis Tools for FPGA/PLD Design. M.Matveev. Rice University. August 10, 2001
Evaluation of the RTL Synthesis Tools for FPGA/PLD Design M.Matveev Rice University August 10, 2001 Xilinx: Foundation ISE Design Entry: VHDL, Verilog, schematic, ABEL Synthesis: Xilinx XST, Synopsys FPGA
On the Fly Reconfiguration with CoolRunner-II CPLDs
Application Note: CoolRunner-II CPLDs XAPP388 (v1.2) May 15, 2003 R On the Fly Reconfiguration with CoolRunner-II CPLDs Summary This application notes describes the CoolRunner -II CPLD capability called
Typical applications where a CPLD may be the best design approach:
By: Carlos Barberis, dba Bartek Technologies Description of Bartek s CPLD1 development board. For some of us CPLD s are familiar devices and for others just another acronym in the electronic device industry.
Xilinx Tutorial Basic Walk-through
Introduction to Digital Logic Design with FPGA s: Digital logic circuits form the basis of all digital electronic devices. FPGAs (Field Programmable Gate Array) are large programmable digital electronic
TPMC632. Reconfigurable FPGA with 64 TTL I/O / 32 Differential I/O Lines. Version 1.0. User Manual. Issue January 2012
The Embedded I/O Company TPMC632 Reconfigurable FPGA with 64 TTL I/O / 32 Differential I/O Lines Version 1.0 User Manual Issue 1.0.0 January 2012 TEWS TECHNOLOGIES GmbH Am Bahnhof 7 25469 Halstenbek, Germany
MICROCONTROLLER S PROGRAMMER
MICROCONTROLLER S PROGRAMMER Todor Mladenov Mladenov, Vladimir Mladenov Mladenov Faculty of Communications and Communications Technologies, Faculty of Computer Systems and Control, Technical University
Implementing a Verilog design into the UWEE CPLD Development Board Using Xilinx s ISE 7.1i Software: A Tutorial
Implementing a Verilog design into the UWEE CPLD Development Board Using Xilinx s ISE 7.1i Software: A Tutorial Revision 0 By: Evan Gander Materials: The following are required in order to complete this
Sidewinder Development Board rev 1.0
33 Sidewinder Development Board rev 1.0 Features Altera MAX V CPLD 5M160ZT100C5 JTAG programmable USB programmable USB powered 12 On board LEDs 10 on board switches 3 RGB LEDs One 40 pin expansion headers
Cmod Board Reference Manual. Overview. 1 Functional Description. Revised October 26, 2012 This manual applies to the Cmod rev. D
1300 Henley Court Pullman, WA 99163 509.334.6306 www.digilentinc.com Cmod Board Reference Manual Revised October 26, 2012 This manual applies to the Cmod rev. D Overview Cmod boards combine a Xilinx CPLD,
QWaveSystems / Melon_S3_FPGA
QWaveSystems / Melon_S3_FPGA A Open-source Hardware : WiFi (ESP8266) FPGA Development Kit Edit Add topics 201 commits 1 branch 0 releases 1 contributor Branch: master New pull request Create new file Upload
KC705 PCIe Design Creation with Vivado August 2012
KC705 PCIe Design Creation with Vivado August 2012 XTP197 Revision History Date Version Description 08/20/12 1.0 Initial version. Added AR50886. Copyright 2012 Xilinx, Inc. All Rights Reserved. XILINX,
475 Electronics for physicists Introduction to FPGA programming
475 Electronics for physicists Introduction to FPGA programming Andrej Seljak, Gary Varner Department of Physics University of Hawaii at Manoa November 18, 2015 Abstract Digital circuits based on binary
Spartan-6 LX9 MicroBoard Embedded Tutorial. Lab 6 Creating a MicroBlaze SPI Flash Bootloader
Spartan-6 LX9 MicroBoard Embedded Tutorial Lab 6 Creating a MicroBlaze SPI Flash Bootloader Version 13.1.01 Revision History Version Description Date 13.1.01 Initial release for EDK 13.1 5/17/11 Table
CHAPTER 1 Introduction of the tnano Board CHAPTER 2 tnano Board Architecture CHAPTER 3 Using the tnano Board... 8
CONTENTS CHAPTER 1 Introduction of the tnano Board... 2 1.1 Features...2 1.2 About the KIT...4 1.3 Getting Help...4 CHAPTER 2 tnano Board Architecture... 5 2.1 Layout and Components...5 2.2 Block Diagram
Programmable Logic Design I
Programmable Logic Design I Introduction In labs 11 and 12 you built simple logic circuits on breadboards using TTL logic circuits on 7400 series chips. This process is simple and easy for small circuits.
NEXYS4DRR board tutorial
NEXYS4DRR board tutorial (VHDL Decoder design using Vivado 2015.1) Note: you will need the Xilinx Vivado Webpack version installed on your computer (or you can use the department systems). This tutorial
TPMC632. Reconfigurable FPGA with 64 TTL I/O / 32 Differential I/O Lines. Version 1.0. User Manual. Issue November 2017
The Embedded I/O Company TPMC632 Reconfigurable FPGA with 64 TTL I/O / 32 Differential I/O Lines Version 1.0 User Manual Issue 1.0.6 November 2017 TEWS TECHNOLOGIES GmbH Am Bahnhof 7 25469 Halstenbek,
Gate Estimate. Practical (60% util)* (1000's) Max (100% util)* (1000's)
The Product Brief October 07 Ver. 1.3 Group DN9000K10PCIe-4GL XilinxVirtex-5 Based ASIC Prototyping Engine, 4-lane PCI Express (Genesys Logic PHYs) Features PCI Express (4-lane) logic prototyping system
CPLD board datasheet EB
CPLD board datasheet EB020-00- Contents. About this document... 2 2. General information... 3 3. Board layout... 4 4. Testing this product... 5 5. Circuit description... 6 Appendix Circuit diagram Copyright
FPGA Design Flow. - from HDL to physical implementation - Victor Andrei. Kirchhoff-Institut für Physik (KIP) Ruprecht-Karls-Universität Heidelberg
FPGA Design Flow - from HDL to physical implementation - Victor Andrei Kirchhoff-Institut für Physik (KIP) Ruprecht-Karls-Universität Heidelberg 6th Detector Workshop of the Helmholtz Alliance Physics
FPGA Discovery-III XC3S200 Board Manual
FPGA Discovery-III XC3S200 Board Manual 77/9 SOI LADPRAO 1, LADPRAO ROAD, JOMPOL, JATUJAK DISTRICT, BANGKOK THAILAND 10900 TEL. 66(0)2939-2084 FAX.66(0)2939-2084 http://www.ailogictechnology.com 1 FPGA
The board is powered by the USB connection, so to turn it on or off you plug it in or unplug it, respectively.
Lab 1 You may work in pairs or individually on this lab Lab Objectives Learn about the equipment we will be using and how to handle it safely. Learn the basics of using Xilinx ISE to develop hardware designs
Circuit design with configurable devices (FPGA)
1 Material Circuit design with configurable devices (FPGA) Computer with Xilinx's ISE software installed. Digilent's Basys2 prototype board and documentation. Sample design files (lab kit). Files and documents
Tutorial on FPGA Design Flow based on Xilinx ISE Webpack and ModelSim. ver. 1.3
Tutorial on FPGA Design Flow based on Xilinx ISE Webpack and ModelSim ver. 1.3 1 Prepared by Marcin Rogawski, Ekawat (Ice) Homsirikamol, Kishorekum Surapathi, and Dr. Kris Gaj The example codes used in
Introduction to WebPACK 6.3. Using Xilinx WebPACK Software to Create FPGA Designs for the XSA Board
Introduction to WebPACK 6.3 Using Xilinx WebPACK Software to Create FPGA Designs for the XSA Board Release date: 1/1/2005 2005 by XESS Corp. All XS-prefix product designations are trademarks of XESS Corp.
KALI Technical Manual. This document covers the Technical Details of KALI
KALI Technical Manual This document covers the Technical Details of KALI 1 KALI RECLOCKER The Kali takes the digital audio signals (I2S) from Sparky SBC or RPI through the on board FPGA based FIFO and
Digilab 2 Reference Manual
125 SE High Street Pullman, WA 99163 (509) 334 6306 (Voice and Fax) www.digilentinc.com PRELIMINARY Digilab 2 Reference Manual Revision: November 19, 2001 Overview The Digilab 2 (D2) development board
SP601 Standalone Applications
SP601 Standalone Applications December 2009 Copyright 2009 Xilinx XTP053 Note: This presentation applies to the SP601 Overview Xilinx SP601 Board Software Requirements SP601 Setup Multi-pin Wake-up GPIO
Tutorial: ISE 12.2 and the Spartan3e Board v August 2010
Tutorial: ISE 12.2 and the Spartan3e Board v12.2.1 August 2010 This tutorial will show you how to: Use a combination of schematics and Verilog to specify a design Simulate that design Define pin constraints
Zynq AP SoC Family
Programmable Logic (PL) Processing System (PS) Zynq -7000 AP SoC Family Cost-Optimized Devices Mid-Range Devices Device Name Z-7007S Z-7012S Z-7014S Z-7010 Z-7015 Z-7020 Z-7030 Z-7035 Z-7045 Z-7100 Part
Introduction to WebPACK 8.1. Using Xilinx WebPACK Software to Create FPGA Designs for the XSA Board
Introduction to WebPACK 8.1 Using Xilinx WebPACK Software to Create FPGA Designs for the XSA Board Release date: 5/16/2005 2006 by XESS Corp. All XS-prefix product designations are trademarks of XESS
Opal Kelly. XEM6002 User s Manual
Opal Kelly XEM6002 User s Manual A business-card sized (3.5 x 2.0 ) semiconductor evaluation platform featuring the Xilinx Spartan-6 FPGA and four Pmod TM connectors. The XEM6002 is a small, business-card
Graduate Institute of Electronics Engineering, NTU. FPGA Lab. Speaker : 鍾明翰 (CMH) Advisor: Prof. An-Yeu Wu Date: 2010/12/14 ACCESS IC LAB
FPGA Lab Speaker : 鍾明翰 (CMH) Advisor: Prof. An-Yeu Wu Date: 2010/12/14 ACCESS IC LAB Objective In this Lab, you will learn the basic set-up and design methods of implementing your design by ISE 10.1. Create
Universal VLSI Protoboard
Universal VLSI Protoboard ni logic Pvt. Ltd., 25/B5, Bandal Complex, Paud Road, Kothrud, Pune 411 038. Maharashtra. Tele-Fax: + 91-20 - 2528 6948 info@ni2designs.com www.ni2designs.com Universal VLSI Protoboard
CS/EE Prerequsites. Hardware Infrastructure. Class Goal CS/EE Computer Design Lab. Computer Design Lab Fall 2010
CS/EE 3710 Computer Design Lab Fall 2010 CS/EE 3710 Computer Design Lab T Th 3:40pm-5:00pm Lectures in WEB 110, Labs in MEB 3133 (DSL) Instructor: Erik Brunvand MEB 3142 Office Hours: After class, when
CS/EE Computer Design Lab Fall 2010 CS/EE T Th 3:40pm-5:00pm Lectures in WEB 110, Labs in MEB 3133 (DSL) Instructor: Erik Brunvand
CS/EE 3710 Computer Design Lab Fall 2010 CS/EE 3710 Computer Design Lab T Th 3:40pm-5:00pm Lectures in WEB 110, Labs in MEB 3133 (DSL) Instructor: Erik Brunvand MEB 3142 Office Hours: After class, when
Spartan-6 LX9 MicroBoard Embedded Tutorial. Tutorial 2 Adding EDK IP to an Embedded System
Spartan-6 LX9 MicroBoard Embedded Tutorial Tutorial 2 Adding EDK IP to an Embedded System Version 13.1.01 Revision History Version Description Date 13.1.01 Initial release for EDK 13.1 5/16/2011 Table
Revision: 5/7/ E Main Suite D Pullman, WA (509) Voice and Fax. Power jack 5-9VDC. Serial Port. Parallel Port
Digilent Digilab 2 Reference Manual www.digilentinc.com Revision: 5/7/02 215 E Main Suite D Pullman, WA 99163 (509) 334 6306 Voice and Fax Overview The Digilab 2 development board (the D2) features the
Programmable Logic Design I
Programmable Logic Design I Read through each section completely before starting so that you have the benefit of all the directions. Put on a grounded wrist strap (cf. Getting Started) before touching
Digilab 2E Reference Manual
Digilent 2E System Board Reference Manual www.digilentinc.com Revision: February 8, 2005 246 East Main Pullman, WA 99163 (509) 334 6306 Voice and Fax Digilab 2E Reference Manual Overview The Digilab 2E
University of Hawaii EE 361L. Getting Started with Spartan 3E Digilent Basys2 Board. Lab 4.1
University of Hawaii EE 361L Getting Started with Spartan 3E Digilent Basys2 Board Lab 4.1 I. Test Basys2 Board Attach the Basys2 board to the PC or laptop with the USB connector. Make sure the blue jumper
ZL10AVR. Versatile Evaluation Board for AVR Microcontrollers
Versatile Evaluation Board for AVR Microcontrollers Thank you for buying ZL10AVR evaluation board. We hope that the power and quality of our tool allow you to appreciate the advantages of AVR microcontrollers
EE 1315 DIGITAL LOGIC LAB EE Dept, UMD
EE 1315 DIGITAL LOGIC LAB EE Dept, UMD EXPERIMENT # 1: Logic building blocks The main objective of this experiment is to let you familiarize with the lab equipment and learn about the operation of the
Using Synplify Pro, ISE and ModelSim
Using Synplify Pro, ISE and ModelSim VLSI Systems on Chip ET4 351 Rene van Leuken Huib Lincklaen Arriëns Rev. 1.2 The EDA programs that will be used are: For RTL synthesis: Synplicity Synplify Pro For
Board Module. for. FPGA Family
EVALXCS User Manual Board Module for FPGA Family EVALXCS User Manual 2/2 Manual: EVALXCS Version 1.1 August 1999 EVALXCS Version 1.2 October 1999 This manual describes the technical properties and the
Enabling success from the center of technology. A Practical Guide to Configuring the Spartan-3A Family
A Practical Guide to Configuring the Spartan-3A Family Goals 2 Explain advantages and disadvantages of each configuration mechanism available for Spartan-3A Show how to use an industry standard flash for
MB95260H/MB95270H. MB95280H Series. MB95260H Series/MB95270H Series/
F 2 MC-8FX Family 8-bit Microcontroller MB95260H Series/MB95270H Series/ General-purpose, low pin count package MB95260H Series, MB95270H Series, and with dual-operation Flash memory that can address EEPROM
GODIL USER MANUAL V 0.9 OHO-Elektronik
GODIL USER MANUAL V 0.9 OHO-Elektronik www.oho-elektronik.de Author: M.Randelzhofer OHO-Elektronik Michael Randelzhofer Rudolf-Diesel-Str. 8 85221 Dachau Germany WEB: www.oho-elektronik.de EMAIL: info@oho-elektronik.de
VHDL introduction Notes
UH Hawaii Manoa 475 Electronics for physicists VHDL introduction Notes Author: Andrej Seljak Date: Fall 2016 update 1 Ver: 1.0 Table of Contents 1. FPGA description3 2. USB EVALUATION board 4 3. ISE Xilinx
Tutorial on FPGA Design Flow based on Xilinx ISE Webpack and ModelSim. ver. 1.5
Tutorial on FPGA Design Flow based on Xilinx ISE Webpack and ModelSim ver. 1.5 1 Prepared by Marcin Rogawski, Ekawat (Ice) Homsirikamol, Kishore Kumar Surapathi and Dr. Kris Gaj The example codes used
MMusb245RL User s manual. Many ideas one solution
MMusb245RL User s manual PIC microcontrollers Sta- Evalu ation Board s for 51, AVR, ST, rter Kits Embedded Web Serve rs Prototyping Boards Minimod- AVR, PIC, ST microcontrollers Microprocesor systems,