Unpipelined Multicycle Datapath Implementation

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1 Unpipelined Multicycle Datapath Implementation Adapted from instructor s supplementary material from Computer Organization and Design, 4 th Edition, Patterson & Hennessy, 8, MK] and Computer Architecture: From Microprocessors to Supercomputers, B. Parhami, 5 Oxford Press

2 Review: Datapath With Jumps Added Chapter 4 The Processor

3 Review: Putting It All Together Fig..9 Fig. 3.4 IncrPC 3 NextPC 3 PCSrc Adder c in 4 MSBs SysCallAddr 3 BrTrue MSBs SE imm Branch condition checker BrType 3 MSBs (rt) (rs) (PC) 3: jta Constant amount Variable amount x y 5 5 Const Var Amount 5 3 Shift function Shifter No shift Logical left Logical right Arith right imm 5 LSBs Shifted y 3 Add Sub c Adder 3 c k c 3 3 x y 3 Function class or MSB 3 3 lui Shift Set less Arithmetic Logic s x Shorth symb for AL Cont Fun A Incr PC Next PC PC Next addr (PC) Instr cache inst op fn jta rd 3 imm rs rt Reg file 6 (rs) (rt) 3 SE Fig. 3.3 ALUOvfl Ovfl ALU Func ALU out Data addr Data in Register input Data cache Data out AND OR XOR NOR Logic unit Logic function input NOR Zero Ovfl y addinst subinst jinst... O Zero sltinst B&J Br&Jump RegDst RegWrite ALUSrc ALUFunc DataRead RegInSrc DtWit DataWrite Feb. Slide 3

4 Review: Performance Estimation for Single Cycle MicroMIPS Instruction access ns Register read ns ALU operation ns Data cache access ns Register write ns Total 8 ns Single-cycle clock = 5 MHz ALU-type Load Store P C P C P C R-type 44% 6 ns Load 4% 8ns Store % 7 ns Branch 8% 5 ns Jump % 3 ns Weighted mean 6.36 ns Branch (and jr) Jump (except jr & jal) P C P C Fig. 3.6 The MicroMIPS data path unfolded (by depicting the register write step as a separate block) so as to better visualize the critical-path latencies. Feb. Slide 4

5 Multicycle datapath implementation (with no pipelining)

6 Single Cycle vs. Multicycle MicroMIPS Clock Time needed Time allotted Instr Instr Instr 3 Instr 4 Clock Time needed Time allotted 3 cycles 5 cycles 3 cycles 4 cycles Instr Instr Instr 3 Instr 4 Time saved Fig. 4. Single-cycle versus multicycle instruction execution. Feb. Slide 6

7 A Multicycle Data Path PC Address Inst Reg jta x Reg rs,rt,rd (rs) z Reg Data Cache imm Reg file (rt) ALU Data Reg y Reg op fn von Neumann (Princeton) architecture Fig. 4. Abstract view of a multicycle instruction execution unit for MicroMIPS. For naming of instruction fields, see Fig. 3.. Feb. Slide 7

8 Multicycle Data Path with Signals Shown Three major changes relative to the single-cycle data path: PC. Instruction & data caches combined Corrections are shown in red Address Data Cache 6 4MSB MSBs 3 3. Registers added for intercycle data Inst Reg jta x Reg rs (rs) rt rd 3 Reg file (rt) Data Reg imm 6 3 y Reg SE. ALU performs double duty for address calculation x Mux y Mux SysCallAddr ALUZero ALUOvfl Zero Ovfl ALU Func z Reg ALU out op fn Inst Data MemWrite RegInSrc ALUSrcX ALUFunc PCWrite MemRead IRWrite RegDst RegWrite ALUSrcY JumpAddr Fig. 4.3 Key elements of the multicycle cle MicroMIPS data path. PCSrc Feb. Slide 8

9 4. Clock Cycle and Signals Table 4. signal 3 Program counter Cache Register file ALU JumpAddr jta SysCallAddr PCSrc,PCSrc Jump addr x reg z reg ALU out PCWrite Don t write Write Inst Data PC z reg MemRead Don t read Read MemWrite Don t write Wit Write IRWrite Don t write Write RegWrite Don t write Write RegDst,RegDst rt rd $3 RegInSrc,RegInSrc Data reg z reg PC ALUSrcX PC x reg ALUSrcY, ALUSrcY 4 y reg imm 4 imm Add Sub Add Subtract LogicFn, LogicFn AND OR XOR NOR FnClass, FnClass lui Set less Arithmetic Logic Feb. Slide 9

10 Multicycle Data Path, Repeated for Reference PC Corrections are shown in red Address Data Cache 6 4 MSBs 3 Inst Reg jta x Reg rs (rs) rt rd 3 Reg file (rt) Data Reg imm 6 3 y Reg SE 4 4 SysCallAddr 3 ALUZero x Mux ALUOvfl Zero z Reg 4 Ovfl ALU y Mux 3 Func 3 ALU out op Inst Data MemWrite PCWrite MemRead IRWrite fn RegInSrc RegDst RegWrite ALUSrcX ALUSrcY ALUFunc JumpAddr PCSrc Fig. 4.3 Key elements of the multicycle MicroMIPS data path. Feb. Slide

11 Execution Cycles Fetch & PC incr Decode & reg read ALU oper & PC update Table 4. Execution cycles for multicycle MicroMIPS Instruction Operations Signal settings Any Read out the instruction and Inst Data =, MemRead = write it into instruction IRWrite =, ALUSrcX = register, increment PC ALUSrcY =, PCSrc = 3, PCWrite = Any Read out rs & rt into x & y ALUSrcX =, ALUSrcY = 3 registers, compute branch address and save in z register ALU type Perform ALU operation and save the result in z register ALUSrcX =, ALUSrcY = or ALUFunc: Varies LoadStore Add base and offset values, save in z register ALUSrcX =, ALUSrcY = 3 Branch If (x reg) = < (y reg), set PC to branch target address ALUSrcX =, ALUSrcY = ALUFunc=, PCSrc = PCWrite = ALUZero or ALUZero or ALUOut 3 JumpAddr = or, PCSrc = or, PCWrite = Jump Set PC to the target address jta, SysCallAddr, or (rs) ALU type Write back z reg into rd RegDst =, RegInSrc = Reg write RegWrite = or mem 4 Load Read memory into data reg Inst Data =, MemRead = access Reg write for lw 5 Store Copy y reg into memory Inst Data =, MemWrite = Load Copy data register into rt RegDst =, RegInSrc = RegWrite = Feb. Slide

12 Sequential Machine Implementation Only for Mealy machine Inputs n Present state Next-state logic Next-state excitation signals State register l Output logic Outputs m Figure.5 Hardware realization of Moore and Mealy sequential machines. Jan. Computer Architecture, Background and Motivation Slide

13 4.3 The State Machine Cycle Cycle Cycle 3 Cycle 4 Cycle 5 es for State 5: % for j or jal, for syscall, don t-care for other instr for j, jal, and syscall, forjr jr, for branches # for j, jr, jal, and syscall, ALUZero ( ) for beq (bne), bit 3 of ALUout for bltz For jal, RegDst =, RegInSrc =, RegWrite = State Inst Data = MemRead = IRWrite = ALUSrcX = ALUSrcY = PCSrc = 3 PCWrite = State t ALUSrcX = ALUSrcY = 3 Jump Branch lw sw State 5 ALUSrcX = ALUSrcY = ALUFunc = JumpAddr = % PCSrc PCWrite = # sw State 6 Inst Data = Me mwrite = State t State t 3 ALUSrcX = ALUSrcY = lw Inst Data = MemRead = Branches based on instruction State t 4 RegDst = RegInSrc = RegWrite = Start Speculative calculation of branch address e for State 7: ALUFunc is determined based on the op and fn fields ALUtype State 7 ALUSrcX = ALUSrcY = or ALUFunc = Varies State 8 RegDst = or RegInSrc = RegWrite = Fig The control state machine for multicycle cle MicroMIPS. Feb. Slide 3

14 State and Instruction Decoding st 4 st Deco oder St St St St3 St4 St5 St6 St7 St8 op fn 6 6 RtypeInst bltzinst jinst 8 3 jalinst 4 beqinst 5 bneinst 8 addiinst andiinst op Decoder sltiinst andiinst oriinst xoriinst luiinst lwinst fn Decoder jrinst syscallinst addinst subinst andinst orinst xorinst norinst sltinst 43 swinst Fig. 4.5 State and instruction decoders for multicycle MicroMIPS. Feb. Slide 4

15 Signal Settings Table 3.3 Instruction ti op fn Load upper immediate Add Subtract Set less than Add immediate Set less than immediate AND OR XOR NOR AND immediate OR immediate XOR immediate Load word Store word Jump Jump register Branch on less than Branch on equal Branch on not equal Jump and link System call Re egwrite Re egdst Re eginsrc AL LUSrc Ad dd Sub gicfn Lo Fn nclass Da ataread Da atawrite Type Br PC CSrc Feb. Slide 5

16 Signal Generation Certain control signals depend only on the control state ALUSrcX = St St5 St7 RegWrite = St4 St8 Auxiliary signals identifying instruction classes addsubinst = addinst subinst addiinst logicinst = andinst orinst xorinst norinst andiinst oriinst xoriinst Logic expressions for ALU control signals Add Sub = St5 (St7 subinst) FnClass = St7 addsubinst logicinst FnClass = St7 (logicinst sltinst sltiinst) LogicFn = St7 (xorinst xoriinst norinst) LogicFn = St7 o (orinst oriinst norinst) Feb. Slide 6

17 4.4 Performance of the Multicycle Design R-type Load Store Branch Jump 44% 4 cycles 4% 5 cycles % 4 cycles 8% 3 cycles % 3 cycles ALU-type Load P C P C Contribution to CPI R-type.44 4 =.76 Load.4 5 =. Store. 4 =.48 Branch.8 3 =.54 Jump. 3 =.6 Average CPI 4.4 Store Branch (and jr) Jump (except jr & jal) P C P C P C Fig. 3.6 The MicroMIPS data path unfolded (by depicting the register write step as a separate block) so as to better visualize the critical-path latencies. Feb. Slide 7

18 4.5 Microprogramming PC control Cache control Register control ALU inputs ALU function Sequence control bits JumpAddr PCSrc PCWrite Inst Data MemRead MemWrite IRWrite 3 Fig. 4.6 Possible -bit microinstruction format for MicroMIPS. RegDst RegWrite FnType LogicFn Add Sub ALUSrcY ALUSrcX RegInSrc Microinstruction Cycle Cycle Cycle 3 Cycle 4 Cycle 5 es for State 5: % for j or jal, for syscall, don t-care for other instr for j, jal, and syscall, for jr, for branches # for j, jr, jal, and syscall, ALUZero ( )forbeq (bne), bit 3 of ALUout for bltz For jal, RegDst =, RegInSrc =, RegWrite = State Inst Data = MemRead = IRWrite = ALUSrcX = ALUSrcY = PCSrc = 3 PCWrite = State ALUSrcX = ALUSrcY = 3 Jump Branch lw sw State 5 ALUSrcX = ALUSrcY = ALUFunc = JumpAddr = % PCSrc PCWrite = # State ALUSrcX = ALUSrcY = sw lw State 6 Inst Data = MemWrite = State 3 Inst Data = MemRead = State 4 RegDst = RegInSrc = RegWrite = The control state machine resembles a program (microprogram) Start e for State 7: ALUFunc is determined based on the op and fn fields ALUtype State 7 ALUSrcX = ALUSrcY = or ALUFunc = Varies State 8 RegDst = or RegInSrc = RegWrite = Feb. Slide 8

19 The State Machine as a Microprogram Cycle Cycle Cycle 3 Cycle 4 Cycle 5 Multiple substates es for State 5: % for j or jal, for syscall, don t-care for other instr for j, jal, and syscall, forjr jr, for branches # for j, jr, jal, and syscall, ALUZero ( ) for beq (bne), bit 3 of ALUout for bltz For jal, RegDst =, RegInSrc =, RegWrite = State Inst Data = MemRead = IRWrite = ALUSrcX = ALUSrcY = PCSrc = 3 PCWrite = State t ALUSrcX = ALUSrcY = 3 Jump Branch lw sw State 5 ALUSrcX = ALUSrcY = ALUFunc = JumpAddr = % PCSrc PCWrite = # sw State 6 Inst Data = Me mwrite = State t State t 3 ALUSrcX = ALUSrcY = lw Inst Data = MemRead = State t 4 RegDst = RegInSrc = RegWrite = Start State 7 State 8 e for State 7: ALUFunc is determined based on the op and fn fields ALUtype ALUSrcX = ALUSrcY = or ALUFunc = Varies Multiple substates RegDst = or RegInSrc = RegWrite = Decompose into substates Fig The control state machine for multicycle cle MicroMIPS. Feb. Slide 9

20 Symbolic Names for Microinstruction Field Values Table 4.3 Microinstruction field values and their symbolic names. The default value for each unspecified field is the all s bit pattern. Field name PC control Cache control Register control ALU inputs* ALU function* Seq. control Possible field values and their symbolic names x x x PCjump PCsyscall PCjreg PCbranch PCnext CacheFetch CacheStore CacheLoad rt Data rt z rd z $3 PC PC 4 PC 4imm x y x imm x xx xx xx x x + < x x xxx lui PCdisp PCdisp PCfetch (imm) * The operator symbol stands for any of the ALU functions defined above (except for lui ). Feb. Slide

21 Unit for Microprogrammingi 64 entries in each table Multiway branch fetch: andi: Dispatch table Dispatch table 3 MicroPC Incr Address Microprogram memory or PLA Data op (from instruction register) Microinstruction register signals to data path Fig. 4.7 Microprogrammed control unit for MicroMIPS. Sequence control Feb. Slide

22 Microprogram for MicroMIPS 37 microinstructions Fig. 4.8 The complete MicroMIPS microprogram. fetch: PCnext, CacheFetch # State (start) PC + 4imm, PCdisp # State lui: lui(imm) # State 7lui rt z, PCfetch # State 8lui add: x + y # State 7add rd z, PCfetch # State 8add sub: x - y # State 7sub rd z, PCfetch # State 8sub slt: x - y # State 7slt rd z, PCfetch # State 8slt addi: x + imm # State 7addi rt z, PCfetch # State 8addi slti: x - imm # State 7slti rt z, PCfetch # State 8slti and: x y # State 7and rd z, PCfetch # State 8and or: x y # State 7or rd z, PCfetch # State 8or xor: x y # State 7xor rd z, PCfetch # State 8xor nor: x y # State 7nor rd z, PCfetch # State 8nor andi: x imm # State 7andi rt z, PCfetch # State 8andi ori: x imm # State 7ori rt z, PCfetch # State 8ori xori: x imm # State 7xori rt z, PCfetch # State 8xori lwsw: x + imm, mpcdisp # State lw: CacheLoad # State 3 rt Data, PCfetch # State 4 sw: CacheStore, PCfetch # State 6 j: PCjump, PCfetch # State 5j jr: PCjreg, PCfetch # State 5jr branch: PCbranch, PCfetch # State 5branch jal: PCjump, $3 PC, PCfetch # State 5jal syscall:pcsyscall, PCfetch # State 5syscall Feb. Slide

23 4.6 Exception Handling Exceptions and interrupts alter the normal program flow Examples of exceptions (things that t can go wrong): ALU operation leads to overflow (incorrect result is obtained) Opcode field holds a pattern not representing a legal operation Cache error-code checker deems an accessed word invalid Sensor signals a hazardous condition (e.g., overheating) Exception handler is an OS program that takes care of the problem Derives correct result of overflowing computation, if possible Invalid operation may be a software-implemented instruction Interrupts are similar, but usually have external causes (e.g., IO) Feb. Slide 3

24 Exception States Cycle Cycle Cycle 3 Cycle 4 Cycle 5 State Inst Data = MemRead = IRWrite = ALUSrcX = ALUSrcY = PCSrc = 3 PCWrite = State ALUSrcX = ALUSrcY = 3 Jump Branch lw sw State 5 ALUSrcX = ALUSrcY = ALUFunc = JumpAddr = % PCSrc PCWrite = # State ALUSrcX = ALUSrcY = sw lw State 6 Inst Data = Me mwrite = State 3 Inst Data = MemRead = State 4 RegDst = RegInSrc = RegWrite = Start State 7 State 8 ALU- type ALUSrcX = ALUSrcY = or ALUFunc = Varies RegDst = or RegInSrc = RegWrite = Illegal operation State IntCause = CauseWrite = ALUSrcX ALUSrcY = ALUFunc = EPCWrite JumpAddr = PCSrc = PCWrite = Overflow State 9 IntCause = CauseWrite = ALUSrcX ALUSrcY = ALUFunc = EPCWrite JumpAddr = PCSrc = PCWrite = Fig. 4. Exception states 9 and added to the control state machine. Feb. Slide 4

Array vs. Linked list Slowly changing size, order More often dynamically y( (rarely statically)

Array vs. Linked list Slowly changing size, order More often dynamically y( (rarely statically) Array vs. Linked list Quickly changing size, order Slowly changing size, order More often dynamically y( (rarely statically) Could be allocated dynamically or statically Could be contiguous (when static)