Array vs. Linked list Slowly changing size, order More often dynamically y( (rarely statically)

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1 Array vs. Linked list Quickly changing size, order Slowly changing size, order More often dynamically y( (rarely statically) Could be allocated dynamically or statically Could be contiguous (when static) but most Contiguous location in memory often not Fast traversal no memory overhead but fixed structure Slower traversal additional memory for storing pointers but flexible structure Example of array C code Example of array MIPS pseudocode.data a:.word int a[]; main:.text void main () { addi $sp, $sp, *4; int b[]; add $t, $sp, $ ($t is base of array b) int size; **** int *p; add $a, $, $t ($t has value of size) **** jal malloc (malloc returning p = (int *)malloc(sizeof(int)*size); memory address to $v) **** **** free(p); add $a, $t, $ ($t has value of **** memory address of p) } add $a, $v, $ jal free **** addi $sp, $sp, +*4; malloc and jr $ra free are a OS Is returning pointer to array b from main() a good idea? procedures

2 Example of linked list C code Struct mylist { int value; struct mylist *next; struct mylist *prev; } In principle i can do this (can be allocated in any type of memory): struct mylist *list[]; Most typically: void main(){ struct mylist *p p, *cur; ***** p = malloc(sizeof(struct mylist)*); add(cur, p); ***** } delete(cur); ***** Linked list example Example of linked list MIPS pseudocode main: **** addi $v, $, 2 jal malloc (malloc returning memory address to $v) add $a, $, $t ($t has address cur) add $a, $, $v jal addelement **** jal delete add $a, $, $t jal free **** jr $ra static dynamic stack

3 Deleting from doubly linked list example I (from quiz ECE5B 2)

4 Deleting from doubly linked list example II

5 Before proceeding to datapath and control let s first review some fundamental concepts from digital logic Critical Path Delay

6 Sequential Elements Register: stores data in a circuit Uses a clock signal to determine when to update the stored value Edge triggered: update when Clk changes from to D Clk Q Clk D Q Chapter 4 The Processor 6

7 Sequential Elements Register with write control Only updates on clock edge when write control input is Used when stored value is required later Write Clk Clk D Q Write D Q Chapter 4 The Processor 7

8 Clocking Methodology Combinational logic transforms data during clock cycles Between clock edges Input from state elements, output to state element Longest delay determines clock period Chapter 4 The Processor 8

Register File and SRAM Write data Write address k h

C Q D Q FF C Q D Q FF C Q k k k Muxes Read data k k

Read addr Read addr Read data Read data Read enable k k

Push Full Read address Read address h h (a) Register

Output Pop (c) FIFO symbol k State element might have

9 Register file with random access and FIFO SRAM memory

9 Register File and SRAM Write data Write address k h Write enable Deco oder 2 h k-bit registers k k k D Q FF C Q D Q FF C Q D Q FF C Q k k k Muxes Read data k k Read data k h h h Write enable Write data Write addr Read addr Read addr Read data Read data Read enable k k (b) Graphic symbol for register file k D FF C Q Q k Push Full Read address Read address h h (a) Register file with random access Read enable k Input Empty Output Pop (c) FIFO symbol k State element might have write enable signal! Figure 2.9 Register file with random access and FIFO SRAM memory is simply a large, single-port register Jan. 2file Computer Architecture, Background and Motivation Slide 9

10 Single Cycle Datapath General Assumptions One instruction executed per one cycle State elements are updated only at the end of cycle Control and data signals (afterthey they become stable) does not change during cycle Two addition operations during cycle = two physical p g y p y adders (however still want to share resources among instructions as much as possible e.g. by using muxes)

11 Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle time Determined by CPU hardware We will examine two MIPS implementations A simplified version A more realistic pipelined version Simples subset, shows s mostaspects Memory reference: lw, sw Arithmeticlogical: add, sub, and, or, slt Control o transfer: beq, j 4. Intro oduction Note that datapath from P&H (which is simpler) is discussed in details in class while datapath from BP is given as a reference Chapter 4 The Processor

12 Instruction Execution PC instruction memory, fetch instruction Register numbers register file, read registers Depending on instruction class Use ALU to calculate Arithmetic result Memory address for loadstore Branch target address Access data memory for loadstore PC target address or PC + 4 Chapter 4 The Processor 2

13 CPU Overview Chapter 4 The Processor 3 Where are the state elements? Why three adders and two memories (caches), i.e. no sharing for single data path?

14 Multiplexers Can t just join wires together Use multiplexers Chapter 4 The Processor 4

15 Chapter 4 The Processor 5 Control

16 Instruction Fetch 32 bit register Increment by 4 for next instruction Chapter 4 The Processor 6

17 R Format Instructions Read two register operands Perform arithmeticlogical operation Write register result Chapter 4 The Processor 7

18 LoadStore Instructions Read register operands Calculate address using 6 bit offset Use ALU, but sign extend offset Load: Read memory and update register Store: Write register value to memory Chapter 4 The Processor 8

19 Branch Instructions Read register operands Compare operands Use ALU, subtract t and check kzero output t Calculate target address Sign extend displacement Shift left 2 places (word displacement) Add to PC + 4 Already calculated by instruction fetch Chapter 4 The Processor 9

20 Branch Instructions Just re routes wires Chapter 4 The Processor 2 Sign bit wire replicated

21 Composing the Elements First cut data path does an instruction in one clock cycle Each datapath element can only do one function at a time Hence, we need separate instruction and data memories Use multiplexers where alternate data sources are used for different instructions Chapter 4 The Processor 2

22 R TypeLoadStore Datapath Chapter 4 The Processor 22

23 Chapter 4 The Processor 23 Full Datapath

24 ALU used for ALU Control LoadStore: F = add Branch: F = subtract R type: F depends on funct field ALU control Function AND OR add subtract set-on-less-than NOR 4.4 A Sim mple Implem mentation Scheme Chapter 4 The Processor 24

25 ALU Control Assume 2 bit ALUOp derived fromopcode opcode Combinational logic derives ALU control opcode ALUOp Operation funct ALU function ALU control lw load word XXXXXX add sw store word XXXXXX add beq branch equal XXXXXX subtract R-type add add subtract subtract AND AND OR OR set-on-less-than set-on-less-than Chapter 4 The Processor 25 Why separate decoding (i.e. ALUOp and funct fields)?

26 The Main Control Unit Control signals derived from instruction R type Load Store Branch rs rt rd shamt funct 3:26 25:2 2:6 5: :6 5: 35 or 43 rs rt address 3:26 25:2 2:6 5: 4 rs rt address 3:26 25:2 2:6 5: opcode always read read, except for load write for R type and load sign extend and add Chapter 4 The Processor 26

27 Datapath With Control Chapter 4 The Processor 27 Why fixed position for read registers in opcode?

28 Chapter 4 The Processor 28 R Type Instruction

29 Chapter 4 The Processor 29 Load Instruction

30 Branch on Equal Instruction Chapter 4 The Processor 3

31 Implementing Jumps Jump 2 address 3:26 25: Jump uses word address Update PC with concatenation of Top 4 bits of old PC 26 bit jump address Need an extra control signal decoded from opcode Chapter 4 The Processor 3

32 Datapath With Jumps Added Chapter 4 The Processor 32

33 Performance Issues Longest delay determines clock period Critical path: load instruction Instruction memory register file ALU data memory register file Not feasible to vary period for different instructions Violates design principle Making the common case fast We will improve performance by pp pipelining Chapter 4 The Processor 33

34 Example of more complex datapath from BP

35 3. A Small Set of Instructions op rs rt R 6 bits 5 bits 5 bits 5 bits I J Opcode Source Source 2 or base or dest n rd sh 5 bits fn 6 bits Destination Unused Opcode ext jta Jump target address, 26 bits inst Instruction, 32 bits imm Operand Offset, 6 bits Fig. 3. MicroMIPS MIPS instruction i formats and naming of the various fields. We will refer to this diagram later Seven R-format ALU instructions (add, sub, slt, and, or, xor, nor) Six I-format ALU instructions (lui, addi, slti, andi, ori, xori) Two I-format memory access instructions (lw, sw) Three I-format conditional branch instructions (bltz, beq, bne) Four unconditional jump instructions ti (j, jr, jal, syscall) Feb. 2 Computer Architecture, Data Path and Control Slide 35

36 The MicroMIPS Instruction Set Arithmetic Copy Instruction Usage Load upper immediate lui rt,imm Add add rd,rs,rt Subtract sub rd,rs,rt Set less than slt rd,rs,rt Add immediate addi rt,rs,imm Set less than immediate slti rd,rs,imm AND and rd,rs,rt OR or rd,rs,rt XOR xor rd,rs,rt NOR nor rd,rs,rt AND immediate andi rt,rs,imm OR immediate ori rt,rs,imm XOR immediate xori rt,rs,imm Load word lw rt,imm(rs) Store word sw rt,imm(rs) Jump j L Jump register jr rs Branch less than bltz rs,l Branch equal beq rs,rt,l Branch not equal bne rs,rt,l op 5 8 Logic Memory access Control transfer Tbl Table 3 3. Jump and link jal L System call syscall fn Feb. 2 Computer Architecture, Data Path and Control Slide 36

37 3.2 The Instruction Execution Unit PC syscall Next addr Instr cache inst beq,bne jta j,jal bltz,jr op rs rt rd sh fn R 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits I J rs,rt,rd (rs) Reg file (rt) Opcode Source or base 2 AL, lui, lw,sw ALU Source 2 or dest n Destination Unused Opcode ext imm Operand Offset, 6 bits jta Jump target address, 26 bits inst Instruction, 32 bits Address Data 22 instructions Data cache imm op fn Control Harvard architecture Fig. 3.2 Abstract view of the instruction execution unit for MicroMIPS. For naming of instruction ti fields, see Fig. 3.. Feb. 2 Computer Architecture, Data Path and Control Slide 37

38 3.3 A Single Cycle Data Path Incr PC Next PC PC Next addr (PC) Instr cache inst jta rd 3 imm rs (rs) rt 2 Reg file 6 (rt) 32 SE ALUOvfl Ovfl ALU Func ALU out Data addr Data in Data cache Register writeback Data out 2 op fn Register input Br&Jump RegDst RegWrite ALUSrc DataRead RegInSrc ALUFunc DataWrite Instruction fetch Reg access decode ALU operation Data access Fig Key elements of the single-cycle cle MicroMIPS data path. Feb. 2 Computer Architecture, Data Path and Control Slide 38

39 Constant amount Variable amount x y 5 Const Var 5 Amount 5 32 Shift function 2 Shifter No shift Logical left Logical right Arith right 5 LSBs Shifted y 32 Add Sub c Adder imm x y c k c 3 32 Logic unit 2 Logic function or MSB 32- input NOR Function class lui Shift Set less Arithmetic Logic s x y An ALU for MicroMIPS Shorthand symbol for ALU We use only 5 control signals (no shifts) Control 5 Func ALU Ovfl Zero Fig..9 9 A multifunction ALU with 8 control signals (2 for function class, arithmetic, 3 shift, 2 logic) specifying the operation. Feb. 2 AND OR XOR NOR Zero Ovfl Computer Architecture, Data Path and Control s Slide 39

40 3.4 Branching and Jumping Update options for PC (PC) 3:2 + (PC) 3:2 ++imm (PC) 3:28 jta (rs) 3:2 SysCallAddr Default option When instruction is branch and condition is met When instruction is j or jal When the instruction is jr Start address of an operating system routine IncrPC 3 NextPC Lowest 2 bits of PC always Adder c in 4 MSBs SysCallAddr MSBs BT BrTrue 3 6 SE imm Branch condition checker 3 MSBs (rt) (rs) (PC) jta 3:2 PCSrc BrType Fig. 3.4 Next-address logic for MicroMIPS (see top part of Fig. 3.3). 3) Feb. 2 Computer Architecture, Data Path and Control Slide 4

41 3.5 Deriving the Control Signals Table 3.2 Control signals for the single-cycle MicroMIPS implementation. ALU Reg file Data cache Next addr Control signal 2 3 RegWrite Don t write Write RegDst, RegDst rt rd $3 RegInSrc, RegInSrc Data out ALUo out IncrPC ALUSrc (rt ) imm Add Sub Add Subtract LogicFn, LogicFn AND OR XOR NOR FnClass, FnClass lui Set less Arithmetic Logic DataRead Don t read Read DataWrite Don t write Write BrType, BrType No branch beq bne bltz PCSrc, PCSrc IncrPC jta (rs) SysCallAddr Feb. 2 Computer Architecture, Data Path and Control Slide 4

42 Incr PC Next PC PC Single Cycle Data Path, Repeated for Reference Next addr (PC) Instr cache inst jta rd 3 imm rs (rs) rt 2 Reg file 6 Outcome of an executed instruction: A new value loaded into PC Possible new value in a reg or memory loc (rt) 32 SE ALUOvfl Ovfl ALU Func ALU out Data addr Data in Data cache Register writeback Data out 2 op fn Register input Br&Jump RegDst RegWrite ALUSrc DataRead RegInSrc ALUFunc DataWrite Instruction fetch Reg access decode ALU operation Data access Fig Key elements of the single-cycle cle MicroMIPS data path. Feb. 2 Computer Architecture, Data Path and Control Slide 42

43 Control Signal Settings Table 3.3 Instruction ti op fn Load upper immediate Add Subtract Set less than Add immediate Set less than immediate AND OR XOR NOR AND immediate OR immediate XOR immediate Load word Store word Jump Jump register Branch on less than Branch on equal Branch on not equal Jump and link System call Re egwrite Re egdst Re eginsrc AL LUSrc Ad dd Sub gicfn Lo Fn nclass Da ataread Da atawrite Type Br PC CSrc Feb. 2 Computer Architecture, Data Path and Control Slide 43

44 Control Signals in the Single Cycle Data Path Incr PC Next PC Next addr jta ALUOvfl PC (PC) Instr cache inst lui slt rd 3 imm rs (rs) rt 2 Reg file 6 (rt) 32 SE Ovfl ALU Func ALU out Data addr Data in Data cache Data out 2 Br&Jump PCSrc BrType op fn RegDst RegWrite x xx xx Register input ALUSrc DataRead RegInSrc ALUFunc DataWrite Add Sub LogicFn FnClass Fig Key elements of the single-cycle cle MicroMIPS data path. Feb. 2 Computer Architecture, Data Path and Control Slide 44

45 Instruction Decoding op fn 6 RtypeInst 6 bltzins t 2 jinst 3 jalinst 4 beqinst 5 bneinst 8 2 jrinst syscallinst 8 addiinst op Deco oder sltiinst andiinst oriinst xoriinst luiinst lwinst fn Dec coder addinst subinst andinst orinst xorins t norinst sltinst 43 swinst Fig. 3.5 Instruction decoder for MicroMIPS built of two 6-to decoders. Feb. 2 Computer Architecture, Data Path and Control Slide 45

46 Control Signal Instruction ti op f Settings: Repeated for Reference Table OR fn Load upper immediate Add Subtract Set less than Add immediate Set less than immediate AND OR XOR NOR AND immediate OR immediate XOR immediate Load word Store word Jump Jump register Branch on less than Branch on equal Branch on not equal Jump and link System call Re egwrite Re egdst Re eginsrc AL LUSrc Ad dd Sub gicfn Lo Fn nclass Da ataread Da atawrite Type Br PC CSrc Feb. 2 Computer Architecture, Data Path and Control Slide 46

47 Control Signal Generation Auxiliary signals identifying instruction classes arithinst = addinst subinst sltinst addiinst sltiinst logicinst = andinst orinst xorinst norinst andiinst oriinst xoriinst imminst = luiinst addiinst sltiinst andiinst oriinst xoriinst Example logic expressions for control signals RegWrite = luiinst arithinst logicinst lwinst jalinst ALUSrc = imminst lwinst swinst Add Sub = subinst sltinst sltiinst DataRead = lwinst PCSrc =jinst jalinst syscallinst... Control addinst subinst jinst... sltinst Feb. 2 Computer Architecture, Data Path and Control Slide 47

48 Putting It All Together Fig..9 Fig. 3.4 IncrPC 3 NextPC 3 PCSrc Adder c in 4 MSBs SysCallAddr 3 BrTrue MSBs SE imm Branch condition checker BrType 3 MSBs (rt) (rs) (PC) 3:2 jta Constant amount Variable amount x y 5 5 Const Var Amount 5 32 Shift function 2 Shifter No shift Logical left Logical right Arith right imm 5 LSBs Shifted y 32 Add Sub c Adder 32 c k c 3 32 x y 32 Function class or MSB lui Shift Set less Arithmetic Logic s x Shorth symb for AL Cont Fun A Incr PC Next PC PC Next addr (PC) Instr cache inst op fn jta rd 3 imm rs rt 2 Reg file 6 (rs) (rt) 32 SE Fig. 3.3 ALUOvfl Ovfl ALU Func ALU out Data addr Data in Register input Data cache Data out AND OR XOR NOR 2 Logic unit 2 Logic function input NOR Zero Ovfl Control y addinst subinst jinst... O Zero sltinst B&J Br&Jump RegDst RegWrite ALUSrc ALUFunc DataRead RegInSrc DtWit DataWrite Feb. 2 Computer Architecture, Data Path and Control Slide 48

49 3.6 Performance of the Single Cycle Design An example combinational-logic data path to compute z := (u + v)(w x) y u v w x y AddSub Multiply Divide Total latency latency latency latency 2 ns 6 ns 5 ns 23 ns + Note that the divider gets its correct inputs after 9 ns, but this won t cause a problem if we allow enough total time z Beginning with inputs u, v, w, x, and y stored in registers, the entire computation can be completed in 25 ns, allowing ns each for register readout and write Feb. 2 Computer Architecture, Data Path and Control Slide 49

50 Performance Estimation for Single Cycle MicroMIPS Instruction access 2 ns Register read ns ALU operation 2 ns Data cache access 2 ns Register write ns Total 8 ns Single-cycle clock = 25 MHz ALU-type Load Store P C P C P C Not used Not used R-type 44% 6 ns Load 24% 8ns Store 2% 7 ns Branch 8% 5 ns Jump 2% 3 ns Weighted mean 6.36 ns Branch (and jr) Jump (except jr & jal) P C P C Not used Not used Not used Not used Not used Not used Not used Fig. 3.6 The MicroMIPS data path unfolded (by depicting the register write step as a separate block) so as to better visualize the critical-path latencies. Feb. 2 Computer Architecture, Data Path and Control Slide 5

51 How Good is Our Single Cycle Design? Clock rate of 25 MHz not impressive Instruction access 2 ns Register read ns How does this compare with ALU operation 2ns current processors on the market? Data cache access 2 ns Register write ns Not bad, where latency is concerned Total 8 ns Single-cycle clock = 25 MHz A 2.5 GHz processor with 2 or so pipeline stages has a latency of about.4 nscycle 2 cycles = 8 ns Throughput, however, is much better for the pipelined pp processor: Up to 2 times better with single issue Perhaps up to times better with multiple issue Feb. 2 Computer Architecture, Data Path and Control Slide 5

Unpipelined Multicycle Datapath Implementation

Unpipelined Multicycle Datapath Implementation Adapted from instructor s supplementary material from Computer Organization and Design, 4 th Edition, Patterson & Hennessy, 8, MK] and Computer Architecture: