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1 6\VWHPRQD&KLS $&DVHIRU+HWHURJHQHRXV $UFKLWHFWXUHV Jan M. Rabaey BWRC University of Berkeley bwrc.eecs.berkeley.eduedu With contributions from Richard Newton and many others

2 Design at a Crossroad Silicon technology tracking Moore s Law Silicon in 2010 Die Area: 2.5x2.5 cm Voltage: V Technology: 0.07 µm Density Access Time (Gbits /c m2) (ns ) DRAM DRAM (Logic) times times denser power 5 times than density clock todayrate SRAM (Cache) Density Max. Ave. Power Clock Rate (Mgates/cm2) (W/cm2) (GHz) Custom Std. Cell Gate Array Single-Mask GA FPGA

3 Design at a Crossroad Applications beat Moore s Law Algorithmic Complexity Log Complexity 3G Cellular generations Moore s Law as applied to processors in Si. (factor 2 every 18 months) 2G 1G Time Source: R. Subramanian, Mophics Tech. Inc

4 Productivity Trans./Staff - Month Design at a Crossroad Design at a Crossroad The Productivity Gap 10,000,000 1,000, ,000 10,000 1,000 Logic Transistors per Chip (K) Logic Transistors/Chip Transistor/Staff Month 100,000,000 10,000,000 1,000, ,000 10,000 1, Source: SEMATECH µ.35µ 2.5µ x x x x x x x

5 Design at a crossroad System-on-a-Chip Multi- Spectral Imager RAM 500 k Gates FPGA + 1 Gbit DRAM Preprocessing 64 SIMD Processor Array + SRAM Image Conditioning 100 GOPS Analog µc system +2 Gbit DRAM Recognition Embedded applications where cost, performance, and energy are the real issues! DSP and control intensive Mixed-mode Combines programmable and application-specific modules Software plays crucial role

6 The Distributed Approach to Information Processing

7 The Changing Metrics Power and/or Energy have become dominant drivers Limiting factor for performance and reliability in wall-plugged applications Enabler for wide-spread use of distributed computing and data access Energy reduction requires joint optimization process between application and implementation

8 The Changing Metrics Cost of fabrication facilities and mask making has increased significantly NRE cost of new design has increased significantly Physical effects (parasitics( parasitics,, reliability issues, power management) are increasingly significant in the design process These must now be considered explicitly at the circuit level Design complexity, and context complexity is sufficiently high that design verification is a major limitation on time-to-market

9 The Changing Metrics Power Cost Flexibility Performance as a Functionality Constraint ( Just-in-Time Computing )

10 The System-on-a-Chip Nightmare Femme se coiffant Pablo Ruiz Picasso 1940

11 The System-on-a-Chip Nightmare DMA CPU DSP System Bus Mem Ctrl. Bridge MPEG The Board-on-a-Chip Approach C I O O Custom Interfaces Control Wires Peripheral Bus

12 System-on-a-Chip A Renaissance in Design Design Methodology Hard+Soft Convergence Applications Multimedia Consumer Communications Aart De Geus DAC 99 Implementation Fabrics Silicon substrate Silicon fabrics

13 An Architectural Renaissance Tensilica Synthesized and Configurable µprocessor (Soft IP) Embedded ARM-8 Microprocessor (Hard IP) Courtesy of ARM, Tensilica Inc

14 An Architectural Renaissance Very-Short Instruction Word Processors Crossbar Switch Memory (512 Mbits / 64 MBytes) C 8 Vector Pipes (+ 1 spare) I P O U Memory (512 Mbits / 64 MBytes) 0.13 µm CMOS 1 GHz 16 GFLOPS 64 GOPS (projected) V-IRAM: An integrated Vector Processor for Media Processing [Patterson et all]

15 An Architectural Renaissance MCU Core Memory DSP Core WCDMA CDMA IS-136 GSM DRA Processor Software programmable Hardware reconfigurable Software Download WCDMA CDMA WTDMA TDMA (mode, param) (mode, param) (mode, param) (mode, param) SIM Card Handset Memory POS Programming Network Download OTA Download Fixed logic Realizes cost, size and power targets similar to traditional core+hardwired MorphICs Dynamically Reconfigurable Architecture (DRA) Processor

16 An Architectural Renaissance Combines Trimedia VLIW with Configurable media co-processors Philips Nexperia NX-2700 A programmable HDTV media processor

17 Architectural Choices Flexibility Prog Mem µp Prog Mem µp Prog Mem µp Satellite Processor MAC Unit Addr Gen General Purpose µp Dedicated Logic Satellite Satellite Processor Processor Hardware Reconfigurable Processor Software Programmable DSP Direct Mapped Hardware 1/Efficiency

18 The Energy-Flexibility Gap Energy Efficiency MOPS/mW (or MIPS/mW) Dedicated HW Reconfigurable Processor/Logic ASIPs DSPs Embedded Processors Pleiades MOPS/mW 2 V DSP: 3 MOPS/mW Flexibility (Coverage) SA MIPS/mW

19 An Architectural Renaissance DMA DMA CPU CPU DSP DSP MPEG Open Core Protocol TM Mem Ctrl. Bridge MPEG C C MEM I I O O O SiliconBackplane Agent TM Communications-based Design Example: The Silicon Backplane (Sonics, Inc) Guaranteed Bandwidth Arbitration

20 Programming the Platform Algorithm Software Implementation Compilation Application What is the Programmer s Model? Architecture Microarchitecture Component Assembly and Synthesis Estimation and Evaluation Primary focus of SIA GSRC Design and Test Focus Center

21 Fast Design Space Exploration Architect Designer s Input: Architectural Choices... Architecture Parameters Application (Generic C code) Profiler Parameterized Architecture Model Retargetable Estimator... Output: Estimate, Profile Example: Retargetable estimation [Ghazal]

22 A Case Study The Integrated CMOS Radio

23 Trends in Wireless Systems Towards better spectrum utilization using aggressive signal and protocol processing Examples: multi-user detection, multi-antenna arrays adaptive, multi-functional networks Example: IMTS2000 / UMTS (3G) Towards ubiquitous wireless networking Example: Bluetooth, HomeRF, FireFly Resulting requirements high performance, low-energy, adaptivity and flexibility

24 Issues in Single-Chip Radio Design &RQWURO UI Call Setup Slot Allocation Synchronization Data Acquisition Data Encoding Radio Data Formatting Mod/ Demod Application Network Mac/ Data Link Physical + RF 'DWD source data sec streams msec packets µsec bits nsec Data and Time Granularity

25 The Software Radio A/D Converter D/A Converter DSP Idea: Digitize (wideband( wideband) ) signal at antenna and use signal processing to extract desired signal Leverages of advances in technology, circuit design, and signal processing Software solution enables flexibility and adaptivity, but at huge price in power and cost 16 bit A/D converter at 2.2 GHz dissipates 1 to 10 W

26 The Mostly Digital Radio Analog Digital cos[2π(2ghz)t] RF input (f c = 2GHz) I (50MS/s) A/D RF filter chip boundary LNA A/D Q (50MS/s) Digital Baseband Receiver sin[2π(2ghz)t]

27 The Software-Definable Radio????????????? uc core (ARM) Logic Accelerators (bit level) phone Java book VM Keypad, Display A D Timing recovery Equalizers Control MUD ARQ Multi-model Analog RF analog digital Filters Adaptive Antenna Algorithms DSP core

28 A Trend Towards GP DSPs? LAN (phy) Fixed Function 10K HDD (read) MegaMacs 1K 100 VDSL Cable modem ADSL G-lite VON, VB Modems, HDD (servo), Wireless baseband General Purpose DSP Time Source: TI

29 Single-Chip DSPs are Lagging Megamacs Moore s law: x 1.58/year DSPs DSP Trend: x 1.4/year Year While algorithms are beating Moore s law! Source: TI

30 And Computation Seems Almost for Free a+jb a b a b c d d c c+jd p_r p_i p_r + jp_i 12 x 12 Complex Multiplier 0.25 µm m CMOS process Area: 0.18 mm 2 Perf: : 25 1V Energy: 40 MCMACs/mW

31 Energy Trends in DSPs v 5v mw/mips v 3v 5v v Year 2v DSP 1v DSP v DSP DSP Power Gene s Law Factor 1.6 reduction per year Source: TI

32 The Implementation Trade-off Adaptive Pilot Correlator... Adaptive Pilot Correlator 300 million multiplications/sec 357 million add-sub s/sec Data In Acquisition and Timing Recovery Channel C 0 Coefficient Estimates C L-1 Signal Update Block Digital Baseband Receiver S k Adaptive Data Correlator Data Out

33 Adaptive Multi-User Detection A Direct Mapping Approach Correlator Power and area are dominated by MACs and multiplies Only 36% of power of DSP-processor solution going into arithmetic

34 Reconfigurable Computing: Merging Efficiency and Versatility Spatially programmed connection of processing elements. Hardware customized to specifics of problem. Direct map of problem specific dataflow, control. Circuits adapted as problem requirements change.

35 A New Look at Architectures Heterogeneous Reconfiguration Reconfigurable Logic Reconfigurable Datapaths Reconfigurable Arithmetic In Reconfigurable Control CLB CLB CLB CLB mux reg0 reg1 adder buffer AddrGen Memory AddrGen Memory MAC Data Memory Datapath Data Memory Program Memory Inst ruction Decoder & Controller Bit-Level Operations e.g. encoding Dedicated data paths e.g. Filters, AGU Arithmetic kernels e.g. Convolution RTOS Process management

36 Multi-granularity Reconfigurable Architecture: The Berkeley Pleiades Architecture Configuration Bus Satellite Processor Arithmetic Processor Arithmetic Processor Communication Network Arithmetic Processor Configuration Dedicated Arithmetic Control Processor Configurable Datapath Configurable Logic Network Interface Computational kernels are spawned to satellite processors Control processor supports RTOS and reconfiguration Order(s) of magnitude energy-reduction over traditional programmable architectures

37 Matching Computation and Architecture AddressGen AddressGen Convolution Memory MAC Memory MAC L G C Control Processor Two models of computation: communicating processes + data-flow Two architectural models: sequential control+ data-driven

38 Example: Covariance Matrix Computation for (i=1; i<=l ength; i ++) { for (k=i; k<=length; k++) { phi[i][k] = phi[i-1][k-1] + in[np-i]*in[np-k] - in[na-1-i]*in[na-1-k]; } } AddrGen Mem:in MPY ALU AddrGen Mem:phi ALU

39 Reconfigurable Kernels for W-CDMA Dominant kernel M(M T X) ) requires array of MACs and segmented memories Additional operations such as sqrt(x), 1/x, and Trellis decoding may be implemented using FPGA or cordic satellite

40 Data-driven Synchronization Based on Finite Streams Smart satellites able to handle data inputs of different types Support of multi-dimensional signal processing Introduction of data types: scalars, vectors, matrices 1 1 MP Y 1 1 n MP Y n n n MAC 1

41 Impact of Architectural Choice Impact of Architectural Choice Example: 16 point Complex Radix-2 FFT (Final Stage) Energy/stage u 10u 1u 21u Delay/stage 10u 3.8u StrongARM TMS320C2xx TMS320LC54x StrongARM TMS320C2xx TMS320LC54x Normalized Energy / stage [nj] Normalized Delay/stage [s] 100n 1000 Energy*Delay/stage n 0.75 TMS320C2xx TMS320LC54x Normalized Energy*Delay / stage [Js*e-14] Pleiades Pleiades StrongARM Pleiades

42 Adaptive Multi-User Detector for W-CDMA Pilot Correlator Unit Using LMS AG AG AG MEM MEM MEM MEM MEM MEM alt alt alt alt alt alt s_r s_i y_r y_i MAC MAC MUL MUL MUL MUL Filter SUB ADD ACC ACC Zmf_r Zmf_i ADD ADD Coefficient Update SUB SUB SUB ADD MUL MUL MUL MUL SUB SUB y_r y_i MUL MUL s_r Zmf_r s_i Zmf_i

43 Architecture Comparison LMS Correlator at 1.67 MSymbols Data Rate Complexity: 300 Mmult/sec and 357 Macc/sec 16 Mmacs/mW! Note: TMS implementation requires 36 parallel processors to meet data rate - validity questionable

44 Maia: : Reconfigurable Baseband Processor for Wireless 0.25um tech: 4.5mm x 6mm 1.2 Million transistors 40 MHz at 1V 1 mw VCELP voice coder Hardware 1 ARM-8 8 SRAMs & 8 AGPs 2 MACs 2 ALUs 2 In-Ports and 2 Out-Ports 14x8 FPGA

45 Fast Design Space Exploration Interconnect Models Model: Interconnect energy and delay model Algorithm mapping Graph-based place and route Mesh Module Hierarchical Mesh Multi-Bus N Inputs cluster cluster B Buses M Outputs cluster

46 Design Methodology and Flow Requires architecture exploration over heterogeneous implementation fabrics Should support refinement and co- design of hardware and software, as well as behavior and architecture Should consider all important metrics, and present PDA (Power-Delay-Area) perspective

47 Software Methodology Flow Algo rithms C++ Kernel Detection Behavioral Es timation/explo ration SUIF+ C-IF Power & Timing Estimation of Vario us Kerne l Imple mentations Partitioning Software Compilation Re c onfig. Hardware Mapping Inte rfac e Code Gen e ratio n µproc & Accelerator PDA Mo de ls Premapped Kernels C++ Module Librarie s

48 Hardware-Software Exploration Macromodel call

49 Implementation Fabrics for Protocols RACH req RACH akn A protocol = Extended FSM RACH idle Memory slotset read write update idle R_ENA W_ENA Slot_Set_Tbl 2x16 BUF BUF addr slot_set <31:0> Slot_no <5:0> Slot start Pkt end Intercom TDMA MAC

50 Intercom TDMA MAC Implementation alternatives ASIC FPGA ARM8 Power 0.26mW 2.1mW 114mW Energy 10.2pJ/op 81.4pJ/op n*457pj/op ASIC: 1V, 0.25 µm m CMOS process FPGA: 1.5 V 0.25 µm m CMOS low-energy FPGA ARM8: 1 V 25 MHz processor; n = 13,000 Ratio: >> 400

51 The Software-Defined Radio FPGA Embedded up Dedicated FSM Dedicated DSP Reconfigurable DataPath

52 Summary and Perspective Technology scaling is redefining the term complexity System-on-a-Chip fosters renaissance in processor architecture, opening the door for new models and combinations thereof: Component and Communication Based Design SOC driven by new set of metrics: how to simultaneously optimize flexibility, cost, energy, and performance? Reconfigurable architectures provide tantalizing combination of flexibility and efficiency Numerous solutions for addressing the data-intensive component of the software-defined radio the next challenge is control