Quelle: IABG. SEmulator. Turbocharging the FPGA Development Process

Transcription

1 Quelle: IABG SEmulator Turbochargig the FPGA Developmet Process

2 Our Compay Softwarepark Hageberg Gleichma Electroic Research (Austria) was fouded i October 2004 i Hageberg (Upper Austria). Part of the Germa based MSC group with more tha employees. GE-Research grew out of GADE (Gleichma ASIC Developmet cetre Europe) i Muich. Workig i cooperatio with the Uiversity of Applied Sciece i Hageberg, GE-Research develops FPGA ad ASIC desig tools as well as System O Chip (SOC) solutios. FH Hageberg Hpe board Resultig from this partership we ow have the FPGA Hardware Prototypig Emulatio boards Hpe ad the Hardware Accelerator ad Cosimulator HAC ad together we will cotiue to develop ad support these tools. GE- Research is also lookig for other Uiversities to joi this developmet scheme ad become a idustrial parter o differet research projects. The results of these projects are the itroduced ito the GE-Research offerigs: 8051, PCI express ad LEON solutios are just a few such collaboratios. These iovatios assist our customers to move forward with the latest iovatios, offerig our customers a cost effective price/performace ratio. Together with the desig cetre i Echig, we have more tha 10 specialists, with may years of product developmet ad ASIC desig experiece. Also we have formed parterships with may compaies, who have special kow how o complex ad future orietated solutio, which we ca offer to you. Buildig Echig 2

3 Itroductio With the SEmulator, Gleichma Electroics Research itroduces a ew method of FPGA/ASIC desig, which promise shorter developmet times ad higher desig security at a lower cost. With complex processor systems, complete iterface structures ad desig, ad up to 3 millio ASIC gates per chip, FPGAs domiate the semicoductor market with their flexibility ad recofigurable architecture. Time pressures o the egieer with a short desig cycle do ot allow for failures. Every revisio costs time ad moey, so the fuctios ad resposiveess of the fiished semicoductors have to be right the first time after silico sythesis. Today s FPGAs are developed i two steps: HDL-fuctioal blocks are simulated, idividually at first, the as a whole. The FPGA desig is sythesized ad tested i a rapid prototypig system. SEmulatio, simulator-cotrolled emulatio, combies these two steps ad allows the step-by-step trasfer of the fuctioal blocks from the simulator (software) ito the FPGA (hardware), without leavig the simulatio eviromet ad thus shorteig the developmet time. Curretly, the simulatio ad emulatio eviromets are separate ad ot always compatible, which results i wasted egieerig time gettig simulated code to ru i the emulator eviromet. Usig the SEmulator, mistakes ad isecurities are elimiated as simulatio takes place i the target hardware. The SEmulator also allows the egieer to itroduce ay exteral compoet ito the simulatio (also kow as hardware i the loop ). For the developer, this meas fuctioal first silico, with a reductio of developmet costs, as well as a icreased resposiveess to market requiremets. Figure 1 shows the cost ad complexity beefits of SEmulatio. Complexity SEmulatio HighEd Hardware- Accelerator Rapid Prototypig System Figure 1. Commercial Positio of SEmulatio Cost SEmulator Bridgig the Gap Betwee Simulatio ad Emulatio The SEmulator, amed for a made-up word that combies the words simulator ad emulator, provides bridgig fuctioality betwee the domai of digital hardware simulatio ad the world of FPGA prototypig. Desig blocks ca easily be moved betwee these two domais. 3

4 Nowadays digital hardware is described usig hardware descriptio laguages (HDL) like VHDL or Verilog. These descriptios are simulated together with a problem-specific test bech (also writte i a HDL). The iitial fuctioal verificatio of this desig is doe via simulatio. This approach is a must for the complex desigs that are developed today. However, the real goal for the hardware desiger is ot the simulatio; it is ruig the desig o real hardware. The step from simulatio to the real hardware prototype is a huge oe ad should ot be uderestimated. Whe the simulatio results are satisfactory, the desiger takes the whole desig ad dowloads the sythesized etlist ito his FPGA prototypig board. The the desiger eeds a logic aalyzer ad plety of time to locate ad fix ay bugs i his desig. The SEmulator approach eables the desiger to use the prototypig FPGA board at a early state of the desig flow. The SEmulator allows desig blocks to be moved ito the FPGA ad to co-simulate them with the actual developed desig blocks i the HDL simulator. Figure 2 shows the SEmulator priciple. The HDL simulator is used for fuctioal verificatio of the desig files; wheever a desig file is stable, it ca be trasferred to the FPGA prototypig system. The trasferred block will be co-simulated with the remaiig blocks i the simulator. The desiger ca easily switch betwee a simulatio with the HDL desig descriptio ad the co-simulatio with the real hardware located o the FPGA prototypig system. This approach allows the use of a real hardware platform i a very early desig stage without much effort. Figure 2. SEmulator Desig Flow 4

5 Whe all desig blocks are hadled by the HDL simulator, it is called simulatio. Whe the whole desig is trasferred to the FPGA prototypig board, it ca be executed at full clock speed ad is called emulatio. Mixig these two modes (havig some blocks sythesized o the FPGA ad others as simulatio models i the simulator) is called SEmulatio. Figure 3 shows the most importat parts of the SEmulator hardware platform. The motherboard (Hpe_midi, marked i red) icludes the most commo useful peripherals like memories, I/O iterfaces, ad the huma iterface. This is where the FPGA module boards (device uder test (DUT) boards) are iserted. Figure 3 shows a 2-FPGA DUT board (i blue). The clock factory allows the selectio of a required umber of clock sources for the DUT clock iputs. The Altera USB-Blaster dowload cable ca be used to cofigure the DUT devices. The child-board coector is used to exted the system with applicatio specific hardware blocks such as DDR2. Figure 3. SEmulatio Hardware Structure The high-speed iterface is achieved by a special child board ad is coected to the board via oe of the child-board coectors. The high-speed iterface (gree) commuicates with the PC via a PCI Express (PCIe) iterface board. It allows the PC software (HDL simulator + Hpe_desk) to commuicate with a I/O maager placed i oe or more of the DUT FPGAs. This system makes the desig blocks i the DUT FPGAs observable ad cotrollable, while the high-speed coectio has a positive impact o the simulatio performace. 5

6 Use Cases for SEmulatio The flexible SEmulator approach provides a wide rage of differet applicatios to accelerate the developmet process ad to ehace the desig quality. The followig poits illustrate some possibilities. A Versatile FPGA Prototypig Eviromet The hardware prototypig ad emulatio (Hpe) family provides a modular FPGA board cocept that is well suited for complex high-speed desigs. The Hpe_midi is a expadable modular FPGA prototypig platform. The base board has a broad rage of the most popular iterfaces, icludig USB 2.0, Etheret 10/100/1000, RS232, LIN, ad CAN 2B. The board also provides additioal memory such as Flash, SRAM, EEPROM ad a SD-Card coectio. A basic huma iterface cosists of a 12-key matrix keyboard, several LEDs, ad a LCD display coector. For advaced user iterface tasks, a VGA iterface, a PS2 iput coector, ad a AC97 soud chip ca be used. Startig with this base board, a FPGA module ca be selected with oe, two or eve four Altera Stratix II FPGAs (Stratix III FPGA modules will be provided oce silico is available). Missig iterfaces or hardware devices are easily added via the high-speed child-board coectors. Oe childboard coector ca hold a DDR2 memory board for huge memory requiremets. Use Real Hardware Early i the Desig Flow The beefit to usig real hardware early i the desig flow is that the desiger ca move his desig blocks step by step to the FPGA board. Usig smaller steps makes debuggig easier. Usig the simulatio test beches is also a big time saver for the desiger, as there is o eed for differet test eviromets for the simulatio ad for the FPGA prototypig board. Movig a desig block to the FPGA prototypig board is ot a oe-way road. Whe a bug is foud i a sythesized descriptio, it ca easily be switched to the simulatio model of that block. After the bug is fixed, the block ca the be trasferred back to the hardware. Check Differet Versios of a Desig Block The DUT FPGA ca hold differet versios of a desig block i parallel, ad the desiger ca easily switch betwee differet versios for debuggig purposes. Co-Simulatio With Real Hardware (Hardware i the Loop) The SEmulator system allows co-simulatio of real hardware blocks (e.g., Etheret, display cotrollers) with a existig HDL simulatio. This approach allows for the itegratio of real hardware earlier i the desig cycle. Aother beefit of usig hardware i the loop is to co-simulate with hardware blocks, where o simulatio model is available. It is possible to co-simulate a ewly developed peripheral block with a existig CPU (without a simulatio model) by puttig the CPU o a child board ad co-simulatig it with the ewly developed compoet. 6

7 Simulatio Acceleratio Simulatig huge desigs with a HDL simulator is a tedious task. Whe the desiger trasfers parts of the desig to the FPGA prototypig board ad co-simulates them with the HDL simulatio, the simulatio ru times ca be decreased. Small desigs will ot beefit, because the commuicatio overhead is higher tha the gaied simulatio performace, but real world desigs will speed up quite impressively. Figure 4 shows the eormous impact ad achievable reductios o the overall simulatio time. The HAC2 techology is itegrated ito the SEmulator system, so similar results are achieved with the ew system. If a stadard simulatio rus 10 hours, this is the required time with HAC 2 10 hours stadard simulatio time without HAC 27 mi 16 mi 4 mi 12 mi CPU09x16, HAC2 Acceleratio, speedup 21,9 32bit CPU LEON3, HAC2 Acceleratio, speedup 37 32bit CPU LEON3, HAC2 with Clock Acceleratio, speedup 137 SQRT, HAC2 Acceleratio, speedup 48 1 mi 43 mi Madelbrot, HAC2 Acceleratio, speedup 14 Madelbrot, HAC2 with Clock Acceleratio, speedup 566 Figure 4. HAC2 Bechmarks I the LEON3 example above, ruig the HDL simulatio takes 10 hours. By placig this desig ito the FPGA ad ruig it with clock accelerated simulatio, the HDL test bech is still i the HDL simulator but this time it rus 37 times faster ad oly takes 16 miutes to complete. The clock acceleratio techology allows the desig to be ru at full speed (up to 100 MHz) for selected time periods, ad ca be exploited for the LEON3 desig to reduce the simulatio time to 4 miutes, a acceleratio of 137 times. Faster simulatios allow: Faster desig iteratios Ad/or the simulatio of more test cases 7

8 The Hpe_desk Software The Hpe_desk provides a ituitive ad powerful scriptable graphical iterface for the SEmulator fuctioality. Figure 5 shows the mai software blocks (Hpe_desk ad the HDL simulator) ad the way the desig files are processed. Figure 5. Hpe_desk ad FPGA Board The Hpe_desk software cosists of the followig mai compoets: VHDL/Verilog parser Hierarchy browser Altera Quartus developmet software iterface Clock factory Logic aalyzer JTAG board test iterface The software is available for Widows ad GNU/Liux systems. This allows the use of SEmulatio i your preferred workig eviromet. 8

9 VHDL/Verilog Parser The VHDL/Verilog parser takes the desig descriptios ad extracts the desig hierarchy ad other relevat data for SEmulatio. The result is stored i the desig database. Hierarchy Browser The hierarchy browser allows the desiger to select desig blocks that should be executed o the FPGA. The required iformatio about the desigs is stored i the desig database. A screeshot is show i Figure 6. Figure 6. Hierarchy Browser The hierarchy browser displays the desig hierarchy i a tree view. This view ca be used as comfortable avigatio tool to edit the HDL desig source files. It ca be used to locate the followig desig compoets: VHDL Etity/Architecture or Verilog Module defiitios The source locatio of istatitated blocks VHDL sigal or process defiitios Differet desig cofiguratios ca be stored as bookmarks. This feature allows to switch easily betwee various simulatios that iclude for example a differet set of blocks that should be executed o the FPGA. 9

10 Altera Quartus Iterface The Altera Quartus icremetal sythesis flow ca be used to shift selected desig blocks to the FPGA board quickly. The, the geerated cofiguratio bitstreams ca be dowloaded to the FPGA prototypig board. The Altera Quartus Iterface provides a powerful cache maagemet to avoid time cosumig re-sythesis steps wheever possible. This is a importat property whe a comparisio betwee differet cofiguratios is eeded. I such scearios it is ecessary to switch ofte betwee differet implemetatios (holdig differet blocks i hardware). The sythesis cache allows to perform this task quickly. Clock Factory The clock factory is a easy-to-use iterface to select the required clocks for the Emulatio mode, as show i Figure 7. Figure 7. Clock Factory The SEmulator system provides differet operatio modes: The Cosimulatio mode: The clocks are geerated by the cotrollig HDL simulator. The system frequecies i this mode are up to 200 khz. The Emulatio mode: The emulated system rus at full speed (up to 100 MHz). The clocks are provided by the clock factory CPLD o the FPGA module board. The clock factory software iterface allows to program the clock factory CPLD for this mode. The combied mode: Some parts of the system ru at full speed. The clocks are provided by the clock factory CPLD. Other parts are cotrolled by the simulator. 10

11 JTAG Board Test Iterface With access to the JTAG-chai o the boards, the desiger ca use this stadard protocol for debuggig purposes. Figure 8 shows the JTAG GUI for a small test desig. Addig a powerful coectio tester allows it to be used for board tests. The JTAG iterface is fully scriptable. This allows to create reusable tests that ca be used to test a small umber of devices i-house. Figure 8. JTAG Tool Widow The JTAG tool is tightly itegrated with the Desig Database ad the Altera Quartus Iterface. This allows to use the sigal ames from the used HDL desig i the JTAG view. The JTAG tool ca also be used to access a JTAG chai that is implemeted i a custom desig ad placed o a DUT FPGA. 11

12 Logic Aalyzer A high-speed logic aalyzer (available i 2008) is a useful debuggig aid that will help to locate bugs without the eed to use a exteral logic aalyzer. The logic aalyzer commuicates via the PCIe X4 iterface with the PC. SEmulator Sythesis Flow Details Oce the desiger selects the blocks to be placed o the FPGA prototypig board, the Altera Quartus iterface sythesizes the blocks. The resultig desig etlist ad a predefied I/O maager etlist are combied to create a top-level etlist. The I/O maager is eeded to observe ad cotrol the desig, as well as provide a commuicatio iterface to the PC software. The Quartus iterface exports the board specific bitstreams ad the eeded board-specific data for the co-simulator extesio. This sythesis flow is show i Figure 9. Figure 9. SEmulator Sythesis Flow Normally, a etire desig hierarchy is placed o a FPGA, as it is ot possible to exclude oe or more sub-blocks. The SEmulator desig flow allows the exclusio of sub-blocks from the sythesis ad keeps them as simulatio models. This feature allows for very fast co-simulatio of a desig block, sice the large hardware block is located o the FPGA ad oly small desig blocks are simulated by the HDL simulator. Ruig the Co-Simulatio Figure 10 shows a screeshot from a ruig Metor Graphics ModelSim simulatio coected to the FPGA prototypig board. 12

13 Figure 10. vsim-hac Sapshot After the desig block is sythesized ad the simulator loads a test bech that istatiates this desig block, the bitstream is automatically trasferred to the DUT FPGAs. At this poit the simulatio ca be started. All top-level sigals of the sythesized block ad some selected iteral sigals ca be displayed i the stadard waveform widow. Hardware for SEmulatio To combie simulatio ad emulatio, the fuctioality of a hardware accelerator is ecessary. I 1999, Gleichma Research developed a hardware accelerator ad co-simulator, based o a previous product, the HAC2. The HAC2 was a efficiet ad easy-to-hadle product, but there was a major challege with the data exchage, icludig protocol, speed, ad the method of data acquisitio. The HAC2 is a PCI card, expadable via a 10-Gbit proprietary iterface. The hadicap of such a system is the additioal cost for hardware ad the iheret difficulties of adaptig such a system to a applicatio. As the hardware accelerator was developed, Gleichma developed ad produced FPGA rapid prototypig boards i parallel, usig the advacemets leart from the HAC2. These Hpe boards are already well accepted i the market, based o the stregth of the umerous o-board iterfaces ad the ability to adapt to high-speed applicatios. Hudreds of these systems are already used i uiversities ad labs worldwide. The goal i 2006 was to combie these two systems. Customer discussios ad requests revealed the followig major targets: No additioal hardware cost No differet cofiguratios betwee simulatio ad emulatio Fast switch betwee simulatio ad emulatio, with o additioal sythesis of etlist Easy hadlig Additioal debug tools o the same user iterface Stadard iterfacig to PC Competitive pricig The Hpe_midi ca solve all of these requests. 13

14 Hpe_midi The Most Flexible Rapid Prototypig System To combie simulatio ad emulatio, the fuctioality of a hardware accelerator is ecessary. I The Hpe_midi (Figure 11) is the ext step up from the Hpe_compact, a FPGA prototypig system, which has bee available sice The compoets cosist of a motherboard, may user iterfaces, ad a removable FPGA module. Available today are 1- ad 2-FPGA modules with the 4- ad 8-FPGA modules curretly uder developmet. Figure 11. Hpe_midi Frot View (left) ad Ope/Rear View (right) All Hpe_midis are delivered i a eclosure. This protects the board agaist mechaical ad evirometal damage. But wheever ecessary, the system ca be used safely with the cover removed. This follows Gleichma s philosophy of decreasig the umber of hidde bugs, allowig the desiger to cocetrate o the real job of developmet. Fuctioal Descriptio The Hpe_midi base board (show i Figure 12) cotais the followig features: O-Board System Fuctios Power supply 5V/11A ad 3.3V/6A Reset geeratio Complex clock factory Hpe_coector for FPGA module 2 Hpe_child coectors for extesios Altera Sata Cruz coector PS/2 coector for mouse ad keyboard SD card slot O-Board Memory FLASH 8M * 32 SRAM 256K * 32 2-Kbyte EEPROM Huma Iterface 3 * 4-butto field 2-digit 7-segmet display 8 LEDs Reset butto Sigle-step key (debouced) Coector for LCD display Others Prototypig area 2 quartz sockets (clock factory) Exteral clock iput (clock factory) D/A coverter A/D coverter 14

15 Figure 12. Hpe_midi Block Diagram As a example, Figure 13 shows a block diagram of the 2-FPGA module. Gleichma will ot accept limitatios o maximum speed, so all systems provide the highest possible speed, givig customers all the fuctioality that the FPGA techology offers: All FPGAs are protectable with the Altera AES ecryptio. A programmable clock factory o the module provides more flexibility. A temperature-regulated fa for every FPGA guaratees highest security/reliability. Two Hpe_child boards o the module, plus two Hpe_child boards o the mai board allow the adaptatio of early every applicatio. A high umber of coectios betwee the FPGAs guaratee easy sythesis. Figure 13. Hpe_module 2X Block Diagram 15

16 VIII-4_2007-DSR-3132 GE Coclusio This paper has discussed how both simulatio ad desig emulatio ca be combied ito a sigle developmet eviromet to deliver shorter verificatio times ad therefore shorter developmet times ad reduced developmet costs. The SEmulator board is curretly available at a very competitive price/performace ratio. The oly additioal compoet ecessary is a Hpe_child board for PCIe exteral coectors, such as a PCIe X4 iterface. This ca coect up to four FPGAs to the PC by a card i the PCIe graphic slot (X16), ad guaratees sufficiet badwidth for the required data throughput. This paper is writte by Dieter Scheurer, Gleichma Electroics Research Dr. Stefa Reichör, Gleichma Electroics Research ad modified by Altera Corporatio. Thaks for this. Altera Corporatio gave us the permissio to prit this paper. Sales Offices Berli Tel.: Berli@msc-ge.com Hamburg Tel.: Hamburg@msc-ge.com Haover Tel.: Haover@msc-ge.com Jea Tel.: Jea@msc-ge.com Nuremberg Tel.: Nuerberg@msc-ge.com Wiesbade Tel.: Wiesbade@msc-ge.com MSC Budapest Kft. Tel.: Budapest@msc-ge.com MSC (Frace) S.A.R.L Tel: Paris@msc-ge.com MSC Nederlad BV Tel.: Netherlads@msc-ge.com MSC Polska Sp. z o.o. Tel.: Gliwice@msc-ge.com MSC Schweiz AG Tel.: Hagedor@msc-ge.com Tel.: E-Mai: Biel@msc-ge.com MSC (Scotlad) LTD. Tel.: Livigsto@msc-ge.com MSC-Vertriebs-CZ s.r.o. Tel.: Kromeriz@msc-ge.com Tel.: Praha@msc-ge.com MSC Vertriebs GmbH Sales Office Austria Tel.: Wie@msc-ge.com MSC Vertriebs GmbH Turkey Liasio Office Tel.: Turkey@msc-ge.com MSC (UK) LTD. Tel.: Brighto@msc-ge.com Headquarters Frakethal Tel.: Frakethal@msc-ge.com Düsseldorf Tel.: Duesseldorf@msc-ge.com Muich Tel.: GE.Mueche@msc-ge.com Stutesee Tel.: Stutesee@msc-ge.com Stuttgart Phoe Stuttgart@msc-ge.com Gleichma Electr. UK Ltd. Milto Keyes Tel.: Miltokeyes@msc-ge.com SDC Systems Limited Herts Tel.: + 44 (0) sales(at)sdcsystems.com HiTech Global Desig & Distributio, LLC Sa Jose, U.S.A Tel.: ifo(at)hitechglobal.com Detailed iformatio o this product is available uder GE Research Phoe: Mail: sales@ge-research.com GE. All rights reserved. Although great care has bee take i preparig this prited matter, GE caot be held resposible for ay errors or omissios. All iformatio i here is subject to chage without otice. All other products ad brad ames are registered trademarks of their respective compaies.