CMOS Digital Integrated Circuits

Transcription

1 CMOS Digital Integrated Circuits Chapter 1 Introduction S.M. Kang and Y. Leblebici 1 CMOS Digital Integrated Circuits 3 rd Edition Copyright The McGraw-Hill Companies, Inc. Permission required for reproduction or display.

2 Some History Invention of the transistor (BJT) 1947 Shockley, Bardeen, Brattain Bell Labs Single-transistor integrated circuit 1958 Jack Kilby Texas Instruments Invention of CMOS logic gates 1963 Wanlass & Sah Fairchild Semiconductor First microprocessor (Intel 4004) ,300 MOS transistors, 740 khz clock frequency Very Large Scale Integration 1978 Chips with more than ~20,000 devices 2 CMOS Digital Integrated Circuits 3 rd Edition

3 More Recently Ultra Large Scale Integration System on Chip (SoC) 20 ~ 30 million transistors in 2002 The chip complexity has increased by a factor of 1000 since its first introduction, but the term VLSI remained virtually universal to denote digital integrated systems with high complexity. 3 CMOS Digital Integrated Circuits 3 rd Edition

4 Some Leading-Edge Examples 7 CMOS Digital Integrated Circuits 3 rd Edition

5 Evolution of Minimum Feature Size 9 CMOS Digital Integrated Circuits 3 rd Edition

6 Moore s Law 11 CMOS Digital Integrated Circuits 3 rd Edition

7 Evolution of Memory Capacity 12 CMOS Digital Integrated Circuits 3 rd Edition

8 Shrinking Device Dimensions YEAR TECHNOLOGY 130 nm 100 nm 70 nm 50 nm 35 nm CHIP SIZE 400 mm mm mm mm mm 2 NUMBER OF TRANSISTORS (LOGIC) DRAM CAPACITY MAXIMUM CLOCK FREQUENCY MINIMUM SUPPLY VOLTAGE MAXIMUM POWER DISSIPATION MAXIMUM NUMBER OF I/O PINS 400 M 1 Billion 3 Billion 6 Billion 16 Billion 2 Gbits 10 Gbits 25 Gbits 70 Gbits 200 Gbits 1.6 GHz 2.0 GHz 2.5 GHz 3.0 GHz 3.5 GHz 1.5 V 1.2 V 0.9 V 0.6 V 0.6 V 130 W 160 W 170 W 175 W 180 W CMOS Digital Integrated Circuits 3 rd Edition

9 Increasing Function Density YEAR TECHNOLOGY 130 nm 100 nm 70 nm 50 nm 35 nm CHIP SIZE 400 mm mm mm mm mm 2 NUMBER OF TRANSISTORS (LOGIC) 400 M 1 Billion 3 Billion 6 Billion 16 Billion DRAM CAPACITY 2 Gbits 10 Gbits 25 Gbits 70 Gbits 200 Gbits MAXIMUM CLOCK FREQUENCY MINIMUM SUPPLY VOLTAGE MAXIMUM POWER DISSIPATION MAXIMUM NUMBER OF I/O PINS 1.6 GHz 2.0 GHz 2.5 GHz 3.0 GHz 3.5 GHz 1.5 V 1.2 V 0.9 V 0.6 V 0.6 V 130 W 160 W 170 W 175 W 180 W CMOS Digital Integrated Circuits 3 rd Edition

10 Increasing Clock Frequency YEAR TECHNOLOGY 130 nm 100 nm 70 nm 50 nm 35 nm CHIP SIZE 400 mm mm mm mm mm 2 NUMBER OF TRANSISTORS (LOGIC) DRAM CAPACITY MAXIMUM CLOCK FREQUENCY MINIMUM SUPPLY VOLTAGE MAXIMUM POWER DISSIPATION MAXIMUM NUMBER OF I/O PINS 400 M 1 Billion 3 Billion 6 Billion 16 Billion 2 Gbits 10 Gbits 25 Gbits 70 Gbits 200 Gbits 1.6 GHz 2.0 GHz 2.5 GHz 3.0 GHz 3.5 GHz 1.5 V 1.2 V 0.9 V 0.6 V 0.6 V 130 W 160 W 170 W 175 W 180 W CMOS Digital Integrated Circuits 3 rd Edition

11 Decreasing Supply Voltage YEAR TECHNOLOGY 130 nm 100 nm 70 nm 50 nm 35 nm CHIP SIZE 400 mm mm mm mm mm 2 NUMBER OF TRANSISTORS (LOGIC) DRAM CAPACITY MAXIMUM CLOCK FREQUENCY MINIMUM SUPPLY VOLTAGE MAXIMUM POWER DISSIPATION MAXIMUM NUMBER OF I/O PINS 400 M 1 Billion 3 Billion 6 Billion 16 Billion 2 Gbits 10 Gbits 25 Gbits 70 Gbits 200 Gbits 1.6 GHz 2.0 GHz 2.5 GHz 3.0 GHz 3.5 GHz 1.5 V 1.2 V 0.9 V 0.6 V 0.6 V 130 W 160 W 170 W 175 W 180 W CMOS Digital Integrated Circuits 3 rd Edition

12 5-layer cross-section of chip 20 CMOS Digital Integrated Circuits 3 rd Edition

13 .. - Passlmloo Global Dlaleemric.,. diffusl'on barrier Intermediate LocaE 21 CMOS Digital Integrated Circuits 3 rd Edition

14 System-on-Chip Integrating all or most of the components of a hybrid system on a single substrate (silicon or MCM), rather than building a conventional printed circuit board. 1. More compact system realization 2. Higher speed / performance Better reliability Less expensive! 22 CMOS Digital Integrated Circuits 3 rd Edition

15 Comm µc I MPEG 2 Yideo detoder Subp cture and OSD proce!sor Scalelf -::!l c:r. c:: 0 > Q.:...:m... CSS Audio Ollllplllt Processor Audio FreqJJ@11cy Synt~i1er '"=i== c D/A A111d lo O llt?llt. S,ste~n Frequency S y11tllesi zer -3.e, 3 M emary lnm~r I :'. M a_naget"jlllllt 32-bit Unit RISC CPU.,,,. j SD RAM 23 CMOS Digital Integrated Circuits 3 rd Edition

16 New Direction: System-on-Chip (SoC) ASIC Core Memory Analog Functions Sensor Interface Communication Embedded Processor Core 24 CMOS Digital Integrated Circuits 3 rd Edition

17 The Y-Chart Notice: There is a need for structured design methodologies to handle the high level of complexity! 29 CMOS Digital Integrated Circuits 3 rd Edition

18 Simplified VLSI Design Flow Top-down Bottom-up 30 CMOS Digital Integrated Circuits 3 rd Edition

19 Top-down vs. bottom-up design Top-down design adds functional detail. - Create lower levels of abstraction from upper levels. Bottom-up design creates abstractions from low-level behavior. Good design needs both top-down and bottom-up efforts. 43

20 VLSI Design Cycle [ l I J I e t Behavioral VHDL, C 10 St ructural.. w VHDL ]... I ! ' ' X=(AB*CD)+ (A+D) Y=(A(B+q+ AC+D) 44

21 VLSI Design Cycle System Specification - A high level representation of the system - Considered factors» Performance Fabrication Technology» Functionality H De)ignTechniques» Physical dimensions (die size) - Result Specs - size, speed, power, and functionality 45

22 VLSI Design Cycle Architectural Design - RISC (Reduced Instruction Set Computer) versus CISC (Complex Instruction Set Computer) - Number of ALUs, Floating Point Units - Number and structure of pipelines - Cache size - Prediction on die size, power, and speed based on existing design - Early estimation are very important here 46

23 VLSI Design Cycle Behavioral or Functional Design - Only behavior and timing without implementation issue - Specify behavior based on Input+ output+ timing - Fast emulation and debugging for the system elk); begin if (enable_ == l 'bo) data= O; else data = dat.a + 1; end 47

24 HDL-Based Design 1980 s Hardware Description Languages (HDL) were conceived to facilitate the information exchange between design groups s The increasing computation power led to the introduction of logic synthesizers that can translate the description in HDL into a synthesized gate-level net-list of the design s Modern synthesis algorithms can optimize a digital design and explore different alternatives to identify the design that best meets the requirements. 45 CMOS Digital Integrated Circuits 3 rd Edition

25 VLSI Design Cycle Logic Design - Control flow, word widths, register allocation, arithmetic operations, and logic operations - RTL (Register Transfer Level) - HDL (Hardware Description Language)» Verilog - most popular» VHDL - Europe and Eastern» Literal + Timing Information X=(AB CD)+ (A-r D) Y= (A(B- C)-r AC+ D) Boolean Expression Timing lnfonnarion 48

26 VLSI Design Cycle Logic Design - More actual simulation and testing a---- b---- c---- d---- () 1 sa 1 sa CJ Y - High Level Synthesis: Produce a RTL description from a behavioral description of the design 49

27 VLSI Design Cycle Circuit Design - Boolean Expression - Circuit Elements (Cells, Macros, Gates, Transistors) + Interconnection - Each component has specific timing and power Info. - Circuit Simulation : Verify the correctness and timing - Terms - Netlist, Schematic - Logic Synthesis Tools : RTL -- Netlist 50

28 VLSI Design Cycle Physical Design - Netlist - Layout (Geometry Representation)» Design rules of applied fabrication process - Layout Synthesis Tools» Automatic conversion (Fully/Partially)» Area and performance penalty - Crucial Challenges - Area/Delay

29 VLSI Design Cycle Fabrication - Layout~ Photo-lithographic mask» One mask for each layer - Wafer : Silicon crystal are grown & sliced - Deposition, and diffusion of various materials on the wafer : each step uses one mask - Term : Tape Out, 8 inch/20cm, 12 inch/30cm - -, 'I J " ', '- ~ 52...,-

30 VLSI Design Cycle Packaging, Testing, and Debugging - For PCB (Printed Circuit Board) : DIP (Dual In-line Package), PGA (Pin Grid Array), BGA (Ball Grid Array), and QFP (Quad Flat Package) - For MCM (Multi-Chip Modules): no packaged - Testing» Before Package - Probe line testing» After Package - Tester machine applies test patterns. 53

31 Structured Design Principles Hierarchy: Regularity: Modularity: Locality: Divide and conquer technique involves dividing a module into submodules and then repeating this operation on the sub-modules until the complexity of the smaller parts becomes manageable. The hierarchical decomposition of a large system should result in not only simple, but also similar blocks, as much as possible. Regularity usually reduces the number of different modules that need to be designed and verified, at all levels of abstraction. The various functional blocks which make up the larger system must have well-defined functions and interfaces. Internal details remain at the local level. The concept of locality also ensures that connections are mostly between neighboring modules, avoiding long-distance connections as much as possible. 31 CMOS Digital Integrated Circuits 3 rd Edition

32 Hierarchy of a 4-bit Carry Ripple Adder 32 CMOS Digital Integrated Circuits 3 rd Edition

33 Regularity 2-input MUX DFF 37 CMOS Digital Integrated Circuits 3 rd Edition

34 VLSI Design Styles FPGA 38 CMOS Digital Integrated Circuits 3 rd Edition

35 Full Custom Design Following the partitioning, the transistor level design of the building block is generated and simulated. The example shows a 1-bit full-adder schematic and its SPICE simulation results. 39 CMOS Digital Integrated Circuits 3 rd Edition

36 Full Custom Design The main objective of full custom design is to ensure fine-grained regularity and modularity. 40 CMOS Digital Integrated Circuits 3 rd Edition

37 Full Custom Design A carefully crafted full custom block can be placed both along the X and Y axis to form an interconnected two-dimensional array. Example: Data-path cells 41 CMOS Digital Integrated Circuits 3 rd Edition

38 Full Custom SRAM Cell Design 42 CMOS Digital Integrated Circuits 3 rd Edition

39 Mapping the Design into Layout Manual full-custom design can be very challenging and time consuming, especially if the low level regularity is not well defined! 43 CMOS Digital Integrated Circuits 3 rd Edition

40 VLSI Design Styles FPGA 44 CMOS Digital Integrated Circuits 3 rd Edition

41 Standard Cells AND DFF INV XOR 47 CMOS Digital Integrated Circuits 3 rd Edition

42 Standard Cells 48 CMOS Digital Integrated Circuits 3 rd Edition

43 Standard Cells 49 CMOS Digital Integrated Circuits 3 rd Edition

44 Standard Cells Rows of standard cells with routing channels between them Memory array 50 CMOS Digital Integrated Circuits 3 rd Edition

45 Standard Cells 51 CMOS Digital Integrated Circuits 3 rd Edition

46 VLSI Design Styles FPGA 52 CMOS Digital Integrated Circuits 3 rd Edition

47 Mask Gate Array 53 CMOS Digital Integrated Circuits 3 rd Edition

48 Mask Gate Array Before customization 54 CMOS Digital Integrated Circuits 3 rd Edition

49 VLSI Design Styles FPGA 55 CMOS Digital Integrated Circuits 3 rd Edition

50 Field Programmable Gate Array 56 CMOS Digital Integrated Circuits 3 rd Edition

51 Field Programmable Gate Array Internal structure of a CLB 57 CMOS Digital Integrated Circuits 3 rd Edition

52 Field Programmable Gate Array 58 CMOS Digital Integrated Circuits 3 rd Edition

53 1.2 Objective and Organization of the Book Increasing Conl>lexily Device Eleetronlcl Two-Translstot Cin:ults (ln1111ners) Combinational and Sequential Logic Circuits.. i. Regular Structures, VLSI Sub-SystemS ROMS, RAMs, Pl.As : Adde1'8, Multipliers System-Related Issues. Relabltlty, Manufaclurablllty, Tes1al>lllty Breadth of Toplcs Fig11rt 1.4. The ordering of topics covered in a typical digital integrated circuits course.

54 'II""' Cln:uta TSPC L.ocfe Cl... P1611r, J.S. CVSL: Cascade Voltage Switch Logic NORA: NO RAce circuits TSPC: True-Single Phase Clock Clan,ficalion of CMOS digilal circuit ty~s. 25

55 1.3 A Circuit Design Example Syst om Roquir oment.s - Architecture Definition and Logic O eslgn Logic d iagr-am I description, ~ VLSI Design nd ~yout Teenno1<>gy Design A Uies Oovico Modola Fall : =~~~~-~ :~~~~:~~~~ ~~~~~-~~~~~~:.~~=~~------_] Pass Mask Genor-atlon Silicon Processing T o : Wt11fer Testing Packaging Reliability Ouoliticotion Figure 1.e The flow of c ircuit design procech. re-s. 27

56 One-bit Full-Adder Circuit Design: Using O.Bum twin-well CMOS technology with specification: 1) Propagation delay times of sum and carry-out signals <1.2ns (worst) 2) Transition delay times of sum- and carry-out signals < 1.2ns (worst) 3) Circuit area < 1500 µ m 2 4) Dynamic power dissipation (@V 00 = 5V and fmax = 20MHz) < 1mW A B c Full Adder sum_out carry_out Sum out= AEBBEBC - = ABC+ABC+ABC+ABC Carry_out =AB+ AC+ BC Sum_out =ABC+ (A+B+C)carry_out ABC sum_out carry_out

57 r --, ~ A B c carry_out ~ A B c sum - - ' Figure 1. 7 Gate-level schematic of the one-bit full-adder circlit 29

58 I c---1 f-- A A---1 e---1 f-e f--a A---1 e---l c---l f-- c f--e -:: '"m Figure 1.8 Transistor-level schematic of the one-bit fud adder circuit. 30

59 Yoo Ill,.----, a-, r e,., o-, c-, 1-c ;lll'!y. Wt I-a c---4 }-A r" Yoo c~ ~ A I-A A~ 8~ ~8 A--l a--j c--l l- 11 l\lffl Figure 1,9 Alternate transistor-level schematic of the one-bit full-adder circuit (note that the nmos and pmos networks are completely symmetric). 31

60 B c I I 1 I. '! i I. I CO P"oly in verti:::: ~~tal in horizontal. SUM Figure 1.10 Initial layout of the full-adder circuit using minimum-size transistors. Area= 21X54 um 2 = 1134 um 2 32

61 ... SPICE simulation ~~ s.zc.,:-.,.. Ai:k::lil!l,r-. (.atn:x:t~ C-,, N. :I ~ a s.a :I l I ] f ~,.... l n I ~:i... r---- ~ ~~ ~ t : I:kc:\.... n. -. ~ ~~~...::;::;::._~...::;;:::::::::::;::===:;::::::::...._.., -~ - 2 ~ iolate 1.2ns ~load Figure r.. 9. Simulated input and ou1j:)ut waveforms ot the ~adder-cirouit. I

62 - in s ut...---,/ ( INP17r CAJ\JtY -- I SVK ;~... - > ~ ]" 2. s 2 j l _,/sum_out l \ Time ( 11 ) Figure Simulated ouqx.it waveforms of the full adder circuit with minimum transistor droensions. showing the signal propagabori delay during one of the worst-case transitions. 34

63 -VDD A B c ] Area = 43X30 um 2 = 1290 um2 SUM GND c;::j OIFF. D NWELL DP+ - POLY O MET- 1 - MET-2 Figure 1.13 Modified layout of the full-adder circuit, with optimized transistor dimensions. 35

64 - > 41 'O :, u... j Worst Case Delay, Optimized Size Transiscors, EXTRACTED - UlPlIT - CARRY sum SUM o o-.oo - uo ~ (\carry \ l f : I : : - :-- ;- '- - 1 i. ' I. --t - +:,<1.23ns ' ; ; r \! ~ : _...,- '---..,...:..'.. ~../ -+- :\ ' - 'a::......_ J, 22 T.ime (ns) Figure 1.14 Simulated output wavef0<ms of the full-adder circuit with optimized transistor dimensions, showing the signal propagation delay during the same worst-case transition.. Power dissipation= 460 µ W 36

65 s, Full Adder c, (FA) Full Adder (FA) C2 Full Adder C3 C, Full Adeler (FA) (FA) Rgur Block diagram of a cany ripple aclder chain consisting of full adders. Si., s, s., s~ Figure Mask layout ol the 4 bt carry npple adder array. 37

66 &I r'1a,,,,,_,. A ll!olt) ln 1 191! J,p l'l (Ob'lI I:t 1 Im lu IP ri...,.,. = Ml(U su,.1(1) ~-:====~--... ~ ';::::==::;-' 51.11,1(~~---~ :..~;----';:::: SUU(S) ----~ rl Sl.l\lCQ ::======== ~r--, - ~:;--~J SUWl'1) ~ SlN(WSll~l----~---~"----'.. ~ 7 : C...,... el loll Mot,,, 51«. -~.ot::l = -~-[,~4.- Ho ~~l:.::::, : =9'.M(l')=:::=,...::::::::; ~, ~... ~... -.Ul.:...,!:;---,-----,... n,.---, ~...,. ~ V: ::\===:=../ H ~ll...:;;:;::;::;:;;:~'~~~~~...!::::=;:;::;::.:::;:;:...,_...:.:::.;::.:= -~...,... ::=]...,.. J = _:3 ).)..., I Flgure 1.17 Slmu1ated Input and output waveforms of the 8-bit carry ripple adder circuit. showing a maximum signal propagation delay of about 7 ns.