Tera-scale Computing and Interconnect Challenges

Transcription

1 Tera-scale Computing and Interconnect Challenges 3D Stacking Considerations Dr. Jerry Bautista Director, Microprocessor Technology Management Co-Director, Tera-scale Computing Research 2007 Intel Corporation

2 Agenda Tera-scale computing - an I/O inflection point Implications to interconnects Options 3D die/wafer stacking considerations Summary 2

3 Multi-core is now mainstream Multi-core Top to Bottom Add cores to deliver historic 2x performance/2 years 3

4 A Tera-scale Platform Vision Cache Cache Cache Special Purpose Engines Integrated IO devices Scalable On-die Interconnect Fabric Last Level Cache Last Level Cache Last Level Cache Integrated Memory Controllers Off Die interconnect High Bandwidth Memory IO Socket Inter- Connect 4

5 Multi-core for Energy-Efficient Performance P = CV 2 f Relative single-core frequency and Vcc 5

6 What is Tera-scale? Model-based Apps Recognition Mining Synthesis 3D & Video Mult- Media Text Models 6

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8 More Compute Better Experience Perceptual accuracy & graphical realism scale with compute Algorithms ideal for array of general purpose CPUs Shared algorithms i.e. ray-tracing for lighting aids physics collision detection and path selection AI Today: Second Life Fluid 1X Now Tomorrow: Particle Fluid 10X Compute Effects Physics Future: Natural Looking Fluid 1000X Compute 10+ years 8

9 Research shows Applications Scale Well 9

10 21.72mm Teraflops Research Processor 12.64mm Goals: Deliver Tera-scale performance - Single precision TFLOP at desktop power - Frequency target 5GHz - Bi-section B/W order of Terabits/s - Link bandwidth in hundreds of GB/s Prototype two key technologies - On-die interconnect fabric - 3D stacked memory Develop a scalable design methodology - Tiled design approach - Mesochronous clocking - Power-aware capability 1 TeraFLOP in < 60 W envelope 100 Million Transistors 80 Tiles 275mm 2 10

11 Agenda Tera-scale computing - an I/O inflection point Implications to interconnects Options 3D die/wafer stacking considerations Summary 11

12 Tera-scale Research Challenges 12

13 FSB and Memory Effective Bandwidth, Effective CPU core MHz Desktop Platform Bandwidth Roadmap GB/s 10 GB/s PentiumIII FSB 64 bit EDO 64 bit SDRAM Pentium4 FSB 2 ch. RDRAM 128 bit DDR 128 bit DDR2 192 bit DDR2/3 CSI Eff CPU Core Freq Mem Eff BW FSB EFF BW 2x / 21 mon 2x / 24 mon 2x / 27 mon Tera-scale Computing Requirements Staying on-trend puts mem BW target at GB/s for the time frame But Tera-scale (highly parallel) work loads are 5x that 13

14 Future CPU s Tera-Scale Performance DIMMs 100 s GB/s Bulk memory This is the problem area cost and power 10 s GB/s Bulk Storage 1 s 1 s TB/s TB/s Array of interconnected processing cores (on die power ~ 0.1 mw/gb/s) 1 s GB/s Another box, shelf or rack Tera FLOPS implies tera bytes/sec bandwidth 14

15 Agenda Tera-scale computing - an I/O inflection point Implications to interconnects Options 3D die/wafer stacking considerations Summary 15

16 Approaches to Increase BW Ex. Software opt. Add Last Lev Cache SIP/MCP 3D Stacking Pin counts challenging package limits. Speed (Power, Complexity, Si area) Si Package Socket ~10 Gb/s Mother Board Si Package Socket Power scaling is exponential with increasing speed. 16

17 Bulk Memory I/O Pins and Power Power (mw/gbps) State of the art Research Signaling Rate GBit/sec Source: Randy Mooney, Intel Pin Count Power: Total Package Pins Power Pins IO Pins Source: Ravi Mahajan, Intel SoA: 100 GB/sec ~ 1 Tb/sec = 1,000 Gb/sec 25mw/Gb/sec = 25 Watts Could be reduced significantly, but requires major changes to physical layer. Pins: Bus-width = 1,000/5 = 200, about 400 pins (differential) Too much power, too many signal pins I/O power should be < 10% of total CPU socket power 17

18 Technologies in the Memory Hierarchy SRAM and/or edram DRAM Non-volatile Memory (NAND or PCM or?) Magnetic Storage 18

19 Memory Flow Model Model: a constant size L1 & L2, and a varying size L3, and a very large L4. Method: Capture L3 accesses per instruction & Capture L4 accesses per instruction Project L3, L4 BW requirements L1 L2 L3 L4 19

20 Bandwidth Requirements Outgrow Roadmap 10TB/s Bandwidth Requirements 1TB/s 100GB/s 10GB/s 1GB/s Kernels: Matrix Operations Equation Solvers Regression Analysis Applications: Financial Analytics Physics Simulation Media Processing BW Roadmap Trends Only 25-40GB/s of BW available by Even by 2013, only ~100GB/s of BW available based on DDRx trends Terascale Workloads Insufficient Bandwidth Will Limit Performance 20 Source: Albert Lin, Intel/Stanford Yen-Kuang Chen, Intel

21 Solving BW Limitations 100% (100% = ideal performance with no BW limitations) Performance 10% 1% 0% Terascale Workloads 21 Source: Albert Lin, Intel/Stanford Yen-Kuang Chen, Intel

22 Hiding Memory/Storage Bandwidth Limitations DIMMs Under CPU: 3D stack Near CPU: MCP or C2C Tradeoffs: capacity (density) latency power/thermals Done. cost integration path SW execution (working set sizes) 22

23 On-Socket DRAM Caches For Memory Scalability Enable Large Capacity L4s - Low Latency - High Bandwidth Technologies - Multi-chip Packages (MCP) - 3D Stacking Benefits - Significant Miss Rate Reduction - Avoids bandwidth wall - At better latency Normalized miss rate Benefits of Large Caches OLTP ERP Java-1 Java Threads / Shared Cache size (MB) MCP ~200GB/s Proc DRAM $ 3D stack >1TB/s Proc DRAM $ Iyer, R, et al, Datacenter-on-Chip Architectures: Tera-scale Opportunities and Challenges, and Polka, LA et al, Package Technology to Address the Memory Bandwidth Challenge for Tera-scale, Computing, Intel Technology Journal, Volume 11, Issue 3,

24 CPU and Nearby Memory Under CPU: 3D stack Near CPU: MCP or C2C Considerations: - SW working set sizes - Power delivery - Heat dissipation - Yield/process flow - Reliability - Stacking method Chip to chip Wafer to wafer Bottom line: No Major Technical Issues Package substrate Existing DRAM devices are I/O constrained stacking attractive 24

25 Agenda Tera-scale computing - an I/O inflection point Implications to interconnects Options 3D die/wafer stacking considerations Summary 25

26 Work in Progress: Stacked Memory Prototype 256 KB SRAM per core 4X C4 bump density 3200 thru-silicon vias Polaris Package Thru-Silicon Via Denser than C4 pitch Freya C4 pitch 26

27 Current Die and Wafer Stacking Structure Comparison Die Stacking TSV Wafer Stacking Source: Intel Possible Application : Logic + Memory TSV Size: ~50 µm Thickness: ~100 µm Bonding Structure: ~Bump Size Bonding Pitch: ~Bump Pitch Source: Intel Possible Application : Logic + Logic TSV Size: <~5µm Thickness ~10 µm *Bonding Structure: <~5 µm *Bonding Pitch <~8 µm Source: Morrow et. al, Wafer-level 3D interconnects via Cu bonding, Proc. AMC, (2004) 27

28 300 mm Wafer Bonding (b) Source: Morrow et. al, Wafer-level 3D interconnects via Cu bonding, Proc. AMC, (2004) 28

29 Bond Interface Electrical Test Configuration Current Bond Pad Through-Si Via Wafer #1 Wafer #2 ~4096 links For this study: Pitch <~ 9 µm Source: Morrow et. al, Wafer-level 3D interconnects via Cu bonding, Proc. AMC, (2004) 29

30 Stacking Memory for Cache -Thermals Intel Core 2 Duo power and thermal map Source: Intel Must carefully consider thermal map for 3D stacking 30 Source: Venkat Natarajan, Intel

31 Impact of Powermap Alignment 0.5 W/Die dissipation in one quarter of die Die 2 Thermal floorplanning for die stacks is critical aspect of thermal design hot spot alignment creates greatest increase in temperature Hot Spots Die 1 Effect of Powermap On Heat Transfer from a Four-Die-Stack Temperature (C) Uniform Heat Load Aligned Powermap Case Non-Aligned Powermap Case Airflow DT max ~ 8.5 C Die Number 31 Source: Venkat Natarajan, Intel

32 Thermal Through Silicon Vias (TTSV) STACKED DIES SIGNAL LAYERS THERMAL THROUGH SILICON VIAS (TTSV) DIE-T0-DIE VIAS THROUGH SILICON VIAS (TSV) SUBSRATE May need dedicated thermal through silicon Vias Large in size: ~100 microns diameter; ~200 microns deep Filled with copper to provide adequate thermal paths 32 Source: Venkat Natarajan, Intel

33 1 CSI4CSI4 Vss CSI4 VFusCSI3 CSI3RXDAT_B0 CSI4 Vss CSI4 CSI4CSI4 CSI4Vss CSI4CSI4RXDAT_B7 CSI4CSI4RXDAT_B3 Vss VCC VSTB CSI4Vss CSI5CSI5 CSI5CSI5RXDAT_B3 Vss Misc CSI5 CSI5RXDAT_B0 POW Vss CSI5 Vss CSI5 2 CSI4CSI3 CSI3CSI3 CSI3RXDAT_B3 Vss CSI4 CSI4CSI4 CSI4Vss CSI4CSI4 CSI4RXDAT_B8 3 Vss CSI3 CSI3CSI3RXDAT_B4 Vss CSI3RXDAT_B1 CSI4CSI4 CSI4Vss CSI4CSI4 CSI4Vio Vss CSI4 CSI4CSI4RXDAT_B4 Vio Vss CSI4 CSI4RXDAT_B2 CSI4RXDAT_B0 Vio Vss CSI4Vio CSI5RXDAT_B6 Vss Vio CSI5 CSI5RXDAT_B1 Vio Vss Misc Misc Misc FBDFBD1 CSI4Vss CSI4CSI4 CSI4CSI5 Vss CSI5 CSI5RXDAT_B4 CSI5RCSI5RXDAT_B2 VssRXDAXDATRXDAXDATCVss Vio FBD1 4 CSI3CSI3 Vss Vio CSI3CSI3RXDAT_B2 CSI3Vss VFusCSI3 CSI3CSI4 Vss CSI4 CSI4CSI4RXDAT_B6 Vio Vss CSI4RXDAT_B1 Vio CSI4CSI4 Vss CSI5RXDAT_B9 CSI5CSI5RXDAT_B5 CSI5Vss CSI5RXDAT XDAT Vio VssRXDATRXDARXCLK 5 Vss CSI3RXDAT_B5 CSI3CSI3RXDAT_B6 Vio Vss CSI3Vio CSI3CSI3 Vss CSI4 CSI4CSI4RXDAT_B9 CSI4Vss CSI4CSI4RXDAT_B5 Vss CSI4 CSI4CSI5 CSI5RXDAT_B8 Vss CSI5CSI5TCSI5 CSI5Vss FBD1RXDATD1 XDATXDATC XDAT VssRXDA 6 Vcac CSI3 CSI3RXDAT_B7 Vss CSI3CSI3 CSI3CSI3 Vss Vio CSI3Vio CSI4Vss CSI4CSI4 CSI4CSI4 Vss CSI4 CSI4Vio CSI4Vss CSI5CSI5 CSI5CSI5TVss CSI5 XCLK FBD1RXDATD0 FBD1RXDATD5 VssRXDAXDATC XDAT 7 VcacVss CSI3CSI3 CSI3RXDAT_B8 Vio Vss CSI3CSI3CSI3CSI3Vss CSI4CSI4CSI4Vio Vss CSI4CSI4CSI4CSI4Vss CSI5CSI5CSI5RXDAT_B7 Vio Vss CSI5TCSI5CSI5CSI5VssXDAT FBD1RXDATD3 XDATRXDATVss 8 VR_OCSI3 CSI3RXDAT_B9 Vss CSI3 CSI3CSI3 CSI3Vss CSI3CSI3 Vio CSI4 Vss CSI4 CSI4CSI4 Vio Vss CSI4CSI4 CSI4CSI5 Vss CSI5 CSI5Misc Vio Vss Misc MiscRXCLKXCLKDVssXDATC RXDA 9 VR_OCSI3 Vss CSI3 CSI3CSI3 Vio Vss CSI3CSI3 Vio SID[0]Vss CSI4 CSI4CSI4 CSI4Vss CSI4CSI4 CSI4Vio Vss CSI5 CSI5CSI5 Misc Vss Misc Misc 1TXDAXDATVss FBD1RXDATD2 XDATRXDAT XDAT 10 Vss CSI3CSI3CSI3Vio Vss CSI3CSI3CSI3CSI3Vss SID[1]MiscMisc CSI4Vss CSI4CachCSI4OCP Vss OCP MiscMisc MiscVss MiscMisc Misc MiscVssFBD1RXDATD4 Vio XDATDVio VssRXDA 11 CSI3CSI3 CSI3Vss CSI3CSI3 CSI3Vio Vss CSI3 PBE SID[2] ERROR[1] Vss Misc Misc Misc Cach Vss OCP_OCP OCP OCP Vss Misc TCKTMS Misc Vss Misc MiscTXDA TXDATVss FBD1RXDATD6 FBD1RXDATD12 FBD1RXDATD_B12 12 CSI3Vss CSI3CSI3 CSI3Vio Vss CSI3 CSI3CSI3 CSI3Vss ERROR[0] Vio Misc Misc Vss Cach CachOCP_OCP Vss OCP OCP OCP_TDI Vss Misc Misc Misc Vio VssTXDA TXDATXDAT FBD1RXDATD7 Vss 13 CSI3Vio CSI3CSI3 Vss CSI3 CSI3CSI3 CSI3Vss PSMI Vio Looking at the top of the Mot TRST#Misc Misc Vss MiscTXDAXDATVio VssXDATDRXDA 14 CSI3CSI3 Vss CSI3 CSI3CSI3 LSS Vss CSI3Vio PROMForcePR# Misc Vss Misc Misc 1TXDAXDATVss1TXDA FBD1RXDATD8 XDATDVio 15 Vss PLL_PLL_PLL_PLL_Vss KBX_DLL_EOR_LOW KBX_BM[0BM[ Vss Heartbeat PM_RPM_RMisc Misc Vss TXCLK TXCLK TXDAT 1TXDAVss FBD1RXDATD V12V 12V12V 12V12V 12V12V 12V12V SLVDSKT_MEM_RSTB PLL_Misc Vss MiscRXDAT FBD0RXDATB_B0 Vio VssTXDAT FBD1RXDATD10 FBD1RXDATD_B V12V12V12V12V12V12V12V12V12VSLVDVss Vss RESET#MiscRXDAT FBD0RXDATB_B1 VssRXDAT 1TXDA TXDATVio Vss 18 12V12V 12V12V 12V12V 12V12V 12V12V SLVDSY SINT_FREQ[0] SysCTDOVio VssRXDAT FBD0RXDATB_B2 FBD0RXDATB_B3 1TXDAVss TXDATXDA 19 12V12V12V12V12V12V12V12V12V12VVio SY SCSI SysCVss MiscRXDAT XDATAVio VssTXDAT 1TXDAXDATVio 20 12V12V 12V12V 12V12V 12V12V 12V12V Vss SMBCEND FBD BypCMisc Misc Misc VssRXDAT FBD0RXDATB_B5 TXDATVssTXDA 21 12V12V 12V12V 12V12V 12V12V 12V12VFRCSSMBD SysInt MiscMisc Vss MiscVio FBD0RXDATB_B4 RXCLKVss1TXDAXDATXDAT 22 12V12V 12V12V 12V12V 12V12V 12V12V FRCSVss END Vss Misc Misc MiscRXDATVssXCLK FBD0RXDATB12 FBD0RXDATB_B12 TXCLVss 23 12V12V12V12V12V12V12V12V12V12VFRCSFRCFG[0] MOTMisc Misc VssXDATARXDAT XDAT Vio Vss XCLKTXDA 24 TRIGGER[0] TRIGGER[1] Vss TRIGGER[2] TRIGGER[3] GIODGIOCVss SLVDSLVDFRCSFRCFG[1] MOTVss MiscRXDAT RXDATXDATAVssRXDAT RXDATVio XDAT 25 Vss CSI2 CSI2CSI2 CSI2Vss ROM_CSI2 CSI2FRDI Vss FRCFG[2] MAI_Misc MiscXDATAVssRXDATVio FBD0RXDATB_B8 FBD0RXDATB_B7 VssTXDA 26 CSI2CSI2 CSI2Vss CSI2CSI2 CSI2CSI2 Vss CSI2 HV MTEST_SY NC MAI_CSD_VssRXDATVioXDATA RXDATVss FBD0RXDATB11 RXDATXDAT 27 Misc Vss CSI2CSI2 CSI2Vio Vss CSI2 CSI2CSI2 CSI2Vss FRC Misc Misc Misc Vss Cach CachMisc Misc Vss Misc Misc Misc Misc Vss CSD_MiscXDATA RXCLKVss FBD0RXDATB_B6 FBD0RXDATB10 FBD0RXDATB_B11 FBD0RXDATB_B9 Vss 28 Misc CSI2 CSI2CSI2 Vss CSI2 CSI2CSI2 Vio Vss CSI2PROCFRDOMisc Vss CSI1 CachCach Misc Vss Misc Misc Misc Misc Vss Misc DFDMisc Vio VssXCLKA FBD0RXDATA_B12 FBD0RXDATB_B10 VssTXDA FBD0TXDATB_B0 29 VR_FCSI2 Vss CSI2 Vio CSI2 CSI2Vss CSI2CSI2 CSI2FRWPVss Misc Vio CSI1 CSI1Vss CSI1CSI1 CSI1Vio Vss CSI0 CSI0Misc DFDVss MiscRXDAT XDATARXDATVss Vio0TXDA FBD0TXDATB_B2 Vio 30 Vss CSI2 CSI2CSI2 CSI2Vss CSI2Vio CSI2CSI2 Vss CSI2 Vio Misc Misc Vss CSI1Vio CSI1CSI1 Vss CSI1 CSI0CSI0 CSI0Vss CSI0CSI0TMisc FBD0TXDATA1 VssXDATA FBD0RXDATA_B10 Vio VssTXDA 31 VR_THERM_ Vio CSI2Vss CSI2CSI2 CSI2CSI2 Vss CSI2 Vio CSI2 CSI2Vss CSI1CSI1 CSI1CSI1 Vss CSI1 Vio CSI1 CSI0Vss CSI0CSI0 CSI0Vio VssTXDATVio RXDAT 32 THERMTRIP# Vss CSI2CSI2 CSI2CSI2RXDAT_B9 Vss CSI2CSI2 CSI1Vss CSI2Vio CSI1RXDAT_B6 Vss CSI1 CSI1CSI1 CSI1Vss CSI0Vio CSI0CSI0 Vss CSI0T XDATAVss0TXDA FBD0TXDATB_B3 FBD0TXDATB_B1 FBD0TXDATA4 FBD0TXDATA0 VssRXDAT FBD0RXDATA_B11 FBD0TXDATB_B4 Vss 33 VcoreCSI2 CSI2RXDAT_B8 Vss Vio CSI2CSI2Vio Vss CSI1CSI1 CSI1CSI1RXDAT_B8 Vss CSI1RXDAT_B3 CSI1CSI1CSI1Vss CSI1CSI1CSI1CSI0Vss CSI0VioFBD0TXDATA6 CSI0T VssTXDAT FBD0TXDATA3 Vio Vss TXCLXCLK 34 VcorCSI2 Vss CSI2 CSI2RXDAT_B7 CSI2CSI2Vss CSI1CSI1 CSI1CSI1 Vss CSI1 CSI1CSI1RXDAT_B4 Vio Vss CSI1CSI1CSI1CSI1Vss CSI0Vio CSI0CSI0VssXDAT 35 CSI2CSI2RXDAT_B6 CSI2Vio CSI2RXDAT_B3 Vss CSI2CSI2 CSI1CSI1 Vss CSI1 CSI1CSI1 CSI1Vss CSI1RXDAT_B1 CSI1CSI1 Vss CSI1 CSI0CSI0 CSI0RXDAT_B6 36 Vss CSI2 CSI2RXDAT_B5 Vss CSI2CSI2 CSI2RXDAT_B1 FBD0TXDATA2 FBD0TXDATA9 VssTXDA FBD0TXDATB_B9 Vss CSI0CSI0RCSI0RXDAT_B1 Vio VssXDATAVio FBD0TXDATB_B7 0TXDAVss FBD0TXDATB_B5 CSI1 Vss CSI1 CSI1CSI1 CSI1RXDAT_B9 Vss CSI1RXDAT_B5 Vio CSI1CSI1 Vss CSI1 CSI1Vio CSI0RXDAT_B9 Vss CSI0RXDAT_B5 CSI0RXDAT_B4 CSI0RVss FBD0TXDATA8 0TXCLXCLK FBD0TXDATA5 FBD0TXDATB_B6 Vss CPU_FBD0 37 CSI1CSI2 CSI2CSI2 CSI2RXDAT_B4 Vss CSI1 CSI1CSI1 Vio Vss CSI1CSI1 CSI1RXDAT_B7 Vss CSI1 CSI1Vio CSI1Vss CSI0RXDAT_B8 38 CSI1CSI1 Vss CSI1 Vss CSI2RXDAT_B2 CSI2CSI2RXDAT_B0 CSI0 CSI0CSI0 Vss CSI0RXDAT_B2 CSI0RXDAT_B0 Vio VssXDATXDA FBD0TXDATB_B8 FBDFBD0 Vio Vss CSI1CSI1 Misc Misc Vss CSI1RXDAT_B2 CSI1CSI1RXDAT_B0 CSI1Vss CSI1CSI1 CSI0CSI0RXDAT_B7 Vss CSI0CSI0RXDAT_B3 FBD0TXDATA7 Vss XDATAMisc Misc CSI0 Vss CSI0 Packaging BW Options Super Socket MCP Edge Stacked Stacked Interconnect Density (1 cm x 1 cm die) Very Low (~ 100) Low (~ 800) Medium (< 5K) ( 100 µm bump pitch) Wafer-wafer ~ 1 M Die-die > 5K Interconnect BW (GB/s) < 0.2 TB/s TB/s ~ 1 TB/s 1 TB/s Flexibility Low High High Medium-Low TSV (Through Si Via) Cost/BW Tradeoff will be key Qualified Prescott dual core MCP

34 Summary An I/O inflection point on the horizon - Increased consolidation of BW at the CPU socket - Parallel execution and new workloads To increase BW, architectural and packaging options are likely the first approach to enabling high BW - 3D stacking is an attractive solution for both a large last level cache and increasing bulk DRAM capacities Challenges: Socket power increased with DRAM integration Thermals Cost/yield No major technical issues Lots of opportunity for architectural innovation! 34