The Rubber Jigsaw Puzzle

Transcription

1 The Rubber Jigsaw Puzzle Floorplanning for network-on-chip (NoC) Benjamin Hong ( 홍병철 ), Brian Huang ( 黃繼樟 ) presented by Jonah Probell Arteris, Inc. September 18, 2015 SNUG Austin SNUG

2 Thanks to the Team SNUG

3 Coming up What is a NoC? Memory subsystem considerations Guidelines for macros and domains Other guidelines NoC P&R constraints Q&A Lunch SNUG

4 What s a NoC? You are all right. But you are all wrong too. For each of you touched only one part of the animal. The Blind Men And The Elephant SNUG

5 The Crossbar master Interface block Interface block slave master master master Interface block Interface block Interface block Interface block Interface block Interface block slave slave slave How many IPs does your chip have? master Interface block Interface block slave Look at all the wires! That s hard to place & route. SNUG

6 The Theoretical NoC Few floorplans are so beautifully aligned. SNUG

7 The Production NoC It s the stuff between IP macros. It must accommodate the floorplan. It s the rubber between the pieces of your jigsaw puzzle floorplan. The NoC has the longest wires. It s the last step of integration. Floorplan with care to avoid project delay. SNUG

8 Packetization reduces wire count Command Transaction interface Address Data Header Packet transport interface Data SNUG

9 Serialization reduces wire count CPU long links are narrow wide links are short DRAM interface SNUG

10 Guidelines for Memory Subsystems SNUG

11 An Hypothetical Chip CPU big CPU little GPU MMU DSP MMU ZRAM VidDec VidEnc ISP JPG GP2D PSI CSI DSI HDMI PCIe Modem MCU Crypto DMA Audio DSP USB2 USB3 Debug WiFi BT Coh 0 Coh 1 Coh NoC CBI MMU Main NoC MI 0 MI 1 LLC 0 LLC 1 Mem NoC ROB Flash emmc SATA UniPro PSI NVM SRAM Sensor WiFi BT SatNav NFC CPU0 dbg CPU1 dbg other IO sys ctrl Sched 0 Sched 1 DRAM DRAM SNUG

12 Debug Sched 0 DDR PHY 0 Sensor SatNav NFC USB 3 USB 2 WiFi MCU crypto antenna Modem JPG DMA PSI DSP NVM DSI Video encode ISP Audio CBI CSI Main ROB PMU Vreg Coh 0 HDMI MI0 MI1 SRAM PLL CPU little PCIe Coh 1 Sys ctrl interfaces CPU big UniPro emmc Flash Other I/O GPU BT GP 2D Video decode SATA last level cache slice 1 ZRAM Sched 1 DDR PHY 1 last level cache slice 0 SNUG

13 Debug Sched 0 DDR PHY 0 Sensor SatNav NFC USB 3 USB 2 WiFi MCU crypto antenna Modem JPG DMA PSI DSP NVM DSI Video encode ISP Audio CBI CSI Main ROB PMU Vreg Coh 0 HDMI MI0 MI1 SRAM PLL CPU little PCIe Coh 1 Sys ctrl interfaces CPU big UniPro emmc Flash Other I/O GPU BT GP 2D Video decode SATA last level cache slice 1 ZRAM Sched 1 DDR PHY 1 last level cache slice 0 SNUG

14 Guidelines for Macros and Domains SNUG

15 Group sockets that are in shared domains close together Domain A IP Domain B IP Domain B IP Domain A IP Group IPs and macro sockets + minimize long wires + allow P&R to localize logic Domain A IP Domain A IP Domain B IP Domain B IP SNUG

16 Group sockets that are in shared domains close together Fast IP Fast IP Fast period Slow period Slow IP Slow IP Fast switch Domain adapter Slow switch Fast IP Slow IP Put domain adapters close to fast switches to minimize pipeline stages. SNUG

17 Cross IP macro boundaries simply Top NoC IP macro NIU AMBA interface Transport link Switch This is intuitive and easy for verification SNUG

18 Cross IP macro boundaries on a specialized socket interface Macro IP Top NoC NoC Switch IP NIU IP NIU NoC-NoC protocol Transport link A macro with multiple IPs should have its own small NoC. This minimizes the P&R stretching internal connectivity. NoC Socket Protocol (NSP) is better for timing and area. It also uses fewer ports at macro boundaries. SNUG

19 Cross macro boundaries on packetized transport links IP macro Top NoC Switch NIU Where is the clock adapter and power disconnect? Generate the network interface unit of the NoC separately. Wrap it with the IP and synthesize it into the IP macro. The macro boundary crossing happens on a serialized NoC transport link, for minimal wires and ports. SNUG

20 Cross macro boundaries at async power adapters IP macro Top NoC Switch NIU NoC clock and power disconnect is at IP macro edge. This uses more macro ports, but the IP macro needs no top NoC clock and the top NoC needs no IP macro clock. Clock trees and power nets align with IP macro edges. SNUG

21 Pipeline close to macro boundaries to separate logic and wire delay IP macro Top NoC NIU Transport link Switch logic delay wire delay NIU Short wires Wide buses Many logic levels Add a pipe stage at the IP macro boundary. Use zero wire load model synthesis. P&R will not stretch wide buses. Transport link Long wires Narrow buses Little logic SNUG

22 Other guidelines SNUG

23 Leave sufficient space around a NoC macro IP macro A Synthesizing the NoC at the top level? NIU A NIU B space Leave space between IP macros for NIU logic and buffers. offset Offset ports to allow logic separation IP macro B SNUG

24 Don t worry (too much) about toplevel time budgeting BUF video codec MCTL 0 Vreg DDR PHY 0 debug PLL sensor PCIe audio USB Flash ADC MCU crypto modem eth DMA GPU MIPI DSP LCD image BT ROB Last level cache slice CPU ROB SATA Last level cache slice MCTL 1 DDR PHY 1 SNUG BUF wifi CPU Not meeting timing on a top-level path? Don t resynthesize your macros. A good thing about NoC is that pipelining is pushbutton. Pipeline during top level synthesis or ECO in pipes if necessary.

25 Leave sufficient space around a NoC macro Part of the NoC A macro offset Another part of the NoC Another macro space Using a methodology of hardening parts of NoC into macros? Leave space between macros for late-project pipe stage insertion. Count the wires in long routing channels. SNUG

26 Constrain NoC unit placement create_placement_blockage set_port_location NIU1[0] coordinate {somewhere} set_port_location NIU2[0] coordinate {elsewhere far away} create_bounds coordinate {an area 1/3 between} name NoCPipe001 \ type soft [get_cells NoCPipe001/*] create_bounds coordinate {an area 2/3 between} name NoCPipe002 \ type soft [get_cells NoCPipe002/*] SNUG

27 Samsung Exynos Octa SNUG

28 Samsung Exynos 7420 SNUG

29 Conclusion Read SNUG papers Use a NoC Distribute the memory subsystem Keep the CPUs close Partition the NoC with the chip Use NoC domain adapters to isolate macro clock and power nets Use pipelining to separate the problems of synthesized logic timing and P&R wire delay timing Constrain NoC unit placement, especially pipe stages Feel free to me: jonah@probell.com SNUG

30 Thank You SNUG