Mm-wave integrated waveguide components in silicon technology

Size: px
Start display at page:

Download "Mm-wave integrated waveguide components in silicon technology"

Transcription

1 Mm-wave integrated waveguide components in silicon technology G. Gentile, M. Spirito, L.C.N. de Vreede, et al. Electronics Research Laboratory (ELCA), Dimes, Delft University of Technology, The Netherlands Delft University of Technology Challenge the future

2 Motivation: transmission line How to distribute signal over large area (on and off chip) minimizing losses? Zhang J., Jackson, M.K.; Long, J.R.; Sadr, S., "Millimeter-wave characteristics of SiGe heterojunction bipolar transistors and monolithic interconnects in silicon technologies," ISSCC 2001 Mm-wave integrated waveguide components in silicon technology

3 Motivation: bulk waveguide Mm-wave integrated waveguide components in silicon technology

4 Motivation: mm-wave waveguide Micro-machined PCB Dedicated process C.E. Collins, et al., A new micro-machined millimeter-wave and terahertz snap-together rectangular waveguide technology, IEEE Microw. Guided Wave Lett., K. Wu, et al., The substrate Integrated Circuits a New Concept for High-Frequency Electronics and Optoelectronics PCB Manufacturing Variation Impact on High Frequency Measurement Fixtures IEEE TELSIKS M. Henry, et al., "Millimeter Wave Substrate Integrated Waveguide Antennas: Design and Fabrication Analysis," Advanced Packaging, IEEE Transactions on, Mm-wave integrated waveguide components in silicon technology

5 Outline KOH waveguide process Intrinsic waveguide Coplanar to waveguide transition Frequency scanning array: Slotted waveguide Uniform offset array Conclusions Mm-wave integrated waveguide components in silicon technology

6 KOH waveguide process Silicon filled substrate integrated waveguide (a) (c) (b) (d) Mm-wave integrated waveguide components in silicon technology

7 KOH waveguide process Continuous metal side walls Size reduction (silicon dielectric) Photo-lithographic accuracy Bi-CMOS-compatible Planar feed Mm-wave integrated waveguide components in silicon technology

8 KOH waveguide process Thick metal coverage (> 2 skin depths) Accuracy: ~1 um Minimum gap: 10 um Mm-wave integrated waveguide components in silicon technology

9 Outline KOH waveguide process Intrinsic waveguide Coplanar to waveguide transition Frequency scanning array: Slotted waveguide Uniform offset array Conclusions Mm-wave integrated waveguide components in silicon technology

10 Intrinsic waveguide: design Trapezoidal cross-section Equivalent rectangular waveguide Fundamental mode: TE 10 -like Intrinsic impedance 50 Ω Propagation constant: γ = α + j β Mm-wave integrated waveguide components in silicon technology

11 Wave number [rad/mm] Loss [db/mm] Intrinsic waveguide: gamma transition waveguide transition j S11 S 21 S22 S 21 port 1 port 2 S21 S j 22 S21 S 11 0 e e measured simulated 0.8 simulated measured Frequency [GHz] Frequency [GHz] Mm-wave integrated waveguide components in silicon technology

12 Outline KOH waveguide process Intrinsic waveguide Coplanar to waveguide transition Frequency scanning array: Slotted waveguide Uniform offset array Conclusions Mm-wave integrated waveguide components in silicon technology

13 CPW-WG transition: design Planar way to feed energy into a 3D structure Facilitates interconnection to other dies: flip-chip bondwires Mm-wave integrated waveguide components in silicon technology

14 CPW-WG transition: design Planar way to feed energy into a 3D structure Facilitates interconnection to other dies: flip-chip bondwires Mm-wave integrated waveguide components in silicon technology

15 CPW-WG transition: S-parameters De-embedding of the transition effects: - L 1 -L 2 algorithm port 1 transition S S S S waveguide 0 e j e j 0 S S transition S S port 2 Mm-wave integrated waveguide components in silicon technology

16 Outline KOH waveguide process Intrinsic waveguide Coplanar to waveguide transition Frequency scanning array: Slotted waveguide Uniform offset array Conclusions Mm-wave integrated waveguide components in silicon technology

17 Frequency scanning array Mm-wave integrated waveguide components in silicon technology

18 Frequency scanning array Mm-wave integrated waveguide components in silicon technology

19 Frequency scanning array Mm-wave integrated waveguide components in silicon technology

20 Outline KOH waveguide process Intrinsic waveguide Coplanar to waveguide transition Frequency scanning array: Slotted waveguide Uniform offset array Conclusions Mm-wave integrated waveguide components in silicon technology

21 Slotted waveguide: design Equivalent rectangular waveguide TE 10 surface currents width length center offset waveguide width Mm-wave integrated waveguide components in silicon technology

22 Outline KOH waveguide process Intrinsic waveguide Coplanar to waveguide transition Frequency scanning array: Slotted waveguide Uniform offset array Conclusions Mm-wave integrated waveguide components in silicon technology

23 Uniform offset array: setup Near field sampling with waveguide wafer probe VNA CNC-machine Mm-wave heads Microscope PC W-band calkit Wafer chuck + positioners + probes Mm-wave integrated waveguide components in silicon technology

24 Uniform offset array: near field Measured near field vs. excitation coefficients 190 μm 190 μm Mm-wave integrated waveguide components in silicon technology

25 E norm [db] [deg.] Uniform offset array: far field theoretical simulated [deg] freq [GHz] Mm-wave integrated waveguide components in silicon technology

26 Uniform offset array: summary Array type Uniform Number of slots 36 Array length [mm] Center frequency [GHz] 94 Scanning angle [degree] 92 Bandwidth [GHz] 20.8 HPBW [degree] 5 SLL [degree] 23 Mm-wave integrated waveguide components in silicon technology

27 Outline KOH waveguide process Intrinsic waveguide Coplanar to waveguide transition Frequency scanning array: Slotted waveguide Uniform offset array Conclusions Mm-wave integrated waveguide components in silicon technology

28 Conclusions: waveguide Mm-wave interconnections Bi-CMOS-compatible process Losses: GHz) Mm-wave integrated waveguide components in silicon technology

29 Conclusions: transition Coplanar feed Interconnection to ICs Broad band Mm-wave integrated waveguide components in silicon technology

30 E norm [db] Conclusions: array Fine lithography accuracy Uniform offset array [deg] Mm-wave integrated waveguide components in silicon technology

31 Acknowledgments The authors would like to thank: the DIMES group, R. Dekker, P. de Graaf, A. Akhnoukh, M. Pelk and J. Long, Delft University of Technology The SmartMix MEMPHIS project R. Jackson, University of Massachusetts Mm-wave integrated waveguide components in silicon technology

Outline. Darren Wang ADS Momentum P2

Outline. Darren Wang ADS Momentum P2 Outline Momentum Basics: Microstrip Meander Line Momentum RF Mode: RFIC Launch Designing with Momentum: Via Fed Patch Antenna Momentum Techniques: 3dB Splitter Look-alike Momentum Optimization: 3 GHz Band

More information

(Sub)mm-wave Calibration

(Sub)mm-wave Calibration 4 (Sub)mm-wave Calibration M. Spirito 1 and L. Galatro 1,2 1 Electronic Research Laboratory, Delft University of Technology, The Netherlands 2 Vertigo Technologies B.V., The Netherlands 4.1 Introduction

More information

Workshop 3-1: Coax-Microstrip Transition

Workshop 3-1: Coax-Microstrip Transition Workshop 3-1: Coax-Microstrip Transition 2015.0 Release Introduction to ANSYS HFSS 1 2015 ANSYS, Inc. Example Coax to Microstrip Transition Analysis of a Microstrip Transmission Line with SMA Edge Connector

More information

Package level Interconnect Options

Package level Interconnect Options Package level Interconnect Options J.Balachandran,S.Brebels,G.Carchon, W.De Raedt, B.Nauwelaers,E.Beyne imec 2005 SLIP 2005 April 2 3 Sanfrancisco,USA Challenges in Nanometer Era Integration capacity F

More information

Powerful features (1)

Powerful features (1) HFSS Overview Powerful features (1) Tangential Vector Finite Elements Provides only correct physical solutions with no spurious modes Transfinite Element Method Adaptive Meshing r E = t E γ i i ( x, y,

More information

NEAR-IR BROADBAND POLARIZER DESIGN BASED ON PHOTONIC CRYSTALS

NEAR-IR BROADBAND POLARIZER DESIGN BASED ON PHOTONIC CRYSTALS U.P.B. Sci. Bull., Series A, Vol. 77, Iss. 3, 2015 ISSN 1223-7027 NEAR-IR BROADBAND POLARIZER DESIGN BASED ON PHOTONIC CRYSTALS Bogdan Stefaniţă CALIN 1, Liliana PREDA 2 We have successfully designed a

More information

SILICON PHOTONICS WAVEGUIDE AND ITS FIBER INTERCONNECT TECHNOLOGY. Jeong Hwan Song

SILICON PHOTONICS WAVEGUIDE AND ITS FIBER INTERCONNECT TECHNOLOGY. Jeong Hwan Song SILICON PHOTONICS WAVEGUIDE AND ITS FIBER INTERCONNECT TECHNOLOGY Jeong Hwan Song CONTENTS Introduction of light waveguides Principals Types / materials Si photonics Interface design between optical fiber

More information

Introduction. Summary. Why computer architecture? Technology trends Cost issues

Introduction. Summary. Why computer architecture? Technology trends Cost issues Introduction 1 Summary Why computer architecture? Technology trends Cost issues 2 1 Computer architecture? Computer Architecture refers to the attributes of a system visible to a programmer (that have

More information

CHAPTER 6 MICROSTRIP RECTANGULAR PATCH ARRAY WITH FINITE GROUND PLANE EFFECTS

CHAPTER 6 MICROSTRIP RECTANGULAR PATCH ARRAY WITH FINITE GROUND PLANE EFFECTS 107 CHAPTER 6 MICROSTRIP RECTANGULAR PATCH ARRAY WITH FINITE GROUND PLANE EFFECTS 6.1 INTRODUCTION The finite ground plane effects of microstrip antennas are one of the issues for the wireless mobile communication

More information

Optimization of Broadband RF Performance and ESD Robustness by π-model Distributed ESD Protection Scheme

Optimization of Broadband RF Performance and ESD Robustness by π-model Distributed ESD Protection Scheme Optimization of Broadband RF Performance and ESD Robustness by π-model Distributed ESD Protection Scheme Ming-Dou Ker and Bing-Jye Kuo Nanoelectronics and Gigascale Systems Laboratory, Institute of Electronics,

More information

Quilt Packaging For Power Electronics

Quilt Packaging For Power Electronics Quilt Packaging For Power Electronics 21 March 2013 Jason M. Kulick President, Co-Founder Indiana Integrated Circuits, LLC Overview Introduction Quilt Packaging (QP) technology Concept Examples Advantages

More information

SMAFTI Package Technology Features Wide-Band and Large-Capacity Memory

SMAFTI Package Technology Features Wide-Band and Large-Capacity Memory SMAFTI Package Technology Features Wide-Band and Large-Capacity Memory KURITA Yoichiro, SOEJIMA Koji, KAWANO Masaya Abstract and NEC Corporation have jointly developed an ultra-compact system-in-package

More information

Test and Measurement Challenges for 3D IC Development. R. Robertazzi IBM Research

Test and Measurement Challenges for 3D IC Development. R. Robertazzi IBM Research Test and Measurement Challenges for 3D IC Development R. Robertazzi IBM Research PFA Bill Price. Pete Sorce. John Ott. David Abraham. Pavan Samudrala Digital Test Kevin Stawaisz. TEL P12 Prober Glen Lansman,

More information

CMOS compatible highly efficient grating couplers with a stair-step blaze profile

CMOS compatible highly efficient grating couplers with a stair-step blaze profile CMOS compatible highly efficient grating couplers with a stair-step blaze profile Zhou Liang( ) a), Li Zhi-Yong( ) a), Hu Ying-Tao( ) a), Xiong Kang( ) a), Fan Zhong-Chao( ) b), Han Wei-Hua( ) b), Yu Yu-De

More information

RF Probing With Rohde & Schwarz ZNB VNA. PacketMicro, Inc Wyatt Drive, Suite 9, Santa Clara, CA

RF Probing With Rohde & Schwarz ZNB VNA. PacketMicro, Inc Wyatt Drive, Suite 9, Santa Clara, CA RF Probing With Rohde & Schwarz ZNB VNA PacketMicro, Inc. 1900 Wyatt Drive, Suite 9, Santa Clara, CA 95054 www.packetmicro.com Outline Why RF Probing Page 3 4 S-Probe Overview Page 5-8 RF Probing Tips

More information

Embedded UTCP interposers for miniature smart sensors

Embedded UTCP interposers for miniature smart sensors Embedded UTCP interposers for miniature smart sensors T. Sterken 1,2, M. Op de Beeck 2, Tom Torfs 2, F. Vermeiren 1,2, C. Van Hoof 2, J. Vanfleteren 1,2 1 CMST (affiliated with Ugent and IMEC), Technologiepark

More information

D5.2: Packaging and fiber-pigtailing of the 2 nd generation 2x2 optical interconnect router

D5.2: Packaging and fiber-pigtailing of the 2 nd generation 2x2 optical interconnect router ICT - Information and Communication Technologies Merging Plasmonics and Silicon Photonics Technology towards Tb/s routing in optical interconnects Collaborative Project Grant Agreement Number 249135 D5.2:

More information

Obsolete. Product Specification PE4210. Product Description. SPDT UltraCMOS RF Switch 10 MHz - 3 GHz Features Single 3-volt power supply

Obsolete. Product Specification PE4210. Product Description. SPDT UltraCMOS RF Switch 10 MHz - 3 GHz Features Single 3-volt power supply Product Description The PE421 UltraCMOS RF Switch is designed to cover a broad range of applications from 1 MHz to 3 GHz. This singlesupply switch integrates on-board CMOS control logic driven by a simple,

More information

56/80 Gb/s PCB transmission lines. and. 56 Gb/s End-launch GPPO connector

56/80 Gb/s PCB transmission lines. and. 56 Gb/s End-launch GPPO connector White paper: WP141-1 56/8 b/s PCB transmission lines and 56 b/s End-launch PPO connector ----- Electrical Interconnection basic technology development ----- Takada RF Labs, Inc. 214/1/2 E-mail: contact@takadarf.com

More information

Quilt Packaging Microchip Interconnect Technology

Quilt Packaging Microchip Interconnect Technology Quilt Packaging Microchip Interconnect Technology 18 November 2012 Jason M. Kulick President, Co-Founder Indiana Integrated Circuits, LLC Overview Introduction to IIC Quilt Packaging (QP) Concept Electrical

More information

Non-contact Test at Advanced Process Nodes

Non-contact Test at Advanced Process Nodes Chris Sellathamby, J. Hintzke, B. Moore, S. Slupsky Scanimetrics Inc. Non-contact Test at Advanced Process Nodes June 8-11, 8 2008 San Diego, CA USA Overview Advanced CMOS nodes are a challenge for wafer

More information

V DD Power supply voltage V. V I Voltage on any input -0.3 T ST T OP. PIN Input power (50Ω) 30 dbm V ESD

V DD Power supply voltage V. V I Voltage on any input -0.3 T ST T OP. PIN Input power (50Ω) 30 dbm V ESD Product Description The PE4239 UltraCMOS RF switch is designed to cover a broad range of applications from DC through 3. GHz. This reflective switch integrates on-board CMOS control logic with a low voltage

More information

VLSI Test Technology and Reliability (ET4076)

VLSI Test Technology and Reliability (ET4076) VLSI Test Technology and Reliability (ET4076) Lecture 8(2) I DDQ Current Testing (Chapter 13) Said Hamdioui Computer Engineering Lab Delft University of Technology 2009-2010 1 Learning aims Describe the

More information

Innovative 3D Structures Utilizing Wafer Level Fan-Out Technology

Innovative 3D Structures Utilizing Wafer Level Fan-Out Technology Innovative 3D Structures Utilizing Wafer Level Fan-Out Technology JinYoung Khim #, Curtis Zwenger *, YoonJoo Khim #, SeWoong Cha #, SeungJae Lee #, JinHan Kim # # Amkor Technology Korea 280-8, 2-ga, Sungsu-dong,

More information

An Overview of Standard Cell Based Digital VLSI Design

An Overview of Standard Cell Based Digital VLSI Design An Overview of Standard Cell Based Digital VLSI Design With examples taken from the implementation of the 36-core AsAP1 chip and the 1000-core KiloCore chip Zhiyi Yu, Tinoosh Mohsenin, Aaron Stillmaker,

More information

Obsolete Parameter Conditions Minimum Typical Maximum Units

Obsolete Parameter Conditions Minimum Typical Maximum Units Product Description The PE4242 UltraCMOS RF Switch is designed to cover a broad range of applications from 1 MHz through 3 GHz. This reflective switch integrates on-board CMOS control logic with a low

More information

Board Design Guidelines for PCI Express Architecture

Board Design Guidelines for PCI Express Architecture Board Design Guidelines for PCI Express Architecture Cliff Lee Staff Engineer Intel Corporation Member, PCI Express Electrical and Card WGs The facts, techniques and applications presented by the following

More information

Optimization of Electronically Scanned Conformal Antenna Array Synthesis Using Artificial Neural Network Algorithm

Optimization of Electronically Scanned Conformal Antenna Array Synthesis Using Artificial Neural Network Algorithm Forum for Electromagnetic Research Methods and Application Technologies (FERMAT) Optimization of Electronically Scanned Conformal Antenna Array Synthesis Using Artificial Neural Network Algorithm HAMDI

More information

PSMC Roadmap For Integrated Photonics Manufacturing

PSMC Roadmap For Integrated Photonics Manufacturing PSMC Roadmap For Integrated Photonics Manufacturing Richard Otte Promex Industries Inc. Santa Clara California For the Photonics Systems Manufacturing Consortium April 21, 2016 Meeting the Grand Challenges

More information

11525A 11524A

11525A 11524A 8 Typical Configuration 11900A 11901A 11904A 8059A 1250-1159 1250-1748 85058-60007 11900C 11901C 11901D 11904C 11904D 8059C 1250-1462 85058-60009 1190A 1250-166 1250-174 11525A 11524A 11852B 11852B Option

More information

Power dissipation! The VLSI Interconnect Challenge. Interconnect is the crux of the problem. Interconnect is the crux of the problem.

Power dissipation! The VLSI Interconnect Challenge. Interconnect is the crux of the problem. Interconnect is the crux of the problem. The VLSI Interconnect Challenge Avinoam Kolodny Electrical Engineering Department Technion Israel Institute of Technology VLSI Challenges System complexity Performance Tolerance to digital noise and faults

More information

MONOLITHIC NEAR INFRARED IMAGE SENSORS ENABLED BY QUANTUM DOT PHOTODETECTOR

MONOLITHIC NEAR INFRARED IMAGE SENSORS ENABLED BY QUANTUM DOT PHOTODETECTOR MONOLITHIC NEAR INFRARED IMAGE SENSORS ENABLED BY QUANTUM DOT PHOTODETECTOR PAWEŁ E. MALINOWSKI, E. GEORGITZIKIS, J. MAES, M. MAMUN, O. ENZING, F. FRAZZICA, J.VAN OLMEN, P. DE MOOR, P. HEREMANS, Z. HENS,

More information

Metrology for Characterization of Wafer Thickness Uniformity During 3D-IC Processing. SEMATECH Workshop on 3D Interconnect Metrology

Metrology for Characterization of Wafer Thickness Uniformity During 3D-IC Processing. SEMATECH Workshop on 3D Interconnect Metrology Metrology for Characterization of Wafer Thickness Uniformity During 3D-IC Processing SEMATECH Workshop on 3D Interconnect Metrology Chris Lee July 11, 2012 Outline Introduction Motivation For New Metrology

More information

SECTION 1 IMP / UMP R107

SECTION 1 IMP / UMP R107 1 SECTION 1 / UMP R107 Contents Introduction... 1-4 to 1-6 Characteristics...1-7 Board to board connectors...1-8 Receptacle packaging...1-9 Assembly instructions... 1-9 to 1-10 UMP Characteristics...1-11

More information

General Purpose, Low Noise NPN Silicon Bipolar Transistor. Technical Data AT AT-41533

General Purpose, Low Noise NPN Silicon Bipolar Transistor. Technical Data AT AT-41533 General Purpose, Low Noise NPN Silicon Bipolar Transistor Technical Data AT-411 AT-433 Features General Purpose NPN Bipolar Transistor 9 MHz Performance: AT-411: 1 db NF,. db G A AT-433: 1 db NF, 14. db

More information

Spherical Geometry Selection Used for Error Evaluation

Spherical Geometry Selection Used for Error Evaluation Spherical Geometry Selection Used for Error Evaluation Greg Hindman, Pat Pelland, Greg Masters Nearfield Systems Inc., Torrance, CA 952, USA ghindman@nearfield.com, ppelland@nearfield.com, gmasters@nearfield.com

More information

Typical Performance 1. IS-95C ACPR dbm WCDMA ACLR dbm

Typical Performance 1. IS-95C ACPR dbm WCDMA ACLR dbm Device Features OIP3 = 49.0 dbm @ 1900 MHz Gain = 12.5 db @ 1900 MHz Output P1 db = 30.3 dbm @ 1900 MHz 50 Ω Cascadable Patented Over Voltage Protection Circuit Lead-free/RoHS-compliant SOIC-8 package

More information

Understanding Strip (Finite) and Slot (Infinite) Ground based EM simulations in ADS

Understanding Strip (Finite) and Slot (Infinite) Ground based EM simulations in ADS Understanding Strip (Finite) and Slot (Infinite) Ground based EM simulations in ADS ADS offer three ways in which designers can model the return path (ground) for their structures to perform EM simulations.

More information

Introduction to Integrated Photonic Devices

Introduction to Integrated Photonic Devices Introduction to Integrated Photonic Devices Class: Integrated Photonic Devices Time: Wed. 1:10pm ~ 3:00pm. Fri. 10:10am ~ 11:00am Classroom: 資電 106 Lecturer: Prof. 李明昌 (Ming-Chang Lee) Block Diagram of

More information

Advanced CSP & Turnkey Solutions. Fumio Ohyama Tera Probe, Inc.

Advanced CSP & Turnkey Solutions. Fumio Ohyama Tera Probe, Inc. Advanced CSP & Turnkey Solutions Fumio Ohyama Tera Probe, Inc. Tera Probe - Corporate Overview 1. Company : Tera Probe, Inc. 2. Founded : August, 2005 3. Capital : Approx. USD118.2 million (as of March

More information

Lecture 6. Dielectric Waveguides and Optical Fibers. Slab Waveguide, Modes, V-Number Modal, Material, and Waveguide Dispersions

Lecture 6. Dielectric Waveguides and Optical Fibers. Slab Waveguide, Modes, V-Number Modal, Material, and Waveguide Dispersions Lecture 6 Dielectric Waveguides and Optical Fibers Slab Waveguide, Modes, V-Number Modal, Material, and Waveguide Dispersions Step-Index Fiber, Multimode and Single Mode Fibers Numerical Aperture, Coupling

More information

Design of Polygonal Patch Antennas with a. Broad-Band Behavior via a Proper Perturbation of Conventional Rectangular Radiators

Design of Polygonal Patch Antennas with a. Broad-Band Behavior via a Proper Perturbation of Conventional Rectangular Radiators Università degli Studi ROMA TRE Dipartimento di Elettronica Applicata Via della Vasca Navale 84 00146 Roma Design of Polygonal Patch Antennas with a Broad-Band Behavior via a Proper Perturbation of Conventional

More information

A Single Grating-lens Focusing Two Orthogonally Polarized Beams in Opposite Direction

A Single Grating-lens Focusing Two Orthogonally Polarized Beams in Opposite Direction , pp.41-45 http://dx.doi.org/10.14257/astl.2016.140.08 A Single Grating-lens Focusing Two Orthogonally Polarized Beams in Opposite Direction Seung Dae Lee 1 1* Dept. of Electronic Engineering, Namseoul

More information

Chapter 1 Introduction

Chapter 1 Introduction Chapter 1 Introduction 1.1 MOTIVATION 1.1.1 LCD Industry and LTPS Technology [1], [2] The liquid-crystal display (LCD) industry has shown rapid growth in five market areas, namely, notebook computers,

More information

"High Frequency Ceramic Solutions"

High Frequency Ceramic Solutions Designed for: BAN, Bluetooth, 802.11, WLAN, igbee, Propietary Protocol, ISM, Smart Energy, WiMax Page 1 of 9 General Specifications Part Number Operating Frequency (MHz) Impedance Operating Temperature

More information

TEXAS INSTRUMENTS ANALOG UNIVERSITY PROGRAM DESIGN CONTEST MIXED SIGNAL TEST INTERFACE CHRISTOPHER EDMONDS, DANIEL KEESE, RICHARD PRZYBYLA SCHOOL OF

TEXAS INSTRUMENTS ANALOG UNIVERSITY PROGRAM DESIGN CONTEST MIXED SIGNAL TEST INTERFACE CHRISTOPHER EDMONDS, DANIEL KEESE, RICHARD PRZYBYLA SCHOOL OF TEXASINSTRUMENTSANALOGUNIVERSITYPROGRAMDESIGNCONTEST MIXED SIGNALTESTINTERFACE CHRISTOPHEREDMONDS,DANIELKEESE,RICHARDPRZYBYLA SCHOOLOFELECTRICALENGINEERINGANDCOMPUTERSCIENCE OREGONSTATEUNIVERSITY I. PROJECT

More information

Scanning Acoustic Microscopy For Metrology of 3D Interconnect Bonded Wafers

Scanning Acoustic Microscopy For Metrology of 3D Interconnect Bonded Wafers Scanning Acoustic Microscopy For Metrology of 3D Interconnect Bonded Wafers Jim McKeon, Ph.D. - Sonix, Director of Technology Sriram Gopalan, Ph.D. - Sonix, Technology Engineer 8700 Morrissette Drive 8700

More information

New Dimensions in Microarchitecture Harnessing 3D Integration Technologies

New Dimensions in Microarchitecture Harnessing 3D Integration Technologies New Dimensions in Microarchitecture Harnessing 3D Integration Technologies Kerry Bernstein IBM T.J. Watson Research Center Yorktown Heights, NY 6 March, 27 San Jose, California DARPA Microsystems Technology

More information

Removing Aluminum Cap in 90 nm Copper Technology

Removing Aluminum Cap in 90 nm Copper Technology Removing Aluminum Cap in 90 nm Copper Technology Emanuele Capitanio Matteo Nobile Didier Renard ST Microelectronics Agrate (Italy) ST Microelectronics Agrate (Italy) Credence Content What Alucap is Needs

More information

Practical hints: splitter characterization. J. Ruefenacht, M. Wollensack, J. Hoffmann, M. Zeier

Practical hints: splitter characterization. J. Ruefenacht, M. Wollensack, J. Hoffmann, M. Zeier Practical hints: splitter characterization J. Ruefenacht, M. Wollensack, J. Hoffmann, M. Zeier Motivation once upon a time at METAS Juerg Ruefenacht HF-Circuits, European ANAMET Meeting, METAS 03.06.2015

More information

3D Integration & Packaging Challenges with through-silicon-vias (TSV)

3D Integration & Packaging Challenges with through-silicon-vias (TSV) NSF Workshop 2/02/2012 3D Integration & Packaging Challenges with through-silicon-vias (TSV) Dr John U. Knickerbocker IBM - T.J. Watson Research, New York, USA Substrate IBM Research Acknowledgements IBM

More information

Chip/Package/Board Design Flow

Chip/Package/Board Design Flow Chip/Package/Board Design Flow EM Simulation Advances in ADS 2011.10 1 EM Simulation Advances in ADS2011.10 Agilent EEsof Chip/Package/Board Design Flow 2 RF Chip/Package/Board Design Industry Trends Increasing

More information

Physical Design Implementation for 3D IC Methodology and Tools. Dave Noice Vassilios Gerousis

Physical Design Implementation for 3D IC Methodology and Tools. Dave Noice Vassilios Gerousis I NVENTIVE Physical Design Implementation for 3D IC Methodology and Tools Dave Noice Vassilios Gerousis Outline 3D IC Physical components Modeling 3D IC Stack Configuration Physical Design With TSV Summary

More information

IMEC CORE CMOS P. MARCHAL

IMEC CORE CMOS P. MARCHAL APPLICATIONS & 3D TECHNOLOGY IMEC CORE CMOS P. MARCHAL OUTLINE What is important to spec 3D technology How to set specs for the different applications - Mobile consumer - Memory - High performance Conclusions

More information

TQPED MMIC Design Training

TQPED MMIC Design Training TQPED MMIC Design Training Outline Installation and Use of the Library AWR AWR Design Kit (PDK Process Design Kit) ICED Layout Kit Create a new document using the Library Environment Setup Hotkeys Background

More information

Burn-in & Test Socket Workshop

Burn-in & Test Socket Workshop Burn-in & Test Socket Workshop IEEE March 4-7, 2001 Hilton Mesa Pavilion Hotel Mesa, Arizona IEEE COMPUTER SOCIETY Sponsored By The IEEE Computer Society Test Technology Technical Council COPYRIGHT NOTICE

More information

Package (1C) Young Won Lim 3/20/13

Package (1C) Young Won Lim 3/20/13 Copyright (c) 2011-2013 Young W. Lim. Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.2 or any later version published

More information

The Future of Electrical I/O for Microprocessors. Frank O Mahony Intel Labs, Hillsboro, OR USA

The Future of Electrical I/O for Microprocessors. Frank O Mahony Intel Labs, Hillsboro, OR USA The Future of Electrical I/O for Microprocessors Frank O Mahony frank.omahony@intel.com Intel Labs, Hillsboro, OR USA 1 Outline 1TByte/s I/O: motivation and challenges Circuit Directions Channel Directions

More information

Package (1C) Young Won Lim 3/13/13

Package (1C) Young Won Lim 3/13/13 Copyright (c) 2011-2013 Young W. Lim. Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.2 or any later version published

More information

SAS-2 Zero-Length Test Load Characterization (07-013r7) Barry Olawsky Hewlett Packard (8/2/2007)

SAS-2 Zero-Length Test Load Characterization (07-013r7) Barry Olawsky Hewlett Packard (8/2/2007) SAS-2 Zero-Length Test Load Characterization (07-013r7) Barry Olawsky Hewlett Packard (8/2/2007) 07-013r7 SAS-2 Zero-Length Test Load Characterization 1 Zero-Length Test Load Provides ideal connection

More information

ESD Protection Design on T/R Switch with Embedded SCR in CMOS Process

ESD Protection Design on T/R Switch with Embedded SCR in CMOS Process ESD Protection Design on T/R Switch with Embedded SCR in CMOS Process Tao-Yi Hung and Ming-Dou Ker Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan Abstract- ESD protection design

More information

UBCx Phot1x: Silicon Photonics Design, Fabrication and Data Analysis

UBCx Phot1x: Silicon Photonics Design, Fabrication and Data Analysis UBCx Phot1x: Silicon Photonics Design, Fabrication and Data Analysis Course Syllabus Table of Contents Course Syllabus 1 Course Overview 1 Course Learning Objective 1 Course Philosophy 1 Course Details

More information

Moore s s Law, 40 years and Counting

Moore s s Law, 40 years and Counting Moore s s Law, 40 years and Counting Future Directions of Silicon and Packaging Bill Holt General Manager Technology and Manufacturing Group Intel Corporation InterPACK 05 2005 Heat Transfer Conference

More information

Mm-wave Technologies and Components for 5G Applications. Liam Devlin, Interlligent UK Seminar, May 18 th 2017

Mm-wave Technologies and Components for 5G Applications. Liam Devlin, Interlligent UK Seminar, May 18 th 2017 Mm-wave Technologies and Components for 5G Applications Liam Devlin, Interlligent UK Seminar, May 18 th 2017 Introduction Full details of the 5G standard are yet to be defined But we do know that it is

More information

Silicon Based Packaging for 400/800/1600 Gb/s Optical Interconnects

Silicon Based Packaging for 400/800/1600 Gb/s Optical Interconnects Silicon Based Packaging for 400/800/1600 Gb/s Optical Interconnects The Low Cost Solution for Parallel Optical Interconnects Into the Terabit per Second Age Executive Summary White Paper PhotonX Networks

More information

Improved RSOL Planar Calibration via EM Modelling and Reduced Spread Resistive Layers

Improved RSOL Planar Calibration via EM Modelling and Reduced Spread Resistive Layers Improved RSOL Planar Calibration via EM Modelling and Reduced Spread Resistive Layers M. Spirito 1, L. Galatro 1, G. Lorito 2, T. Zoumpoulidis 2, F. Mubarak 1,3 1 Delft University of Technology, Electronic

More information

Low Current, High Performance NPN Silicon Bipolar Transistor. Technical Data AT AT-32033

Low Current, High Performance NPN Silicon Bipolar Transistor. Technical Data AT AT-32033 Low Current, High Performance NPN Silicon Bipolar Transistor Technical Data AT-311 AT-333 Features High Performance Bipolar Transistor Optimized for Low Current, Low Voltage Operation 9 MHz Performance:

More information

A 20 GSa/s 8b ADC with a 1 MB Memory in 0.18 µm CMOS

A 20 GSa/s 8b ADC with a 1 MB Memory in 0.18 µm CMOS A 20 GSa/s 8b ADC with a 1 MB Memory in 0.18 µm CMOS Ken Poulton, Robert Neff, Brian Setterberg, Bernd Wuppermann, Tom Kopley, Robert Jewett, Jorge Pernillo, Charles Tan, Allen Montijo 1 Agilent Laboratories,

More information

Direct Connection of OML Frequency Extenders to Keysight s PNA-C (E836xC) VNA for 1-Path 2-Port S-Parameter Measurements

Direct Connection of OML Frequency Extenders to Keysight s PNA-C (E836xC) VNA for 1-Path 2-Port S-Parameter Measurements Direct Connection of OML Frequency Extenders to Keysight s PNA-C (E836xC) VNA for 1-Path 2-Port S-Parameter Measurements Introduction For full two-port S-parameter measurements to extend PNA-C vector network

More information

Overlaid Mesh Topology Design and Deadlock Free Routing in Wireless Network-on-Chip. Danella Zhao and Ruizhe Wu Presented by Zhonghai Lu, KTH

Overlaid Mesh Topology Design and Deadlock Free Routing in Wireless Network-on-Chip. Danella Zhao and Ruizhe Wu Presented by Zhonghai Lu, KTH Overlaid Mesh Topology Design and Deadlock Free Routing in Wireless Network-on-Chip Danella Zhao and Ruizhe Wu Presented by Zhonghai Lu, KTH Outline Introduction Overview of WiNoC system architecture Overlaid

More information

Optoelectronic Packaging for 16-Channel Optical Backplane Bus with VHOEs

Optoelectronic Packaging for 16-Channel Optical Backplane Bus with VHOEs Optoelectronic Packaging for 16-Channel Optical Backplane Bus with VHOEs J.H. Choi*, H. Bi*, J. Ellis**, R. T. Chen* * Microelectronics Research Center, Department of Electrical and Computer Engineering,

More information

Development of Focal-Plane Arrays and Beamforming Networks at DRAO

Development of Focal-Plane Arrays and Beamforming Networks at DRAO Development of Focal-Plane Arrays and Beamforming Networks at DRAO Bruce Veidt Dominion Radio Astrophysical Observatory Herzberg Institute of Astrophysics National Research Council of Canada Penticton,

More information

Wafer Level Packaging The Promise Evolves Dr. Thomas Di Stefano Centipede Systems, Inc. IWLPC 2008

Wafer Level Packaging The Promise Evolves Dr. Thomas Di Stefano Centipede Systems, Inc. IWLPC 2008 Wafer Level Packaging The Promise Evolves Dr. Thomas Di Stefano Centipede Systems, Inc. IWLPC 2008 / DEVICE 1.E+03 1.E+02 1.E+01 1.E+00 1.E-01 1.E-02 1.E-03 1.E-04 1.E-05 1.E-06 1.E-07 Productivity Gains

More information

POWER4 Test Chip. Bradley D. McCredie Senior Technical Staff Member IBM Server Group, Austin. August 14, 1999

POWER4 Test Chip. Bradley D. McCredie Senior Technical Staff Member IBM Server Group, Austin. August 14, 1999 Bradley D. McCredie Senior Technical Staff Member Server Group, Austin August 14, 1999 Presentation Overview Design objectives Chip overview Technology Circuits Implementation Results Test Chip Objectives

More information

THz Transmission Properties of Metallic Slit Array

THz Transmission Properties of Metallic Slit Array THz Transmission Properties of Metallic Slit Array Guozhong Zhao * Department of Physics, Capital Normal University, Beijing 100048, China Beijing Key Lab for Terahertz Spectroscopy and Imaging Key Lab

More information

Frequency Selective Surfaces with Inhomogeneous, Periodic Substrates: Analysis and Optimization

Frequency Selective Surfaces with Inhomogeneous, Periodic Substrates: Analysis and Optimization Frequency Selective Surfaces with Inhomogeneous, Periodic Substrates: Analysis and Optimization Arya Fallahi, Christian Hafner, and Rüdiger Vahldieck Computational Optics Group Outline Motivation Frequency

More information

High Performance Electronics Integration in Flexible Technology

High Performance Electronics Integration in Flexible Technology High Performance Electronics Integration in Flexible Technology February 10, 2011 www.americansemi.com 2011 American Semiconductor, Inc. All rights reserved. About American Semiconductor Corporate Headquarters

More information

Beyond Chip Stacking---Quilt Packaging Enabled 3D Systems

Beyond Chip Stacking---Quilt Packaging Enabled 3D Systems Beyond Chip Stacking---Quilt Packaging Enabled 3D Systems Jason Kulick, President & Co-Founder jason.kulick@indianaic.com 574-217-4612 (South Bend, IN) May 3, 2016 2016 New England IMAPS Symposium Presentation

More information

Optimum Placement of Decoupling Capacitors on Packages and Printed Circuit Boards Under the Guidance of Electromagnetic Field Simulation

Optimum Placement of Decoupling Capacitors on Packages and Printed Circuit Boards Under the Guidance of Electromagnetic Field Simulation Optimum Placement of Decoupling Capacitors on Packages and Printed Circuit Boards Under the Guidance of Electromagnetic Field Simulation Yuzhe Chen, Zhaoqing Chen and Jiayuan Fang Department of Electrical

More information

CAD for VLSI. Debdeep Mukhopadhyay IIT Madras

CAD for VLSI. Debdeep Mukhopadhyay IIT Madras CAD for VLSI Debdeep Mukhopadhyay IIT Madras Tentative Syllabus Overall perspective of VLSI Design MOS switch and CMOS, MOS based logic design, the CMOS logic styles, Pass Transistors Introduction to Verilog

More information

Silicon Photonics Scalable Design Framework:

Silicon Photonics Scalable Design Framework: Silicon Photonics Scalable Design Framework: From Design Concept to Physical Verification Hossam Sarhan Technical Marketing Engineer hossam_sarhan@mentor.com Objective: Scalable Photonics Design Infrastructure

More information

Digital Integrated Circuits A Design Perspective. Jan M. Rabaey

Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Digital Integrated Circuits A Design Perspective Jan M. Rabaey Outline (approximate) Introduction and Motivation The VLSI Design Process Details of the MOS Transistor Device Fabrication Design Rules CMOS

More information

March 15-18, 2015 Hilton Phoenix / Mesa Hotel Mesa, Arizona Archive Session 4

March 15-18, 2015 Hilton Phoenix / Mesa Hotel Mesa, Arizona Archive Session 4 Proceedings March 15-18, 2015 Hilton Phoenix / Mesa Hotel Mesa, Arizona Archive Session 4 2015 BiTS Workshop Image: BCFC/iStock Session 4 Rafiq Hussain Session Chair BiTS Workshop 2015 Schedule Performance

More information

Gigascale Integration Design Challenges & Opportunities. Shekhar Borkar Circuit Research, Intel Labs October 24, 2004

Gigascale Integration Design Challenges & Opportunities. Shekhar Borkar Circuit Research, Intel Labs October 24, 2004 Gigascale Integration Design Challenges & Opportunities Shekhar Borkar Circuit Research, Intel Labs October 24, 2004 Outline CMOS technology challenges Technology, circuit and μarchitecture solutions Integration

More information

Design of Aperiodic Frequency Selective Surfaces for Compact Quasi-Optical Networks

Design of Aperiodic Frequency Selective Surfaces for Compact Quasi-Optical Networks Design of Aperiodic Frequency Selective Surfaces for Compact Quasi-Optical Networks Min Zhou 1, Stig B. Sørensen 1, Niels Vesterdal 1, Raymond Dickie 2, Paul Baine 2, John Montgomery 2, Robert Cahill 2,

More information

Typical Performance 1. 2 OIP3 _ measured with two tones at an output of 0 dbm per tone separated by 1 MHz. RFout

Typical Performance 1. 2 OIP3 _ measured with two tones at an output of 0 dbm per tone separated by 1 MHz. RFout Device Features 3 ~ 3.3V supply No Dropping Resistor Required No matching circuit needed Lead-free/Green/RoHS compliant SOT-343 package Product Description BeRex s BGS6 is a high SiGe HBT MMIC amplifier,

More information

CMPEN 411 VLSI Digital Circuits. Lecture 01: Introduction

CMPEN 411 VLSI Digital Circuits. Lecture 01: Introduction CMPEN 411 VLSI Digital Circuits Kyusun Choi Lecture 01: Introduction CMPEN 411 Course Website link at: http://www.cse.psu.edu/~kyusun/teach/teach.html [Adapted from Rabaey s Digital Integrated Circuits,

More information

OVERALL TECHNOLOGY ROADMAP CHARACTERISTICS TABLES CONTENTS

OVERALL TECHNOLOGY ROADMAP CHARACTERISTICS TABLES CONTENTS OVERALL TECHNOLOGY ROADMAP CHARACTERISTICS TABLES CONTENTS Table 1a Product Generations and Chip Size Model Technology Nodes Near-term Years... 2 Table 1b Product Generations and Chip Size Model Technology

More information

Using Sonnet in a Cadence Virtuoso Design Flow

Using Sonnet in a Cadence Virtuoso Design Flow Using Sonnet in a Cadence Virtuoso Design Flow Purpose of this document: This document describes the Sonnet plug-in integration for the Cadence Virtuoso design flow, for silicon accurate EM modelling of

More information

GHz 6-Bit Digital Phase Shifter

GHz 6-Bit Digital Phase Shifter 1.1 1.5 GHz 6-Bit Digital Phase Shifter Features Frequency Range: 1.1 to 1.5 GHz RMS Error ~ 1.6 deg. 5 db Insertion Loss TTL Control Inputs.5-um InGaAs phemt Technology 28 Lead 7. x 7. x.8 mm 3 QFN Package

More information

Vertical Circuits. Small Footprint Stacked Die Package and HVM Supply Chain Readiness. November 10, Marc Robinson Vertical Circuits, Inc

Vertical Circuits. Small Footprint Stacked Die Package and HVM Supply Chain Readiness. November 10, Marc Robinson Vertical Circuits, Inc Small Footprint Stacked Die Package and HVM Supply Chain Readiness Marc Robinson Vertical Circuits, Inc November 10, 2011 Vertical Circuits Building Blocks for 3D Interconnects Infrastructure Readiness

More information

3M TM VCP TM Package Stripline Two Port Characterization. David A. Hanson Division Scientist 3M Microelectronic Packaging

3M TM VCP TM Package Stripline Two Port Characterization. David A. Hanson Division Scientist 3M Microelectronic Packaging 3M TM VCP TM Package Stripline Two Port Characterization David A. Hanson Division Scientist 3M Microelectronic Packaging 3M 21 2 Background To support the requirements of 2.5GBs and 1GBs data communication

More information

Silicon Photonics PDK Development

Silicon Photonics PDK Development Hewlett Packard Labs Silicon Photonics PDK Development M. Ashkan Seyedi Large-Scale Integrated Photonics Hewlett Packard Labs, Palo Alto, CA ashkan.seyedi@hpe.com Outline Motivation of Silicon Photonics

More information

Contents Contents Creating a Simulation Example: A Dipole Antenna AMDS User s Guide

Contents Contents Creating a Simulation Example: A Dipole Antenna AMDS User s Guide Contents Contents 1 Creating a Simulation 7 Introduction 8 Data Files for Examples 8 Software Organization 9 Constructing the Geometry 10 Creating the Mesh 11 Defining Run Parameters 13 Requesting Results

More information

Micron Level Placement Accuracy for Wafer Scale Packaging of P-Side Down Lasers in Optoelectronic Products

Micron Level Placement Accuracy for Wafer Scale Packaging of P-Side Down Lasers in Optoelectronic Products Micron Level Placement Accuracy for Wafer Scale Packaging of P-Side Down Lasers in Optoelectronic Products Daniel D. Evans, Jr. and Zeger Bok Palomar Technologies, Inc. 2728 Loker Avenue West Carlsbad,

More information

PLANAR LIGHTWAVE CIRCUITS FOR USE IN ADVANCED OPTICAL INSTRUMENTATION

PLANAR LIGHTWAVE CIRCUITS FOR USE IN ADVANCED OPTICAL INSTRUMENTATION PLANAR LIGHTWAVE CIRCUITS FOR USE IN ADVANCED OPTICAL INSTRUMENTATION AN ENABLENCE ARTICLE WRITTEN BY DR. MATT PEARSON, VP TECHNOLOGY & ASHOK BALAKRISHNAN, DIRECTOR OF PRODUCT DEVELOPMENT PUBLISHED IN

More information

Magnetic probe holders are fully adjustable for more DUT heights and probe styles

Magnetic probe holders are fully adjustable for more DUT heights and probe styles Data Sheet The W4.0 x L6.5 mini probe station is a manual probe station designed for a versatile and comfortable operation on up to 4.0 wafers or 4.0 x 6.5 printed circuit board assemblies. This mini probe

More information

Novel manufacturing route for scale up production of Terahertz technology devices Penchev, Pavel; Shang, Xiaobang; Lancaster, Michael; Dimov, Stefan

Novel manufacturing route for scale up production of Terahertz technology devices Penchev, Pavel; Shang, Xiaobang; Lancaster, Michael; Dimov, Stefan Novel manufacturing route for scale up production of Terahertz technology devices Penchev, Pavel; Shang, Xiaobang; Lancaster, Michael; Dimov, Stefan Document Version Early version, also known as pre-print

More information

Monolithic 3D Integration using Standard Fab & Standard Transistors. Zvi Or-Bach CEO MonolithIC 3D Inc.

Monolithic 3D Integration using Standard Fab & Standard Transistors. Zvi Or-Bach CEO MonolithIC 3D Inc. Monolithic 3D Integration using Standard Fab & Standard Transistors Zvi Or-Bach CEO MonolithIC 3D Inc. 3D Integration Through Silicon Via ( TSV ), Monolithic Increase integration Reduce interconnect total

More information

Near-field time-of-arrival measurements for four feed-arms with a bicone switch

Near-field time-of-arrival measurements for four feed-arms with a bicone switch EM Implosion Memos Memo 37 February 2010 Near-field time-of-arrival measurements for four feed-arms with a bicone switch Prashanth Kumar, Serhat Altunc, Carl E. Baum, Christos G. Christodoulou and Edl

More information