Understanding the tradeoffs and Tuning the methodology

Transcription

1 Understanding the tradeoffs and Tuning the methodology Graham Scott, Technical Lead ARM Cortex Application Processors, Cadence Nandan Nayampally, Director CPU Product Marketing, ARM Inc 1

2 Agenda Market drivers for the Cortex-A8 Introduction to the Cortex-A8 The range of implementation options for the Cortex-A8 Summary 2

3 Enabling Enhanced User Experiences Handle and process high data rates Provide the power for the next gen 3D games Browse any website Edit & Enhance 8MP photos Handle any office & document Edit & Enhance captured videos Handle future User Interfaces Watch any video in any format 3

4 Multi-function and Convergence 4

5 CMC Requirements Example Better Processor and System Performance Rich Operating Systems Advanced browsers Advanced security General applications 3D graphics & gaming Java & Execution Environments High bandwidth networks Multi-format audio Video Recorder / Player Voice/Video over IP..and these pictures are from today s ARM technology 5

6 Cortex-A8: High Performance Uni-Processor High throughput processor >1GHz operation, delivering 2,000+ DMIPS Low-power implementations at under 300 mw In-order, dual-issue, superscalar core MMU for running virtual memory open OS Thumb-2 technology NEON media acceleration technology Jazelle-RCT technology TrustZone security foundation IEM Intelligent Energy Management and leakage control Configurable L1 caches Integrated L2 Cache Configurable size 0K - 1MB with programmable wait-states ECC error checking for fault-tolerance. 6

7 A Selection of Real Performance Points This part of the presentation will give real examples of the range of performance achievable. Signoff criteria need to be known to compare performance points Performance numbers are achievable with the stated design flow and all frequency values shown are worst case (Vdd-10%, SS, 125C) Criteria Include: OCV (10% inside WC and BC) Setup Margin (50ps) Well ties (where appropriate) Metal Fill Dense power grid Limited metal layer usage (65nm flows only) Holds fixed Minimal Routing Violations Unless stated, all physical IP available from ARM Flow generally tuned with Performance and Power Given Equal Weight 7

8 Implementation Flow Netlist Floorplan Constraints Std Cell Models IP/Block Models N2N Opt Placement tuned targets setplacemode timingdriven placedesign inplaceopt PreCTS Opt Optional: setoptmode usefulskew optdesign -prects Clock Synth clockdesign Reduce Clock Uncertainty PostCts Opt S.M.A.R.T. NR Optional: setoptmode usefulskew optdesign postcts [-ilm] Optional: optdesign postcts hold [-ilm] Wire Spreading for SI and Yield Concurrent MCV insertion for Yield postroute Opt Concurrently Optimize Timing/SI optdesign postroute setup -si optdesign postroute -hold si 8

9 TSMC 90G Synthesizable First fully synthesizable flow for the Cortex-A8 to be distributed by ARM. 700MHz, 1400DMIPS. Worst case: Includes all margins discussed earlier Used as baseline for following discussion Comments: TSMC 90G was chosen for comparitive reasons: First Optimized implementation of the Cortex-A8 was implemented in this process. This process is not amenable to wireless/ mobile due to hits higher leakage however, it is still a consideration for Consumer and Enterprise applications. 9

10 Use of Optimized techniques The Cortex-A8 processor was designed for synthesizable implementation. However, it was also partitioned so that partners could: Apply advanced circuit design and structured implementation techniques Improve performance, power and area Significantly reduce resource requirement compared to full-custom Along with synthesizable blocks, the Optimized implementation uses: Limited set of Custom array blocks Improve frequency and reduce power Structured datapath blocks Improve frequency, power and area. Advanced clocking (clock mesh) Improves frequency and power. 10

11 TSMC 65LP Synthesizable Fully synthesized implementation 500MHz, 1000DMIPS. Leakage Power < 0.5% of 90G Dynamic Power < 50% of 90G Implementation Targets Ideal for high-end mobile devices High-performance with Low-leakage Implementation geared towards low-power Methodology can be tuned to enable multiple voltage domains and added power savings Considerations: Always ON operation Key requirements: Extremely low stand-by power >100x lower than 90G Efficient high-performance Tradeoffs: Higher-dynamic power Higher Vdd (1.2V) Lower frequency Slower, less-leaky transistors Summary: Higher DMIPS/mW 11

12 TSMC 65GP Synthesizable (NVT) Fully synthesized implementation 800MHz+, DMIPS. Leakage Power > 50x of 65LP Dynamic power < 70% of 65LP Implementation Targets Ideal for high-end consumer or tethered devices High-performance with Low dynamic power Implementation geared towards performance Methodology tuned to achieve right performance/ cost (area/power) balance Considerations: Only ON when in use (battery) Tethered (no battery) Key requirements: High-end performance Lower dynamic power to reduce packaging cost Lower area cost Tradeoffs: Higher leakage power Summary: Low area and power cost 12

13 TSMC 65GP Synthesizable (LVT) Fully synthesized implementation Further Boost in performance over NVT implementation Leakage Power > 100% of 65LP Dynamic Power < 60% of 65LP Implementation Targets Ideal for tethered consumer and enterprise devices High-performance with Low dynamic power Implementation tuned for performance Methodology tuned to achieve maintain or increase performance while reducing area and dynamic power Considerations: Only ON when in use (battery) Tethered (no battery) Extra Performance Key requirements: High-end performance Lower dynamic power to reduce packaging cost Lower area cost Tradeoffs: Higher leakage power again Summary: Low area and power cost 13

14 Summary The Cortex-A8 has a range of implementation choices Optimized implementation techniques provide best performance, area and power Synthesized implementations can also provide a high level of performance while maintaining aggressive power goals. Depending on application, the choice of process and tuning of the methodology, can help the user achieve the ideal performance/cost tradeoff. 14