Addressing 7nm Arm DynamIQ Cluster Design Challenges Using the Cadence Digital Implementation Flow

Transcription

1 Addressing 7nm Arm DynamIQ Cluster Design Challenges Using the Cadence Digital Implementation Flow Shawn Hung Sr. Engineering Manager, Arm Jerry Chen Sr. AE Manager, Cadence Arm Tech Symposia 2017, Taipei

2 Agenda Arm DynamIQ introduction Arm-Cadence collaboration Cadence flow for 7nm DynamIQ Shared Unit (DSU) implementation 7nm DSU implementation best practices Floor-planning Placement Clock choices Handling crosstalk Signoff ECO for power/timing Wrap-up followed by Q&A 2

3 Arm DynamIQ Introduction

4 Arm DynamIQ design Multi-core redefined New single cluster design Greater flexibility, with or without big.little technology Redesigned memory subsystem Advanced compute capabilities 4

5 Arm Cortex-A75: New premium performance point Cortex -A75 Massive uplift for laptop-ready performance Massive uplift for laptop-ready performance Smartphone power profile Smartphone power profile AI for edge to cloud compute >50% more performance AI for edge to cloud compute compared to current devices Estimated device performance using SPECINT2006, final device results may vary Comparison using Cortex-A73 at 2.4GHz vs Cortex-A75 at 3GHz 5

6 Cortex-A55: Efficient performance redefined Cortex-A55 Breakthrough power efficiency Higher sustained performance More intelligent compute at the edge 2.5x higher power efficiency compared to current devices Comparison using Cortex-A53 in 28nm devices vs Cortex-A55 in 16nm devices 6

7 Uncompromised performance at the edge New DynamIQ big.little performance levels across all tiers High end Mid Entry level 4b+4L Laptop-ready compute performance 1b+7L 2x single-thread performance (vs. today s octacore) 4L Elevating your user experience 7 Example configurations shown

8 Arm-Cadence Collaboration

9 9 Arm and Cadence project collaboration Implementation Reference Methodology irm cmos32lp Cortex-A15 irm Samsung 20nm testchip Hardened Macro Testchip cmos32lp IBM 20nm testchip TSMC 28hpm Cortex-A7 irm TSMC 20nm Cortex-A15 testchip RAK Rapid Adoption Kit Cortex-A7 irm TSMC 28hpm GPU Mali-T604 irm TSMC 40lp Samsung 20nm testchip POP IP Dual-A9 TSMC 28hpm Cortex-A9 Hard macro TSMC 28hpm Seahawk Quad-A15 IBM Arm 14nm FinFET testchip Samsung A7 14nm FINFET Next-gen Mali Cortex- A53 irm TSMC 28hpm TSMC 16FF Cortex-A57 Cortex -A57 Mali T678 irm Armv8 tsmc28hpm Arm big.little + GPU Testchip Cortex-A15 R3 irm Update TSMC 28hpm Cortex -A53 TSMC 28hpm Cortex-A57 irm TSMC 28hpm Seahawk 2 Dual-A15 GF 28nm A12 CCN-504 irm CCN-504 irm Cortex-A12 irm TSMC 16FF Cortex- A53/A57 Next-gen System IP irm TSMC 28hpm Cortex-A17 irm Cortex-A15 LP irm TSMC 28hpm GF 28nm A17 Mali T720 irm Cortex-A57 irm refresh Cortex- M7 irm Arm and Cadence are successfully engaged in several joint projects Cortex-A72 irm TSMC 16FF Cortex-A53/A57 PPPA Push TSMC 16FF+ TSMC 40LP Mail- T880 Armv8 Arm big.little + GPU Testchip T860 Cortex GPU A53 Cortex- A72 CPU TSMC 16FF+ TSMC 16FF+ TSMC 16FF+ TSMC 16FFC Cortex-A35 RAK N10 Cortex- A Cortex-A73 RAK Mali-G71 RAK 2 MP1 A73 TSMC 16FFC High Performance Low Power Cortex-R52 RAK Cortex-M23 RAK Cortex-A75 RAK Mali-G72 RAK Cortex-A55 RAK TSMC 7nm DSU RAK Cortex-M33 RAK

10 Arm and Cadence collaboration Close collaboration with Arm IP and flow developers Early access to new Arm IP during RTL development cycle enables better understanding of EDA requirements Cadence tool and flow enhancements implemented in parallel with Arm IP Arm IP Updates Arm R&D Cadence Digital Design tools Investigations / experiments / tool enhancements Cadence R&D Tool & Flow updates Initial Arm IP Early collaboration ensures tool support in place 10

11 Cadence Implementation Flow Placement PostRoute Optimization RTL synthesis to gates (Cadence Genus ) Design RTL Timing-Aware Placement Scan Reordering Clock estimation (Early Clock Flow) PRECTS optimization POSTROUTE Setup Opt Skew Optimization Incremental POSTROUTE Opt POSTROUTE Hold Fixing Synthesis / Mapping Multibit Insertion Scan Insertion/Compression Netlist / ScanDEF Place and Route Setup (Cadence Innovus ) Floorplan Initialization MMMC Setup MultiBit Level Shifter Insertion Libraries DEF/Floorplan UPF SDC LEF files QRC tech Files + Additional Constraints - Bounds - Blockages - Route Guides - NDR - CTS constraints Clock Tree Synthesis CTS with Useful Skew Enabled Clock Tree Routing POSTCTS Setup Opt POSTCTS Hold Fixing Signal Routing Timing-aware Signal Routing Signoff Extraction (QRC) Multi-corner RC extraction Libraries LEF files Signoff Constraints (SDC) Netlist and DEF STA (Cadence Tempus ) - Multi corner - Multi mode - STA signoff settings - Graph Based STA - Path based STA on failing paths RC SPEF 11

12 Stylus Common User Interface Arm DSU project used the Stylus Common User Interface Common User Interface Streamline synthesis to signoff flow Script consistency across the whole digital flow Simple reuse of code & fewer files to maintain Uniform New GUI Across Tools Uniform Commands Across Tools Automated Flow and Metrics Faster debug with robust common reporting Common UI Easy to capture advanced flow recipes such as 7nm Uniform Database Access Uniform Reports and Logs Enables each designer to be more productive Common Initialization Commands Improved ease-of-use and designer productivity 12

13 7nm DSU Implementation Flow

14 TRIM TRIM Derate 7nm process changes On-chip variation requires more accuracy, SOCV Ideal derate OCV derate AOCV derate SOCV derate VIA pillars for highperformance designs Lower voltage needs accurate waveform for delay calculation PMOS off NMOS on, Output switching Vdd The output switch only at the tail of the input waveform Both transistors are off, Output floating Vtp Path depth Trim metal shapes needed for best routing density Significant RC differences across layer stack PMOS on NMOS off, Output no change Vtn Wire1 Wire2 Wire3 > 30X interconnect delay difference between layers 14

15 7nm Cadence flow Synthesis Early Physical Synthesis considering 7nm rules RTL Genus (Physical Synthesis) GigaPlace Placement No placement guides / regions Early clock flow Clock tree synthesis Non default rules for clock nets based on 7nm layer stack Cloning and merging of ICGs Signoff Complete 7nm timing signoff SOCV enabled Conformal (Formal Eq) Innovus (Implementation) GigaOpt (pre-cts) CCOpt (CTS) NanoRoute GigaOpt (post-route) Quantus (Signoff Extr) Tempus (Signoff STA) No manual latencies for RAMs or ICGs Routing Timing driven Aggressive wire spreading to control SI effects of long parallel wires Signoff ECO Integrated into Implementation flow Path based to avoid pessimism Focus on total power reduction 15 GDS

16 DSU MP8 configuration RTL Configuration 4x Cortex-A75 + 4x Cortex-A55 MP8 2MB L3 cache Asynchronous DVFS for cores AMBA ACE Bus Interface Accelerator Coherency Port, Peripheral Port Interface Cortex-A75 config: 64KB L1, 512KB L2, ECC/Parity present, Crypto Cortex-A55 config: 32KB L1, 256KB L2, ECC/Parity present, Crypto, NEON Target Frequency: 2.5 TT/1.0V/85C 4x Cortex-A75 4b+4L *Zoomed-in view of DSU layout 16 Example configuration

17 7nm DSU Implementation Best Practices

18 Floorplanning DSU in the SoC context In a typical SoC floorplan, the CPU cluster would occupy one corner of the die Need to consider SoC floorplan along with DSU Cores and DSU shaped to be efficient at the SoC level Some examples for a 2x Cortex-A75 + 4x Cortex-A55 configuration shown here 18 *Schematics with representative scaling

19 Example rectilinear floor plan results Floorplan details 2x Cortex-A75 + 4x Cortex-A55 No notches along die edges Ports accessible close to die center, with some flexibility to move Results Timing goals are met Exact same flow used for all floorplan trials No placement guides / additional tuning necessary *Zoomed-in view of DSU layout 19

20 7nm DSU floor planning and placement considerations RAM channels Use density screens to limit the cell density in core channels For typical RAM channels, use soft blockages to ensure long wires are buffered optimally Size the core channels to accommodate logic + routing DSU logic module placement Logic module placement follows DSU data path flow Placement guides / regions not found to be necessary SI and wire delay avoidance is critical in macro dominated floorplans, especially for 7nm *Zoomed-in view of DSU layout 20

21 Placement guides Historically designers used placement guides to improving timing closure Time-consuming, iterative, manual process, which may not converge Needs to be manually recreated for each floorplan revision Innovus Implementation System natively understands DSU data path flow No need for manual placement guides Generally user-defined placement guides make results worse 21

22 Clock latency planning DSU design uses a number of levels of architectural clock gates for achieving low power For optimal timing closure, pre-cts clock gate latency estimations should be applied to the architectural clock gates Manual latency estimation can be error prone and iterative Innovus early clock flow fully automates the latency calculation significantly improving accuracy Enables faster floorplan trials and design closure GigaPlace Latencies automatically generated CCOpt Clock tree synthesis implements latency Innovus (Implementation) GigaPlace GigaOpt (pre-cts) CCOpt (CTS) NanoRoute GigaOpt Optimization driven by accurate timing, improving QoR Early clock flow used for 7nm DSU implementation GigaOpt (post-route) 22

23 SI avoidance during initial placement Floorplan creates long thin channels between CPUs and DSU logic Std.cell snapshot in channel Need to control cell density in these channels to reduce SI effects Initial placement should consider SI timing effects Route segments 23

24 SI avoidance from initial placement - Results Results Cell density controlled Placer manages cell density in channels, so router can reduce signal integrity (SI) effects on long wires Enables optimal buffer placement Significantly improves final timing Std.cell snapshot in channel Reduced cell density in channel Post Route Timing Reference Cell density control in channels R2R; WNS/TNS/FEP /-6.393/ /-0.667/381 R2CG; WNS/TNS/FEP /-0.041/ /-0.108/50 All; WNS/TNS/FEP /-7.549/ /-0.854/445 Route segments Long wires aggressively spread to reduce SI 24

25 Routing over the L3 RAM macros For achieving optimal PPA, it is essential to ensure shortest possible paths to and from L3 RAM pins Routing to RAM pins needs to go across memory macros Rotate memory macros so pins on edge facing DSU logic paths Memory abstracts should not block upper metal layers Router needs to use upper metal layers across memory macros to avoid detours Long wire buffers should use channels between memory macros L3 RAM Inefficient routing & buffering around L3 RAMs DSU logic DSU logic Desired routing and buffering across L3 RAMs 25

26 Routing over the L3 RAM macros Innovus system automatically creates dense 7nm routes in M10 directly across SRAM macros Significantly reduces wire length on nets connecting to memory macros Results in optimal timing on L3 paths L3 RAMs M10 routes 26

27 Tempus ECO - Flow Final stage of implementation based on signoff-quality timing and extraction Path-based analysis (PBA) used to avoid any pessimism Power optimization timing aware, so no impact to timing closure Integrated into Innovus system, so easy to use without leaving implementation environment Tempus ECO flow used during 7nm DSU implementation Innovus (Implementation) GigaPlace GigaOpt (pre-cts) CCOpt (CTS) NanoRoute GigaOpt (post-route) Tempus-ECO Quantus (Signoff Extr) Tempus (Signoff STA) 27

28 % of cells Tempus ECO 7nm DSU results During implementation a few VT/CL cell classes enabled High-performance timing closure is the focus during implementation, so not all VT classes required As part of Tempus ECO flow, all VT/CL cell classes are allowed 120% 100% 80% 60% 40% 20% 0% Cell Type Cell VT Class Percentage Reduced VT Leakage *TUL_C8* *TUL_C11* *TL_C8* *TL_C11* *TS_C8* *TS_C11* Usage (Before ECO) Usage (After ECO) Normalized Leakage Power Enables Tempus ECO to reclaim significant power without any impact to critical timing paths 95% reduction in leakage power Sequential Cell Type Combinational Before Tempus ECO After Tempus ECO 28

29 Summary 7nm DSU design easily achieves 2.5GHz target frequency Frequency could be increased if necessary for SoC requirements Placement and optimization need to understand floorplan channels between CPUs and cache memories to manage SI Innovus early CTS used to automatically estimate Architectural clock gate latency pre-cts Tempus ECO used to improve final leakage power Innovus (Implementation) RTL Genus (Physical Synthesis) GigaPlace GigaOpt (pre-cts) CCOpt (CTS) NanoRoute GigaOpt (post-route) Tempus ECO Tempus (Signoff STA) Physical synthesis based on 7nm rules Channel aware placement Clock latencies automatically generated Aggressive wire spreading to reduce SI Tempus ECO sign off driven timing and power closure 29 GDS

30 Thank You! Danke! Merci! 謝謝! ありがとう! Gracias! Kiitos! 감사합니다 धन यव द 30

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