ECE/Comp. Sci. 352 { Digital System Fundamentals

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Alexander Johnson
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1 epartment of Electrical and Computer Engineering University of Wisconsin - Madison Final uggested olution ECE/Comp. ci. 352 { igital ystem Fundamentals. (25 points) hort Questions (a)(5points) Convert (3:) 2 into a decimal number. ound to the hundredth digit. nswer: 46:92 (b) (5 points) dd the two hexadecimal numbers leave the result in hexadecimal, of course. 9876h 5432h 597h nswer: 597h (c)(5 points) Mark each oolean identity which is incorrect in the table below, and give ONE counter example on its right to illustrate that it is wrong. If it is correct, leave it alone. Mark oolean Identities X + = C + C + = + Counter example: Let =, and =. Then + = + =6=. (d) (5 points) Express the following oolean function in product-of-mxtem canonical form. olution: Use Karnaugh map, we have: f(w x y z) =y(xz + z) +wx(y + yz) +xyz = Q ( ) (e) (5 points) Express F in minimal sum-of-products form. F C nswer: F = + C 2. ( points) Carry Look-head dder s a compromise between hardware cost and speed a four-bit parallel adder is designed such that the carry-out of the fourth bit C 4 is implemented with a two-level sum-of-products

2 function of G 3, P 3, G 2, P 2, G, P,andG, P as well as carry-in C. The remaining carries C 3, C 2, and C are generated using conventional carry propagation (C i+ = G i + P i C i ). lso recall that G i = i i, P i = i i,and i =( i i ) C i. (a)(5points) Write C 4 in sum-of-products form. (b) (5 points) ssuming that N, O, NOT, as well as XO gates all introduce unit propagation delay. lso, assume that all the inputs f i i i 5g and C are made available simultaneously at time. 3. (5 points) ynchronous equential Circuit Maximum gate delay when C 4 is stablized is: 3 Maximum gate delay when s 3 is stablized is: 7 two-bit counter has two control lines s s. Its function is described in the table below. Two positive edge triggered ip-ops and are used to implement this counter. is the most signicant bit of a count. s s Function unchanged count up count down clear (synchronous) (a) (5 points) ketch the state diagram. Label each state with (t)(t) = respectively. (b)(5points) Carefully draw the waveforms for and for the given initial values and control signals. how ip-op propagation delay (/6 th of an inch orso). clock s s (c) (5 points) Flip-op is a JK-ip-op is a -ip-op. erive input equations for the two ip-ops. J = K = = 4. (5 points) More hort ubjects

3 (a) (8 points) system is to perform the following register transfers in response to the control variables shown. K a : 2 K b : 2 3 K c : 3 2 K d : 4 Each of the four registers has bidirectional input-output lines with load and three-state output Enable controls. These registers are connected to the bus as shown below. Write oolean expressions for all control signals to all registers so that the above four register transfer operations are realized. olution: Connections to the load control of each registers, 2, 3 and 4 are, respectively, K a, K b, K c,andk d. Connections to the Enable signals to each registers are: K d to Enable, K a + K c to 2 Enable, K b to 3 Enable, and to 4 Enable. (b) (7 points) computer has a 64-bit word length with 64-bit instruction format. It contains 4 bits OP code, 3 register elds with bits each, and a 2 bit immediate operand eld. In the following three questions, you may leave your answer in exponential form (e.g. 2 3 ). nswer: The maximum number of operations that can be specied is: 2 4 The maximum number of registers can be addressed is: 2 The largest algebraic value of signed 2's complement binary number that can be accommodated as an immediate operand is 2 9 ; 5. ( point) M Chart esign s G X s2 s Y Y

4 G X Y are input or output oolean variables in the M chart on the facing page. raw the logic diagram of a one ip-op per state implementation of this M chart. Only NN gates and inverters are available in addition to the ip-ops shown. n active-low input EET must asynchronously force the FM to state s. 6. (5 points) ingle-cycle Computer efer to the single cycle computer documented on the facing page. (a)(5 points) Complete the following table to determine the opcode of the shift-right instruction shown. Instruction egister Transfer F M M W MW Opcode [] sr[] (b) ( points) imulate the single cycle computer for the rst two of the instructions shown in the table below. IM[PC] is the contents of the Instruction Memory at the address held by the PC register shown in binary for your convenience. ll register entries are in hexadecimal all results should be in hexadecimal. Each line represent one clock cycle. Micro-operation IM[PC] [] [] [2] [3] ( points) Multi-Cycle Microprogrammed Computer Instruction (add and shift-right) for the micro-programmed computer documented on the facing page performs the operation [] sr[[]+[]] erive the symbolic microprogram for this instruction starting at microprogram control memory address. You may not need all of the rows provided in the table below. If a eld in a microinstruction is not signicant place a dash in its box. The execution of this instruction will be at consecutive address in the control memory starting from as labeled in the table below. The address for instruction fetch microinstruction is IF. Use the temporary register 8 to store intermediate result. To save space, the following abbreviations may be used:

5 T, T, T { the entries may be either 8 or,, respectively. PI { I (increment), N(nochange) IL { L (load), N (no load) M { the entries may be F (function unit) or (ata) W, MW { W (write), or NW (do not write) MM { PC (program counter), M (memory address from bus ) Other symbols refer to tables 8-9 and 8- in the back of the cover page. ddr. NXT M MC IL PI T T T M F M W MM MW NXT NX N N 8 F=+ F W { NW IF NXT NX N N 8 { { F=sr F W { NW or if we assume = + in the control memory, wemayalsousecnt in the M eld: ddr. NXT M MC IL PI T T T M F M W MM MW { CNT { N N 8 F=+ F W { NW IF NXT NX N N 8 { { F=sr F W { NW

Real Digital Problem Set #6

Real Digital Problem Set #6 Real igital Problem et #6. (2 points) ketch a block diagram for a magnitude comparator bit-slice circuit. Create K-maps to define the bit-slice circuit, and use them to find optimal logic equations. ketch