Chapter 5: Tasks, Functions, and UDPs
|
|
|
- Cuthbert Clyde Stevenson
- 6 years ago
- Views:
Transcription
1 Chapter 5: Tasks, Functions, and UDPs Prof. Ming-Bo Lin Department of Electronic Engineering National Taiwan University of Science and Technology Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 5-1
2 Syllabus Objectives Tasks Functions Combinational UDPs Sequential UDPs Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 5-2
3 Objectives After completing this chapter, you will be able to: Describe the features of tasks and functions Describe how to use tasks and functions Describe the features of dynamic tasks and functions Describe the features of UDPs (user-defined primitives) Describe how to use combinational and sequential UDPs Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 5-3
4 Syllabus Objectives Tasks Definition and call Types of tasks Functions Combinational UDPs Sequential UDPs Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 5-4
5 Task Definition and Calls task [automatic] task_identifier(task_port_list); endtask // port list style task [automatic] task_identifier; [declarations] // include arguments procedural_statement endtask // port list declaration style task [automatic] task_identifier ([argument_declarations]); [other_declarations] // exclude arguments procedural_statement endtask Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 5-5
6 A Task Example // count the zeros in a byte module zero_count_task (data, out); input [7:0] data; output reg [3:0] out; count_0s_in_byte(data, out); // task declaration from here task count_0s_in_byte(input [7:0] data, output reg [3:0] count); integer i; begin // task body count = 0; for (i = 0; i <= 7; i = i + 1) if (data[i] == 0) count= count + 1; end endtask endmodule Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 5-6
7 Syllabus Objectives Tasks Definition and call Types of tasks Functions Combinational UDPs Sequential UDPs Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 5-7
8 Types of Tasks (static) task task endtask automatic (reentrant, dynamic) task task automatic endtask Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 5-8
9 A Dynamic Task Example Chapter 5: Tasks, Functions, and UDPs // task definition starts from here task automatic check_counter; reg [3:0] count; // the body of the task begin $display ($realtime,,"at the beginning of task, count = %d", count); if (reset) begin count = 0; $display ($realtime,,"after reset, count = %d", count); end endmodule Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 5-9
10 Syllabus Objectives Tasks Functions Definition and call Types of functions Combinational UDPs Sequential UDPs Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 5-10
11 Function Definition and Calls Chapter 5: Tasks, Functions, and UDPs function [automatic] [signed] [range_of_type] endfunction // port list style function [automatic] [signed] [range_or_type] function_identifier; input_declaration other_declarations procedural_statement endfunction // port list declaration style function [automatic] [signed] [range_or_type] function_identifier (input_declarations); other_declarations procedural_statement endfunction Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 5-11
12 A Function Example // count the zeros in a byte module zero_count_function (data, out); input [7:0] data; output reg [3:0] out; out = count_0s_in_byte(data); // function declaration from here. function [3:0] count_0s_in_byte(input [7:0] data); integer i; begin count_0s_in_byte = 0; for (i = 0; i <= 7; i = i + 1) if (data[i] == 0) count_0s_in_byte = count_0s_in_byte + 1; end endfunction endmodule Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 5-12
13 Syllabus Objectives Tasks Functions Definition and call Types of functions Combinational UDPs Sequential UDPs Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 5-13
14 Types of Functions (static) function function endfunction automatic (recursive, dynamic) function function automatic endfunction Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 5-14
15 Automatic (Recursive) Functions Chapter 5: Tasks, Functions, and UDPs // the use of reentrant function module factorial(input [7:0] n, output [15:0] result); // instantiate the fact function assign result = fact(7); // define fact function function automatic [15:0] fact; input [7:0] N; // the body of function if (N == 1) fact = 1; else fact = N * fact(n - 1); endfunction endmodule Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 5-15
16 Constant Functions module RAM (addr_bus, data_bus); parameter RAM_depth = 1024; input [count_log_b2(ram_depth)-1:0] addr_bus; output reg [7:0] data_bus; // function declaration from here function integer count_log_b2(input integer depth); begin // function body count_log_b2 = 0; while (depth) begin count_log_b2 = count_log_b2 + 1; depth = depth >> 1; end end endfunction endmodule Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 5-16
17 Syllabus Objectives Tasks Functions Combinational UDPs Definition Instantiation Sequential UDPs Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 5-17
18 Definition of Combinational UDPs Chapter 5: Tasks, Functions, and UDPs // port list style primitive udp_name(output_port, input_ports); output output_port; input input_ports; // UDP state table table // the state table starts from here <table rows> endtable endprimitive Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 5-18
19 Definition of Combinational UDPs State table entries <input1><input2> <inputn>:<output>; Chapter 5: Tasks, Functions, and UDPs The <input#> values must be in the same order as in the input list Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 5-19
20 A Primitive UDP --- An AND Gate primitive udp_and (out, a, b); output out; input a, b; table // a b : out; 0 0 : 0; 0 1 : 0; 1 0 : 0; 1 1 : 1; endtable endprimitive Chapter 5: Tasks, Functions, and UDPs Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 5-20
21 Another UDP Example primitive prog253 (output f, input x, y, z); table // truth table for f(x, y, z,) = ~(~(x y) ~x & z); // x y z : f : 0; : 0; : 1; : 0; : 1; : 1; : 1; : 1; endtable endprimitive x y z g2 a g1 g3 b c g4 f Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 5-21
22 Shorthand Notation for Don t Cares Chapter 5: Tasks, Functions, and UDPs primitive udp_and(f, a, b); output f; input a, b; table // a b : f; 1 1 : 1; 0? : 0;? 0 : 0; //? expanded to 0, 1, x endtable endprimitive Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 5-22
23 Syllabus Objectives Tasks Functions Combinational UDPs Definition Instantiation Sequential UDPs Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 5-23
24 Instantiation of Combinational UDPs Chapter 5: Tasks, Functions, and UDPs // instantiations of UDPs module UDP_full_adder(sum, cout, x, y, cin); output sum, cout; input x, y, cin; wire s1, c1, c2; // instantiate udp primitives udp_xor (s1, x, y); udp_and (c1, x, y); udp_xor (sum, s1, cin); udp_and (c2, s1, cin); udp_or (cout, c1, c2); endmodule Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 5-24
25 Syllabus Objectives Tasks Functions Combinational UDPs Sequential UDPs Definition Instantiation Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 5-25
26 Definition of Sequential UDPs Chapter 5: Tasks, Functions, and UDPs // port list style primitive udp_name(output_port, input_ports); output output_port; input input_ports; reg output_port; // unique for sequential UDP initial output-port = expression; // optional for sequential UDP // UDP state table table // keyword to start the state table <table rows> endtable endprimitive Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 5-26
27 Definition of Sequential UDPs State table entries Chapter 5: Tasks, Functions, and UDPs <input1><input2> <inputn>:<current_state>:<next_state>; The output is always declared as a reg An initial statement can be used to initialize output Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 5-27
28 Level-Sensitive Sequential UDPs Chapter 5: Tasks, Functions, and UDPs // define a level-sensitive latch using UDP primitive d_latch(q, d, gate, clear); output q; input d, gate, clear; reg q; initial q = 0; // initialize output q table // d gate clear : q : q+;?? 1 :? : 0 ; // clear :? : 1 ; // latch q = :? : 0 ; // latch q = 0? 0 0 :? : - ; // no change endtable endprimitive Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 5-28
29 Edge-Sensitive Sequential UDPs Chapter 5: Tasks, Functions, and UDPs // define a positive-edge triggered T-type flip-flop using UDP primitive T_FF(q, clk, clear); output q; input clk, clear; reg q; // define the behavior of edge-triggered T_FF table // clk clear : q : q+;? 1 :? : 0 ; // asynchronous clear? (10) :? : - ; // ignore negative edge of clear (01) 0 : 1 : 0 ; // toggle at positive edge (01) 0 : 0 : 1 ; // of clk (1?) 0 :? : - ; // ignore negative edge of clk endtable endprimitive Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 5-29
30 Shorthand Symbols for Using in UDPs Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 5-30
31 Syllabus Objectives Tasks Functions Combinational UDPs Sequential UDPs Definition Instantiation Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 5-31
32 Instantiation of UDPs // an example of sequential UDP instantiations module ripple_counter(clock, clear, q); input clock, clear; output [3:0] q; // instantiate the T_FFs. T_FF tff0(q[0], clock, clear); T_FF tff1(q[1], q[0], clear); T_FF tff2(q[2], q[1], clear); T_FF tff3(q[3], q[2], clear); endmodule Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 5-32
Course Topics - Outline
Course Topics - Outline Lecture 1 - Introduction Lecture 2 - Lexical conventions Lecture 3 - Data types Lecture 4 - Operators Lecture 5 - Behavioral modeling A Lecture 6 Behavioral modeling B Lecture 7
Chapter 9: Sequential Logic Modules
Chapter 9: Sequential Logic Modules Prof. Ming-Bo Lin Department of Electronic Engineering National Taiwan University of Science and Technology Digital System Designs and Practices Using Verilog HDL and
The Verilog Language COMS W Prof. Stephen A. Edwards Fall 2002 Columbia University Department of Computer Science
The Verilog Language COMS W4995-02 Prof. Stephen A. Edwards Fall 2002 Columbia University Department of Computer Science The Verilog Language Originally a modeling language for a very efficient event-driven
Chapter 2a: Structural Modeling
Chapter 2a: Structural Modeling Prof. Ming-Bo Lin Department of Electronic Engineering National Taiwan University of Science and Technology Digital System Designs and Practices Using Verilog HDL and FPGAs
Verilog Behavioral Modeling
Verilog Behavioral Modeling Lan-Da Van ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Spring, 2017 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Source:
Hardware Description Languages (HDLs) Verilog
Hardware Description Languages (HDLs) Verilog Material from Mano & Ciletti book By Kurtulus KULLU Ankara University What are HDLs? A Hardware Description Language resembles a programming language specifically
EECS150 - Digital Design Lecture 10 Logic Synthesis
EECS150 - Digital Design Lecture 10 Logic Synthesis September 26, 2002 John Wawrzynek Fall 2002 EECS150 Lec10-synthesis Page 1 Logic Synthesis Verilog and VHDL stated out as simulation languages, but quickly
EECS150 - Digital Design Lecture 10 Logic Synthesis
EECS150 - Digital Design Lecture 10 Logic Synthesis February 13, 2003 John Wawrzynek Spring 2003 EECS150 Lec8-synthesis Page 1 Logic Synthesis Verilog and VHDL started out as simulation languages, but
Laboratory Exercise 3
Laboratory Exercise 3 Latches, Flip-flops, and egisters The purpose of this exercise is to investigate latches, flip-flops, and registers. Part I Altera FPGAs include flip-flops that are available for
Verilog Tutorial (Structure, Test)
Digital Circuit Design and Language Verilog Tutorial (Structure, Test) Chang, Ik Joon Kyunghee University Hierarchical Design Top-down Design Methodology Bottom-up Design Methodology Module START Example)
ECE 4514 Digital Design II. Spring Lecture 2: Hierarchical Design
ECE 4514 Digital Design II Spring 2007 Abstraction in Hardware Design Remember from last lecture that HDLs offer a textual description of a netlist. Through abstraction in the HDL, we can capture more
EEL 4783: HDL in Digital System Design
EEL 4783: HDL in Digital System Design Lecture 15: Logic Synthesis with Verilog Prof. Mingjie Lin 1 Verilog Synthesis Synthesis vs. Compilation Descriptions mapped to hardware Verilog design patterns for
CSE140L: Components and Design Techniques for Digital Systems Lab
CSE140L: Components and Design Techniques for Digital Systems Lab Tajana Simunic Rosing Source: Vahid, Katz, Culler 1 Announcements & Outline Lab 4 due; demo signup times listed on the cse140l site Check
CSE140L: Components and Design
CSE140L: Components and Design Techniques for Digital Systems Lab Tajana Simunic Rosing Source: Vahid, Katz, Culler 1 Grade distribution: 70% Labs 35% Lab 4 30% Lab 3 20% Lab 2 15% Lab 1 30% Final exam
EPC6055 Digital Integrated Circuits EXAM 1 Fall Semester 2013
EPC6055 Digital Integrated Circuits EXAM 1 Fall Semester 2013 Print Here Student ID Signature This is a closed book exam. The exam is to be completed in one-hundred ten (110) minutes. Don t use scratch
Chap 6 Introduction to HDL (d)
Design with Verilog Chap 6 Introduction to HDL (d) Credit to: MD Rizal Othman Faculty of Electrical & Electronics Engineering Universiti Malaysia Pahang Ext: 6036 VERILOG HDL Basic Unit A module Module
Chapter 10: Design Options of Digital Systems
Chapter 10: Design Options of Digital Systems Prof. Ming-Bo Lin Department of Electronic Engineering National Taiwan University of Science and Technology Digital System Designs and Practices Using Verilog
Introduction to Verilog design. Design flow (from the book)
Introduction to Verilog design Lecture 2 ECE 156A 1 Design flow (from the book) ECE 156A 2 1 Hierarchical Design Chip Modules Cells Primitives A chip contain many modules A module may contain other modules
Topics. Midterm Finish Chapter 7
Lecture 9 Topics Midterm Finish Chapter 7 Xilinx FPGAs Chapter 7 Spartan 3E Architecture Source: Spartan-3E FPGA Family Datasheet CLB Configurable Logic Blocks Each CLB contains four slices Each slice
Logic Synthesis. EECS150 - Digital Design Lecture 6 - Synthesis
Logic Synthesis Verilog and VHDL started out as simulation languages, but quickly people wrote programs to automatically convert Verilog code into low-level circuit descriptions (netlists). EECS150 - Digital
Chapter 6: Hierarchical Structural Modeling
Chapter 6: Hierarchical Structural Modeling Prof. Soo-Ik Chae Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 6-1 Objectives After completing this chapter, you will
FPGA: FIELD PROGRAMMABLE GATE ARRAY Verilog: a hardware description language. Reference: [1]
![FPGA: FIELD PROGRAMMABLE GATE ARRAY Verilog: a hardware description language. Reference: [1]](/thumbs/80/81661285.jpg "FPGA: FIELD PROGRAMMABLE GATE ARRAY Verilog: a hardware description language. Reference: [1]")
FPGA: FIELD PROGRAMMABLE GATE ARRAY Verilog: a hardware description language Reference: [] FIELD PROGRAMMABLE GATE ARRAY FPGA is a hardware logic device that is programmable Logic functions may be programmed
Introduction to Digital Design with Verilog HDL
Introduction to Digital Design with Verilog HDL Modeling Styles 1 Levels of Abstraction n Behavioral The highest level of abstraction provided by Verilog HDL. A module is implemented in terms of the desired
Module 2.1 Gate-Level/Structural Modeling. UNIT 2: Modeling in Verilog
Module 2.1 Gate-Level/Structural Modeling UNIT 2: Modeling in Verilog Module in Verilog A module definition always begins with the keyword module. The module name, port list, port declarations, and optional
Synthesis vs. Compilation Descriptions mapped to hardware Verilog design patterns for best synthesis. Spring 2007 Lec #8 -- HW Synthesis 1
Verilog Synthesis Synthesis vs. Compilation Descriptions mapped to hardware Verilog design patterns for best synthesis Spring 2007 Lec #8 -- HW Synthesis 1 Logic Synthesis Verilog and VHDL started out
Introduction to Verilog design. Design flow (from the book) Hierarchical Design. Lecture 2
Introduction to Verilog design Lecture 2 ECE 156A 1 Design flow (from the book) ECE 156A 2 Hierarchical Design Chip Modules Cells Primitives A chip contain many modules A module may contain other modules
EECS 427 Lecture 14: Verilog HDL Reading: Many handouts/references. EECS 427 W07 Lecture 14 1
EECS 427 Lecture 14: Verilog HDL Reading: Many handouts/references EECS 427 W07 Lecture 14 1 Online Verilog Resources ASICs the book, Ch. 11: http://www.ge.infn.it/~pratolo/verilog/verilogtutorial.pdf
Hardware Description Language (HDL)
Hardware Description Language (HDL) What is the need for Hardware Description Language? Model, Represent, And Simulate Digital Hardware Hardware Concurrency Parallel Activity Flow Semantics for Signal
FPGA Design Challenge :Techkriti 14 Digital Design using Verilog Part 1
FPGA Design Challenge :Techkriti 14 Digital Design using Verilog Part 1 Anurag Dwivedi Digital Design : Bottom Up Approach Basic Block - Gates Digital Design : Bottom Up Approach Gates -> Flip Flops Digital
Nikhil Gupta. FPGA Challenge Takneek 2012
Nikhil Gupta FPGA Challenge Takneek 2012 RECAP FPGA Field Programmable Gate Array Matrix of logic gates Can be configured in any way by the user Codes for FPGA are executed in parallel Configured using
Chapter 9: Sequential Logic Modules
Chapter 9: Sequential Logic Modules Prof. Soo-Ik Chae Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 9-1 Objectives After completing this chapter, you will be able
N-input EX-NOR gate. N-output inverter. N-input NOR gate
Hardware Description Language HDL Introduction HDL is a hardware description language used to design and document electronic systems. HDL allows designers to design at various levels of abstraction. It
Advanced Digital Design with the Verilog HDL
Copyright 2001, 2003 MD Ciletti 1 Advanced Digital Design with the Verilog HDL M. D. Ciletti Department of Electrical and Computer Engineering University of Colorado Colorado Springs, Colorado ciletti@vlsic.uccs.edu
Verilog. What is Verilog? VHDL vs. Verilog. Hardware description language: Two major languages. Many EDA tools support HDL-based design
Verilog What is Verilog? Hardware description language: Are used to describe digital system in text form Used for modeling, simulation, design Two major languages Verilog (IEEE 1364), latest version is
Federal Urdu University of Arts, Science and Technology, Islamabad VLSI SYSTEM DESIGN. Prepared By: Engr. Yousaf Hameed.
VLSI SYSTEM DESIGN Prepared By: Engr. Yousaf Hameed Lab Engineer BASIC ELECTRICAL & DIGITAL SYSTEMS LAB DEPARTMENT OF ELECTRICAL ENGINEERING VLSI System Design 1 LAB 01 Schematic Introduction to DSCH and
Verilog HDL Introduction
EEE3050 Theory on Computer Architectures (Spring 2017) Prof. Jinkyu Jeong Verilog HDL Introduction 2017.05.14 TA 이규선 (GYUSUN LEE) / 안민우 (MINWOO AHN) Modules The Module Concept Basic design unit Modules
ECE 2300 Digital Logic & Computer Organization. More Sequential Logic Verilog
ECE 2300 Digital Logic & Computer Organization Spring 2018 More Sequential Logic Verilog Lecture 7: 1 Announcements HW3 will be posted tonight Prelim 1 Thursday March 1, in class Coverage: Lectures 1~7
Behavioral Modeling and Timing Constraints
Lab Workbook Introduction Behavioral modeling was introduced in Lab 1 as one of three widely used modeling styles. Additional capabilities with respect to testbenches were further introduced in Lab 4.
Chap 3. Modeling structure & basic concept of Verilog HDL
Chap 3. Modeling structure & basic concept of Verilog HDL Fall semester, 2016 Prof. Jaeseok Kim School of Electrical & Electronics Eng. Yonsei university jaekim@yonsei.ac.kr Digital System Design 3-1 Chapter
Verilog HDL. Gate-Level Modeling
Verilog HDL Verilog is a concurrent programming language unlike C, which is sequential in nature. block - executes once at time 0. If there is more then one block, each execute concurrently always block
Computer Aided Design Basic Syntax Gate Level Modeling Behavioral Modeling. Verilog
Verilog Radek Pelánek and Šimon Řeřucha Contents 1 Computer Aided Design 2 Basic Syntax 3 Gate Level Modeling 4 Behavioral Modeling Computer Aided Design Hardware Description Languages (HDL) Verilog C
Programmable Logic Devices Verilog VII CMPE 415
Synthesis of Combinational Logic In theory, synthesis tools automatically create an optimal gate-level realization of a design from a high level HDL description. In reality, the results depend on the skill
Lecture 7. Standard ICs FPGA (Field Programmable Gate Array) VHDL (Very-high-speed integrated circuits. Hardware Description Language)
Standard ICs FPGA (Field Programmable Gate Array) VHDL (Very-high-speed integrated circuits Hardware Description Language) 1 Standard ICs PLD: Programmable Logic Device CPLD: Complex PLD FPGA: Field Programmable
Online Verilog Resources
EECS 427 Discussion 6: Verilog HDL Reading: Many references EECS 427 F08 Discussion 6 1 Online Verilog Resources ASICs the book, Ch. 11: http://www.ge.infn.it/~pratolo/verilog/verilogtutorial.pdf it/ pratolo/verilog/verilogtutorial
P-1/26. Samir Palnitkar. Prentice-Hall, Inc. INSTRUCTOR : CHING-LUNG SU.
: P-1/26 Textbook: Verilog HDL 2 nd. Edition Samir Palnitkar Prentice-Hall, Inc. : INSTRUCTOR : CHING-LUNG SU E-mail: kevinsu@yuntech.edu.tw Chapter 4 P-2/26 Chapter 4 Modules and Outline of Chapter 4
Under-Graduate Project Logic Design with Behavioral Models
97-1 1 Under-Graduate Project Logic Design with Behavioral Models Speaker: 吳佳謙 Adviser: Prof. An-Yeu Wu Date: 2008/10/20 ACCESS IC LAB Operation Assignment Outline Blocking and non-blocking Appendix pp.
A Tutorial Introduction 1
Preface From the Old to the New Acknowledgments xv xvii xxi 1 Verilog A Tutorial Introduction 1 Getting Started A Structural Description Simulating the binarytoeseg Driver Creating Ports For the Module
RIZALAFANDE CHE ISMAIL TKT. 3, BLOK A, PPK MIKRO-e KOMPLEKS PENGAJIAN KUKUM. SYNTHESIS OF COMBINATIONAL LOGIC (Chapter 8)
RIZALAFANDE CHE ISMAIL TKT. 3, BLOK A, PPK MIKRO-e KOMPLEKS PENGAJIAN KUKUM SYNTHESIS OF COMBINATIONAL LOGIC (Chapter 8) HDL-BASED SYNTHESIS Modern ASIC design use HDL together with synthesis tool to create
Behavioral Modeling and Timing Constraints
Introduction Behavioral modeling was introduced in Lab 1 as one of three widely used modeling styles. Additional capabilities with respect to testbenches were further introduced in Lab 4. However, there
Verilog Fundamentals. Shubham Singh. Junior Undergrad. Electrical Engineering
Verilog Fundamentals Shubham Singh Junior Undergrad. Electrical Engineering VERILOG FUNDAMENTALS HDLs HISTORY HOW FPGA & VERILOG ARE RELATED CODING IN VERILOG HDLs HISTORY HDL HARDWARE DESCRIPTION LANGUAGE
14. Introducton to Verilog
14. Introducton to Verilog Jacob Abraham Department of Electrical and Computer Engineering The University of Texas at Austin VLSI Design Fall 2017 October 23, 2017 ECE Department, University of Texas at
VERILOG: FLIP-FLOPS AND REGISTERS
VERILOG: FLIP-FLOPS AND REGISTERS Semiconductor Memories Single-bit or Memory (Foreground) Individual memory circuits that store a single bit of information and have at least a 1) data input, 2) data output,
EECS150, Fall 2004, Midterm 1, Prof. Culler. Problem 1 (15 points) 1.a. Circle the gate-level circuits that DO NOT implement a Boolean AND function.
Problem 1 (15 points) 1.a. Circle the gate-level circuits that DO NOT implement a Boolean AND function. 1.b. Show that a 2-to-1 MUX is universal (i.e. that any Boolean expression can be implemented with
EECS150 - Digital Design Lecture 5 - Verilog Logic Synthesis
EECS150 - Digital Design Lecture 5 - Verilog Logic Synthesis Jan 31, 2012 John Wawrzynek Spring 2012 EECS150 - Lec05-verilog_synth Page 1 Outline Quick review of essentials of state elements Finite State
ECEN 468 Advanced Logic Design
ECEN 468 Advanced Logic Design Lecture 28: Synthesis of Language Constructs Synthesis of Nets v An explicitly declared net may be eliminated in synthesis v Primary input and output (ports) are always retained
VERILOG. Deepjyoti Borah, Diwahar Jawahar
VERILOG Deepjyoti Borah, Diwahar Jawahar Outline 1. Motivation 2. Basic Syntax 3. Sequential and Parallel Blocks 4. Conditions and Loops in Verilog 5. Procedural Assignment 6. Timing controls 7. Combinatorial
Verilog Tutorial. Verilog Fundamentals. Originally designers used manual translation + bread boards for verification
Verilog Fundamentals Verilog Tutorial History Data types Structural Verilog Functional Verilog Adapted from Krste Asanovic Originally designers used manual translation + bread boards for verification Hardware
Verilog Tutorial 9/28/2015. Verilog Fundamentals. Originally designers used manual translation + bread boards for verification
Verilog Fundamentals Verilog Tutorial History Data types Structural Verilog Functional Verilog Adapted from Krste Asanovic Originally designers used manual translation + bread boards for verification Hardware
Verilog 1 - Fundamentals
Verilog 1 - Fundamentals FA FA FA FA module adder( input [3:0] A, B, output cout, output [3:0] S ); wire c0, c1, c2; FA fa0( A[0], B[0], 1 b0, c0, S[0] ); FA fa1( A[1], B[1], c0, c1, S[1] ); FA fa2( A[2],
HDL Introduction and Reuse
Verilog HDL Introduction and Reuse P. Bakowski bako@ieee.org Verilog HDL Verilog IEEE 13641 1995 95 P. Bakowski 2 Verilog HDL Verilog IEEE 13641 Verilog AMS 1995 95 1998 P. Bakowski 3 Verilog HDL Verilog
Synthesizable Verilog
Synthesizable Verilog Courtesy of Dr. Edwards@Columbia, and Dr. Franzon@NCSU http://csce.uark.edu +1 (479) 575-6043 yrpeng@uark.edu Design Methodology Structure and Function (Behavior) of a Design HDL
Introduction To HDL. Verilog HDL. Debdeep Mukhopadhyay Dept of CSE, IIT Madras 1
Introduction To HDL Verilog HDL Debdeep Mukhopadhyay debdeep@cse.iitm.ernet.in Dept of CSE, IIT Madras 1 How it started! Gateway Design Automation Cadence purchased Gateway in 1989. Verilog was placed
ECE 551: Digital System *
ECE 551: Digital System * Design & Synthesis Lecture Set 5 5.1: Verilog Behavioral Model for Finite State Machines (FSMs) 5.2: Verilog Simulation I/O and 2001 Standard (In Separate File) 3/4/2003 1 Explicit
Synthesis of Combinational and Sequential Circuits with Verilog
Synthesis of Combinational and Sequential Circuits with Verilog What is Verilog? Hardware description language: Are used to describe digital system in text form Used for modeling, simulation, design Two
EN2911X: Reconfigurable Computing Topic 02: Hardware Definition Languages
EN2911X: Reconfigurable Computing Topic 02: Hardware Definition Languages Professor Sherief Reda http://scale.engin.brown.edu School of Engineering Brown University Spring 2014 1 Introduction to Verilog
Chapter 5 Registers & Counters
University of Wisconsin - Madison ECE/Comp Sci 352 Digital Systems Fundamentals Kewal K. Saluja and Yu Hen Hu Spring 2002 Chapter 5 Registers & Counters Originals by: Charles R. Kime Modified for course
Finite-State Machine (FSM) Design
1 Finite-State Machine (FSM) Design FSMs, an important category of sequential circuits, are used frequently in designing digital systems. From the daily used electronic machines to the complex digital
Chapter 3: Dataflow Modeling
Chapter 3: Dataflow Modeling Prof. Soo-Ik Chae Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 3-1 Objectives After completing this chapter, you will be able to: Describe
Verilog for High Performance
Verilog for High Performance Course Description This course provides all necessary theoretical and practical know-how to write synthesizable HDL code through Verilog standard language. The course goes
CSCB58 - Lab 3. Prelab /3 Part I (in-lab) /2 Part II (in-lab) /2 TOTAL /8
CSCB58 - Lab 3 Latches, Flip-flops, and Registers Learning Objectives The purpose of this exercise is to investigate the fundamental synchronous logic elements: latches, flip-flops, and registers. Prelab
Introduction to Verilog
Introduction to Verilog Synthesis and HDLs Verilog: The Module Continuous (Dataflow) Assignment Gate Level Description Procedural Assignment with always Verilog Registers Mix-and-Match Assignments The
Topics. Midterm Finish Chapter 7
Lecture 9 Topics Midterm Finish Chapter 7 ROM (review) Memory device in which permanent binary information is stored. Example: 32 x 8 ROM Five input lines (2 5 = 32) 32 outputs, each representing a memory
Chapter-5. EE 335 : Advanced Microprocessor. Logic Design with Behavioral Models of Combinational and Sequential Logic
EE 335 : Advanced Microprocessor Chapter-5 Logic Design with Behavioral Models of Combinational and Sequential Logic Ajay Kumar Yadav (Instructor) Electrical & Computer Engineering Temple University Data
St.MARTIN S ENGINEERING COLLEGE Dhulapally, Secunderabad
St.MARTIN S ENGINEERING COLLEGE Dhulapally, Secunderabad-500 014 Subject: Digital Design Using Verilog Hdl Class : ECE-II Group A (Short Answer Questions) UNIT-I 1 Define verilog HDL? 2 List levels of
ECE 353 Lab 3 (Verilog Design Approach)
ECE 353 Lab 3 (Verilog Design Approach) Prof Daniel Holcomb Recall What You Will Do Design and implement a serial MIDI receiver Hardware in an Altera Complex Programmable Logic Device (CPLD) MAX 7000S
The Verilog Hardware Description Language
Donald Thomas Philip Moorby The Verilog Hardware Description Language Fifth Edition 4y Spri nnger Preface From the Old to the New Acknowledgments xv xvii xxi 1 Verilog A Tutorial Introduction Getting Started
ECE 4514 Digital Design II. Spring Lecture 13: Logic Synthesis
ECE 4514 Digital Design II A Tools/Methods Lecture Second half of Digital Design II 9 10-Mar-08 L13 (T) Logic Synthesis PJ2 13-Mar-08 L14 (D) FPGA Technology 10 18-Mar-08 No Class (Instructor on Conference)
Course Topics - Outline
Course Topics - Outline Lecture 1 - Introduction Lecture 2 - Lexical conventions Lecture 3 - Data types Lecture 4 - Operators Lecture 5 - Behavioral modeling A Lecture 6 Behavioral modeling B Lecture 7
Writing Circuit Descriptions 8
8 Writing Circuit Descriptions 8 You can write many logically equivalent descriptions in Verilog to describe a circuit design. However, some descriptions are more efficient than others in terms of the
Modeling Sequential Circuits in Verilog
Modeling Sequential Circuits in Verilog COE 202 Digital Logic Design Dr. Muhamed Mudawar King Fahd University of Petroleum and Minerals Presentation Outline Modeling Latches and Flip-Flops Blocking versus
A Verilog Primer. An Overview of Verilog for Digital Design and Simulation
A Verilog Primer An Overview of Verilog for Digital Design and Simulation John Wright Vighnesh Iyer Department of Electrical Engineering and Computer Sciences College of Engineering, University of California,
Digital System Design Verilog-Part III. Amir Masoud Gharehbaghi
Digital System Design Verilog-Part III Amir Masoud Gharehbaghi amgh@mehr.sharif.edu Procedural Blocks initial block always block Place in module body Run concurrently with other module constructs Continuous
VHDL VS VERILOG.
1 VHDL VS VERILOG http://www.cse.cuhk.edu.hk/~mcyang/teaching.html 2 VHDL & Verilog They are both hardware description languages for modeling hardware. They are each a notation to describe the behavioral
14:332:231 DIGITAL LOGIC DESIGN. Hardware Description Languages
14:332:231 DIGITAL LOGIC DESIGN Ivan Marsic, Rutgers University Electrical & Computer Engineering Fall 2013 Lecture #22: Introduction to Verilog Hardware Description Languages Basic idea: Language constructs
CSE 2021 Computer Organization. The Basics of Logic Design
CSE 2021 Computer Organization Appendix C The Basics of Logic Design Outline Fundamental Boolean operations Deriving logic expressions from truth tables Boolean Identities Simplifying logic expressions
Blocking(=) vs Nonblocking (<=) Assignment. Lecture 3: Modeling Sequential Logic in Verilog HDL. Procedural assignments
Blocking(=) vs Nonblocking (
CS429: Computer Organization and Architecture
CS429: Computer Organization and Architecture Dr. Bill Young Department of Computer Sciences University of Texas at Austin Last updated: January 2, 2018 at 11:23 CS429 Slideset 5: 1 Topics of this Slideset
HDL Compiler Directives 7
7 HDL Compiler Directives 7 Directives are a special case of regular comments and are ignored by the Verilog HDL simulator HDL Compiler directives begin, like all other Verilog comments, with the characters
Digital Design with FPGAs. By Neeraj Kulkarni
Digital Design with FPGAs By Neeraj Kulkarni Some Basic Electronics Basic Elements: Gates: And, Or, Nor, Nand, Xor.. Memory elements: Flip Flops, Registers.. Techniques to design a circuit using basic
VLSI II E. Özgür ATES
VERILOG TUTORIAL VLSI II E. Özgür ATES Outline Introduction Language elements Gate-level modeling Data-flow modeling Behavioral modeling Modeling examples Simulation and test bench Hardware Description
Verilog Dataflow Modeling
Verilog Dataflow Modeling Lan-Da Van ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Spring, 2017 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Source:
Introduction to Verilog HDL. Verilog 1
Introduction to HDL Hardware Description Language (HDL) High-Level Programming Language Special constructs to model microelectronic circuits Describe the operation of a circuit at various levels of abstraction
Verilog. Like VHDL, Verilog HDL is like a programming language but:
Verilog Verilog Like VHDL, Verilog HDL is like a programming language but: Statements can execute simultaneously unlike programming e.g. nand(y1,a1,b1); nand(y2,a2,b2); or (out,y1,y2); a1 b1 all statements
problem maximum score 1 8pts 2 6pts 3 10pts 4 15pts 5 12pts 6 10pts 7 24pts 8 16pts 9 19pts Total 120pts
University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences EECS150 J. Wawrzynek Spring 2010 3/31/09 Name: ID number: Midterm Exam This is a closed-book,
ECE 4514 Digital Design II. Spring Lecture 9: Review of Key Ideas, System Commands and Testbenches
ECE 4514 Digital Design II Lecture 9: Review of Key Ideas, System Commands and Testbenches A Language Lecture Iterating the Key Ideas Verilog is a modeling language. It cannot express hardware directly.
EN2911X: Reconfigurable Computing Lecture 06: Verilog (3)
EN2911X: Lecture 06: Verilog (3) Prof. Sherief Reda Division of Engineering, Brown University Fall 09 http://scale.engin.brown.edu Level sensitive latch (D-Latch) The Verilog implementation of a D-latch
Verilog for Synthesis Ing. Pullini Antonio
Verilog for Synthesis Ing. Pullini Antonio antonio.pullini@epfl.ch Outline Introduction to Verilog HDL Describing combinational logic Inference of basic combinational blocks Describing sequential circuits
Digital Design using HDLs EE 4755 Midterm Examination
Name Digital Design using HDLs EE 4755 Midterm Examination Wednesday, 28 October 2015 11:30 12:20 CDT Alias Problem 1 Problem 2 Problem 3 Problem 4 Problem 5 Exam Total (100 pts) Good Luck! Problem 1:
101-1 Under-Graduate Project Digital IC Design Flow
101-1 Under-Graduate Project Digital IC Design Flow Speaker: Ming-Chun Hsiao Adviser: Prof. An-Yeu Wu Date: 2012/9/25 ACCESS IC LAB Outline Introduction to Integrated Circuit IC Design Flow Verilog HDL
A Brief Introduction to Verilog Hardware Definition Language (HDL)
www.realdigital.org A Brief Introduction to Verilog Hardware Definition Language (HDL) Forward Verilog is a Hardware Description language (HDL) that is used to define the structure and/or behavior of digital