CS470: Computer Architecture. AMD Quad Core

Size: px

Start display at page:

Download "CS470: Computer Architecture. AMD Quad Core"

Norman Booth
5 years ago
Views:

1 CS470: Computer Architecture Yashwant K. Malaiya, Professor AMD Quad Core 1

2 Architecture Layers Building blocks Gates, flip-flops Functional bocks: Combinational, Sequential Instruction set architecture Assembly/machine level Implementation using blocks Systems Processor + memory hierarchy 2

3 Optimization Objectives Reduce cost, complexity and power Combinational & sequential minimization Enhance performance Faster technology More Parallelism (of different types) Higher performance with lower cost Memory hierarchy Reliability Testing and verification Redundancy What else? 3

4 Combinational Circuits Gates & Boolean Algebra Functional blocks: Decoder, MUX, Adder Minimization Programmable logic Interlocking building blocks Propagation delays 4

5 Logic Design: Outline Gates, boolean algebra and truth tables Combinational logic and functional blocks (MUX, decoders, Adders, PLAs) Flip-flops, registers and memories Timing analysis Finite state machines Use of software packages for simulation 5

6 Basic hardware building blocks 6

7 OR and NOR A B OR Inputs: 2 or more A B NOR Output=A+B Output=A+B 7

8 AND and NAND A B AND Inputs: 2 or more A B NAND Output = A.B Output = A.B 8

9 Boolean Algebra x 0 0 x 1 x x x 0 x.0 = 0 x.1 = x x.x = 0 x 0 x x 1 1 x x 1 X+0 = x x+1 = 1 x+x = 1 9

10 Boolean Algebra (2) Commutative A+B = B+A Associative A+(B+C)=(A+B)+C A.(B.C)=(A.B).C Distributive A.(B+C)=A.B+A.C A+(B.C)=(A+B).(A+C) A.B = B.A 1/18/2017 Discrete math YKM 10

11 Boolean Algebra (3) DeMorgan s Law A.B = A+B A+B = A.B A B C = A B C A B A B AN D C

12 Some Useful Identities AB+AB = A AB+AB =A(B+B) =A A+AB = A A+AB =A(1+B) =A 12

13 Decoder A=0 B= Input Outputs A,B

14 MUX Multiplexer: selects one of the inputs and connects it to the output. A B A B A B C D S=1 S S 1 0 B C 4 input MUX B 2-to-1 MUX 14

15 Tri-State Lines Tri-state: 0, 1 and high z (disconnected) Used for implementing buses Input A Control C Tri-state buffer Output Y = A if C = 1 High Z if C = 0 15

16 Boolean Functions A B C S S=A.B.C + A.B.C + A.B.C + A.B.C A B C S 16

17 Simplification Some rules for simplification: A + A = A A A = A [Prove them] AB +AB = A [Use for joining or breaking] Proof: AB +AB = A(B +B) = A A+AB = A [Use for absorption] Proof: A+AB = A(1+B) = A 17

18 Karnaugh maps Objective: minimize literals. Based on set-theory Visual representation of algebraic functions Allow algorithmic minimization of boolean functions in sum-ofproducts form Note: ABC+ABC = AB(C+C )=AB Thus ABC and ABC are two pieces of AB. Minterms For n-variables, there are 2 n minterms, corresponding to each row of truth table. 1/18/2017 Discrete math YKM 18

19 Minterms A B C in C out C out = A BC in + AB C in + ABC in + ABC in Involves four minterms 19

20 Combining Minterms Combining minterms F(a,b,c) = a b c +a b c+a bc +a bc minterms a b c +a b c combine to give a b minterms a bc +a bc combine to give a b Terms a b and a b combine to give a Two Adjacent terms: differ in only one variable, complemented in one, uncomplemented on the other. They combine to drop that variable. 1/18/2017 Discrete math YKM 20

21 Visualization of Boolean Functions Each box is a minterm. Adjacent minterms can be combined 2-variable maps X: lower half Y: right half 0 x y 0 1 x y 1 xy xy X X Y = x+y Y 21

22 3-variable Kmaps B A C F(A,B,C) = C +A B B x 1 1 x 1 A C F(A,B,C) = AC +A B All 1 s must be covered. Don t cares (x) can be taken as either 0 or 1 Columns arranged so that adjacent terms are visually adjacent. Sometimes the solution is not unique 22

23 3-variable Kmaps B A C B A C F(A,B,C) = B C +A C+AB F(A,B,C) = A B +BC+AC 23

24 4-variable Kmaps / Design C A D F(A,B,C,D)=ABC +A C D+ A BC+ACD+? B F(A,B,C,D)=B D + C A B 1/18/2017 Discrete math YKM D 24

25 Combinational Logic Optimization Design steps: Get truth table Do minimization (K-map, Quine-McCluskey etc) as applicable Get Boolean expression Get logic diagram. Automated methods: computer based implementation. Example: Multi-output circuits: Many functions have multiple outputs Often implemented as PLAs Objective: minimize product terms Adjacent product terms: with same output combinations 25

26 Full Adder A i B i C i C i+ S 1 i A i B i C i C i+1 S 26

27 4-bit Adder A 3 B 3 A 2 B 2 A 1 B 1 A 0 B 0 Full Full Full Full 0 adder adder adder adder C 4 C C 2 3 C 1 S 3 S 2 S 1 S 0 Note that propagation delay add for each stage. 27

28 Two-level logic: SOP form A combinational functional can be implemented using a two-level implementation Sum-of-products (SOP)form F(A,B,C) = B C +A B AND-OR A B C F B A C 28

29 Two-level logic: POS form Product of Sums (POS) form: Step: 1. Minimize F (i.e. 0s) is SOP form. 2. Complement both sides 3. Use DeMorgan s for RHS F (A,B,C) = B C+AB F(A,B,C) = (B+C )(A +B ) OR-AND A B C F B A C 29

QUESTION BANK FOR TEST

CSCI 2121 Computer Organization and Assembly Language PRACTICE QUESTION BANK FOR TEST 1 Note: This represents a sample set. Please study all the topics from the lecture notes. Question 1. Multiple Choice