2008 The McGrawHill Companies, Inc. All rights reserved.


 Alannah Rodgers
 2 years ago
 Views:
Transcription
1 28 The McGrawHill Companies, Inc. All rights reserved.
2 28 The McGrawHill Companies, Inc. All rights reserved. All or Nothing Gate Boolean Expression: A B = Y Truth Table (ee next slide) or AB = Y
3 28 The McGrawHill Companies, Inc. All rights reserved. Truth Table  AND Gate B A Y
4 28 The McGrawHill Companies, Inc. All rights reserved. QUIZ What is the output of the AND gate? L L? H H? L H? H L? Unique Output: Output HIGH only when all inputs are HIGH.
5 28 The McGrawHill Companies, Inc. All rights reserved. Any or All Gate Boolean Expression: A + B = Y Truth Table (ee next slide)
6 28 The McGrawHill Companies, Inc. All rights reserved. Truth Table  OR Gate B A Y
7 28 The McGrawHill Companies, Inc. All rights reserved. NOT Circuit Gives output that is not the same as the input. Boolean Expression: Y = A or Y = A Double inverting: A = A NOT gate inverts, or complements, or negates
8 28 The McGrawHill Companies, Inc. All rights reserved. NOT AND or inverted AND function. Boolean Expression: or A B = Y (A B)' = Y Truth Table (ee next slide)
9 28 The McGrawHill Companies, Inc. All rights reserved. Truth Table  NAND Gate B A AND NAND
10 28 The McGrawHill Companies, Inc. All rights reserved. NOT OR or Inverted OR Boolean Expression: A + B = Y or (A + B)' = Y Truth Table (ee next slide)
11 28 The McGrawHill Companies, Inc. All rights reserved. Truth Table  NOR Gate B A OR NOR
12 28 The McGrawHill Companies, Inc. All rights reserved. Known as Exclusive OR Gate Anything but not all Gate Boolean Expression: A B = Y Truth Table (ee next slide)
13 28 The McGrawHill Companies, Inc. All rights reserved. Truth Table  XOR Gate B A OR XOR
14 28 The McGrawHill Companies, Inc. All rights reserved. Known as the Exclusive NOR Gate The Inverted XOR Boolean Expression: A B = Y or (A B)' = Y or A B = Y Truth Table (ee next slide)
15 28 The McGrawHill Companies, Inc. All rights reserved. Truth Table  XNOR Gate B A XOR XNOR
16 28 The McGrawHill Companies, Inc. All rights reserved. The NAND as a Universal Gate Universal gate can be used in combination to create any other logic function. horting NAND inputs Example: Yields the NOT logic function A + B Equal to the OR logic function
17 28 The McGrawHill Companies, Inc. All rights reserved. Using Inverters to Convert Gates For example:
18 Combinational vs. equential logic circuits Combinatorial logic circuit : Output is determined by input at one moment equential logic circuit : Output is determined by input and current state of the logic circuit equential Logic Circuit input combinational logic circuit feedback memory element output=f(input,state) tate of memory element is determined by input and previous state of the element memory element: flipflops, latch 28 The McGrawHill Companies, Inc. All rights reserved.
19 28 The McGrawHill Companies, Inc. All rights reserved. Combinatorial vs. equential logic circuits Combinatorial logic circuits equential logic circuit
20 28 The McGrawHill Companies, Inc. All rights reserved. Tools of the Trade for olving Logic Problems Gate symbols Truth tables Boolean expressions Combinational(combinatorial) logic circuits: ANDOR pattern of gates from umofproducts Boolean expression such as: AB + CD = Y ANDOR pattern of gates ORAND pattern of gates from Productofsums Boolean expression such as: (A+B) (C+D) = Y ORAND pattern of gates
21 28 The McGrawHill Companies, Inc. All rights reserved. Logic Circuit From Boolean Expression Example: Draw the ANDOR logic diagram for the Boolean expression: AB + CD = Y tep : OR AB with CD tep 2: Add top AND gate tep 3: Add bottom AND gate
22 28 The McGrawHill Companies, Inc. All rights reserved. Boolean Algebra Boolean Postulates P X = or X = P2 = P3 = P4 + = P5 + = P6 = = P7 + = + =
23 28 The McGrawHill Companies, Inc. All rights reserved. Basic rules Boolean Algebra. X+=+X=X 2. X = X=X 3. X+=+X= 4. X = X= 5. X+X=X 6. X X=X 7. X X 8. X X 9. X X commutative law. X+Y=Y+X. XY=YX associate law 2. (X + Y) + Z = X + (Y + Z) 3. (XY) Z = X (YZ) distributive law 4. X (Y + Z) = XY + XZ 5. X + YZ = (X+Y)(X+Z) De Morgan's theorem 6. X Y X Y 7. XY X absorptive law 8. X + XY = X 9. X(X+Y) = X Y
24 28 The McGrawHill Companies, Inc. All rights reserved. Boolean Expressions umofproducts form: A B + C D = Y Productofsums form: (A + B) (C + D) = Y
25 28 The McGrawHill Companies, Inc. All rights reserved. Boolean Expressions Minterm A term of a boolean function in sum of products form composed of all input variables For f(w,x,y,z) W XY Z WXYZ minterms W XY Maxterm A term of a boolean function in product of sums form composed of all input variables For f(w,x,y,z) W X Z Not minterms ( W X Y Z ) ( W X Y Z ) maxterms ( W X Y ) ( W X Z ) Not maxterms
26 28 The McGrawHill Companies, Inc. All rights reserved. Boolean Expression from Truth Table Write the Boolean expression that describes the logic in this truth table. Truth Table Input Output ABC Y tep : Focus only on the truth table lines with outputs of. tep 2: AND the inputs for these two lines and logically OR the ANDed groups. A B C + A B C = Y Minterm Boolean expression: A B C + A B C = Y
27 Truth Table From Boolean Expressions Fill in a truth table from a minterm Boolean Expression. Minterm Boolean expression: A B C + A B C + A B C = Y tep : Place three s in output column. tep 2: Place five s in blanks in output column of truth table. Truth Table Input Output ABC Y 28 The McGrawHill Companies, Inc. All rights reserved.
28 28 The McGrawHill Companies, Inc. All rights reserved. Truth Table from Boolean Expressions Fill in a truth table from a Boolean Expression. Boolean expression: A B + A B C = Y tep : Place single output column for term with three variables. tep 2: Place two s in output column for term with two variables. tep 3: Fill in s. Truth Table Input Output ABC Y
29 28 The McGrawHill Companies, Inc. All rights reserved. Boolean Expression Minterm expression of 3 Variables x y z f minterm symbol f ( x, y, z) f ( x, y, z) x y z x y z x y z x y z x y z x y z x y z x y z m(,, 3, 5, 7) f ( x, y, z) m(2, 4, 6) m(,, 3, 5, 7) m m m 2 m 3 m 4 m 5 m 6 m 7 m(2, 4, 6) x y z f ( x, y, z) m(,, 3, 5, 7) xyz xyz xyz xyz f ( x, y, z) m(2, 4, 6) xyz xyz xyz xyz xyz xyz x y z xyz x y z x y z x y z x y z xyz xyz xyz xyz xyz xyz xyz
30 Boolean Expression 28 The McGrawHill Companies, Inc. All rights reserved. Minterm expression of 4 Variables a b c d minterm symbol a b c d minterm symbol m abcd abcd m abcd m 2 abcd m 3 abcd m 4 abcd m 5 abcd m 6 abcd m 7 abcd abcd abcd abcd abcd abcd abcd abcd m 8 m 9 m m m 2 m 3 m 4 m 5 Example f ( a, b, c, d ) m(,, 5, 9,,5) abcd abcd abcd abcd abcd abcd
31 Boolean Expression 28 The McGrawHill Companies, Inc. All rights reserved. Maxterm expression of 3 Variables x y z f maxterm symbol Example x x x x x x x x y z y z y y z y z y z y z z y z M M M 2 M 3 M 4 M 5 M 6 M 7 f ( x, y, z) M(,, 3, 5, 7) ( x y z)( x y z)( x y z)( x y z)( x y z)
32 28 The McGrawHill Companies, Inc. All rights reserved. 7) 6, (, 7) 6, (, 5) 4, 3, 2, (, 5) 4, 3, 2, (, ),, ( m M M m c b a f 4,5) 2,3, (, ) )( )( )( )( ( 4,5) 2,3, (, ),, ( M c b a c b a c b a c b a c b a abc abc abc abc abc abc abc abc abc abc abc abc abc abc abc m c b a f (,6,7) ) )( )( ( (,6,7) ),, ( M c b a c b a c b a abc abc abc abc abc abc abc abc abc m c b a f 4,5) 3, 2, (, 4,5) 3, 2, (, (,6,7) (,6,7) ),, ( m M M m c b a f Negation of minterms becomes maxterms Negation of maxterms becomes minterms OP functions and PO functions
33 28 The McGrawHill Companies, Inc. All rights reserved. implify Boolean Expression Karnaugh Maps(Kmap) A Kmap is a diagram made up of squares, with each square representing one minterm of the function is to be minimized. The simplest expression is a Boolean expression with minimum number of terms and the smallest possible number of literals in each term. This expression produces a circuit with minimum number of gates and with minimum number of inputs to each gate. The simplest expression is not unique.
34 28 The McGrawHill Companies, Inc. All rights reserved. implify Boolean Expression Drawing and grouping Karnaugh Maps(Kmap) Minterms in a Kmap must be arranged in a sequence, and the sequence is that only one bit changes in value from one adjacent column to the next. It utilizes the basic rule 7 of Boolean algebra. X+X = hape of a mintermgroup has to be a square or a rectangle. The number of minterms in a group must be multiple of 2 n. Group the adjacent minterms or groups. The bigger the better!
35 28 The McGrawHill Companies, Inc. All rights reserved. implify Boolean Expression Drawing Karnaugh Maps(Kmap) F ( A, B, C) m(,2,3,4,5,7) AB C 2 3 F ( A, B, C, D) m(,2,4,5,7,9, 2, 3, 5) AB CD Only one bit is different 4= = = 3=
36 28 The McGrawHill Companies, Inc. All rights reserved. implify Boolean Expression F ( A, B, C, D) m(4,5,7,2,3,5) AB CD implified as:. Group 4,5,2,3 and 7,5 BC + BCD 2. Group 4,5,2,3 and 5,7,3,5 BC + BD Which one is more simple? Can 4,5,7,2,3,5 be grouped?
37 28 The McGrawHill Companies, Inc. All rights reserved. implify Boolean Expression Don t care terms: terms that can be either or F( A, B, C, D) m(,2,3,4,5,) d(,7,9,5) F( A, B, C, D) m(,2,3,4,6,8,) d(,2,4) m(,2,3,4,8,9,) F( A, B, C, D) d(,5,6,7,,2) CD AB x x x x CD AB x x x CD AB x x x x x x F AB CD AC F D AB F A B
38 28 The McGrawHill Companies, Inc. All rights reserved. implify Boolean Expression f ( w, x, y, z) wx wxy wyz w yz wxy z wx( y y )( z z) wxy( z z) w( x x) yz w( x x) yz wxy z m(, 3, 5, 6, 7, 2, 3, 4, 5) yz wx f ( w, x, y, z) wx wz xy
39 28 The McGrawHill Companies, Inc. All rights reserved. Encoder Encoder is a combinational circuit that converts binary information from a maximum of 2 n input lines to n output lines. This output lines generate a binary code corresponding to the input lines. The encoder detects the active input. 4 2 encoder input output D 3 D 2 D D D 3 D 2 D D B B B B B D2 D3, B D D3
40 28 The McGrawHill Companies, Inc. All rights reserved. 8 3 encoder input output D 7 D 6 D 5 D 4 D 3 D 2 D D B 2 B B D D D D B D D D D B D D D D B D 7 D 6 D 5 D 4 D 3 D 2 D D B B B 2
41 Example of commercial IC 28 The McGrawHill Companies, Inc. All rights reserved.
42 28 The McGrawHill Companies, Inc. All rights reserved. Multiplexer A multiplexer is a combinational circuit that selects binary information from one of many input lines and directs it to a single output line. There are 2 n input lines and n selection lines whose bit combinations determine which input is selected. D D D 2 D 3 8x multiplexer x8 demultiplexer D D D 2 D 3 D 4 D 4 D 5 D 5 D 6 D 6 D 7 (sender) (receiver) D elect signals elect signals
43 28 The McGrawHill Companies, Inc. All rights reserved. 4 multiplexer election lines output F F D D D 2 D 3 D D D2 D3 D D D 2 F D 3
44 28 The McGrawHill Companies, Inc. All rights reserved. 8 multiplexer election lines output 2 F D D D 2 D 3 D 4 D 5 D 6 D 7 D D D 2 D 3 F 2 D 4 D 5 D 6 D D D D D D D D D F
45 28 The McGrawHill Companies, Inc. All rights reserved. Decoder A decoder is a combinational logic circuit that converts binary information from n input lines to maximum 2 n unique output lines. Decoders performs the inverse operation of encoders. 2 4 decoder/demultiplexer B A input output B A Y 3 Y 2 Y Y Y Y Y 2 Y Y 2 BA BA Y Y 3 BA BA Y 3
46 28 The McGrawHill Companies, Inc. All rights reserved. Commercial IC s are constructed with NAND gates. input output B A B A Y 3 Y 2 Y Y Y Y Y 2 Y Y 2 BA BA Y Y 3 BA BA Y 3
47 28 The McGrawHill Companies, Inc. All rights reserved. 2 4 decoders with enable inputs Most decoders include one or more enable inputs to control the circuit operation. A decoder operates when the enable input is equal to. A decoder constructed with NAND gates operates when the enable input is equal to. B A E input output E B A Y 3 Y 2 Y Y Y Y Y 2 Y Y 2 EBA EB A Y Y 3 EBA EBA Y 3
48 28 The McGrawHill Companies, Inc. All rights reserved. 3 8 decoder input output C B A Y 7 Y 6 Y 5 Y 4 Y 3 Y 2 Y Y Y Y 4 CBA, CBA, Y Y 5 CBA, CBA, Y Y 2 6 CBA, CBA, Y Y 3 7 CBA CBA C B A Y Y Y 2 Y 3 Y 4 Y 5 Y 6 Y 7
49 Demultiplexer 28 The McGrawHill Companies, Inc. All rights reserved. Demultiplexer is combinational circuit that receives information from a single input line and directs it to one of 2 n possible output lines. A decoder with enable input can function as a demultiplexer. A B 2x4 Decoder Y Y Y 2 Y 3 E x4 Demultiplexer Y Y Y 2 Y 3 E A B 2 4 decoder 4 demultiplexer
50 28 The McGrawHill Companies, Inc. All rights reserved. 4 cases of onebit addition X Y + C input output X Y C Y X C Y X XY XY X Y C HA C X Y : sum C : carry Half Adder
51 28 The McGrawHill Companies, Inc. All rights reserved. Full Adder Used for adding binary place values other than the s place Input Output Logic ymbol: C in A B Full Adder (sum) C (carry out) Logic Diagram:
52 28 The McGrawHill Companies, Inc. All rights reserved. Full Adder 8 cases of onebit addition C in X + Y C out input output X Y C in C out C XYC in X ( YC in X ( Y C XYC YC in X Y C out C C in in XYC in in in in ( XY XY ) ( X Y ) XY XYC ) X ( YC ) X ( Y C XYC in XY ( C in in in ) XY C in in C XYC YC in in XYC ) in ) in
53 28 The McGrawHill Companies, Inc. All rights reserved. Full Adder X Y C in X Y FA HA C out C in C out X Y C in C out C ( X Y) in XY X Y HA HA C in C out
54 28 The McGrawHill Companies, Inc. All rights reserved. Parallel Adding Use half adder for LD Use full adder for other digits A 2 A A + B 2 B B
55 Parallel Adder + UM appears here Parallel adders are available in IC form. s place uses halfadder 2s, 4s, 8s places use full adders The The McGrawHill Companies, Inc. Inc. All All rights reserved.
56 28 The McGrawHill Companies, Inc. All rights reserved. Paralleladder/subtracter X 3 Y 3 X 2 Y 2 X Y X Y FA FA FA FA C 3 C 2 C C Parallel adder X 3 Y 3 X 2 Y 2 X Y X Y (sign) :Add :ub FA C 3 FA C 2 FA C FA C C Parallel adder/subtracter
57 28 The McGrawHill Companies, Inc. All rights reserved. Highspeed adder The FA s must wait until their right FA s generate carries, i.e., a parallel adder has the delay time it takes to propagate the carry through the full adder. A highspeed adder(carry Lookahead Adder(CLA)) A CLA employs the carrylookahead generator that does not have any delay time for propagating the carry. C ) For 4bit CLA C C G PC out Ci XiYi ( Xi Yi Ci i i i i C where G i X i Y i P i X i Y G: generate, P: propagate G P C 2 G PC G PG P P C 3 G2 P2 C2 G2 P2 G PG P P C) G2 P2 G 2 4 G3 PC 3 3 G3 PG 3 2 P3 P2 G P3 P2 PG P3 P2 PP C C C i X i Y i C i P C i ( P PG P P P C i 2 i
58 28 The McGrawHill Companies, Inc. All rights reserved. Highspeed adder XY Partial Full Adder (PFA) G P C X 3 Y 3 X 2 Y 2 X Y X Y 3 G P C 2 G P C G P C G P C G 3 P 3 C 3 G 2 P 2 C 2 G P C G P Carry Lookahead Logic C
59 28 The McGrawHill Companies, Inc. All rights reserved. Highspeed adder 6bit CLA with four 4bit CLA s P G P P P G G G 3 2 P C 4 G3 PC 3 3 G3 PG 3 2 P3 P2 G P3 P2 PG P3 P2 PP C 3 P3 G2 P3 P2 G P3 P2 P G X 25 Y 25 X 8 Y 8 X 47 Y 47 X 3 Y 3 4Bit Adder 4Bit Adder 4Bit Adder 4Bit Adder 25 G P C 8 G P C 47 G P C 3 G P C G 3 P 3 C 3 G 2 P 2 C 2 G P C G P Carry Lookahead Logic G G P G C
Gate Level Minimization Map Method
Gate Level Minimization Map Method Complexity of hardware implementation is directly related to the complexity of the algebraic expression Truth table representation of a function is unique Algebraically
More informationQUESTION BANK FOR TEST
CSCI 2121 Computer Organization and Assembly Language PRACTICE QUESTION BANK FOR TEST 1 Note: This represents a sample set. Please study all the topics from the lecture notes. Question 1. Multiple Choice
More informationCode No: R Set No. 1
Code No: R059210504 Set No. 1 II B.Tech I Semester Regular Examinations, November 2006 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science & Systems
More informationCode No: 07A3EC03 Set No. 1
Code No: 07A3EC03 Set No. 1 II B.Tech I Semester Regular Examinations, November 2008 SWITCHING THEORY AND LOGIC DESIGN ( Common to Electrical & Electronic Engineering, Electronics & Instrumentation Engineering,
More informationB.Tech II Year I Semester (R13) Regular Examinations December 2014 DIGITAL LOGIC DESIGN
B.Tech II Year I Semester () Regular Examinations December 2014 (Common to IT and CSE) (a) If 1010 2 + 10 2 = X 10, then X is  Write the first 9 decimal digits in base 3. (c) What is meant by don
More informationIT 201 Digital System Design Module II Notes
IT 201 Digital System Design Module II Notes BOOLEAN OPERATIONS AND EXPRESSIONS Variable, complement, and literal are terms used in Boolean algebra. A variable is a symbol used to represent a logical quantity.
More informationCode No: R Set No. 1
Code No: R059210504 Set No. 1 II B.Tech I Semester Regular Examinations, November 2007 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science & Systems
More informationSimplification of Boolean Functions
Simplification of Boolean Functions Contents: Why simplification? The Map Method Two, Three, Four and Five variable Maps. Simplification of two, three, four and five variable Boolean function by Map method.
More informationCombinational Logic Circuits
Chapter 3 Combinational Logic Circuits 12 Hours 24 Marks 3.1 Standard representation for logical functions Boolean expressions / logic expressions / logical functions are expressed in terms of logical
More informationChapter 2 Combinational Logic Circuits
Logic and Computer Design Fundamentals Chapter 2 Combinational Logic Circuits Part 2 Circuit Optimization Overview Part Gate Circuits and Boolean Equations Binary Logic and Gates Boolean Algebra Standard
More information1. Mark the correct statement(s)
1. Mark the correct statement(s) 1.1 A theorem in Boolean algebra: a) Can easily be proved by e.g. logic induction b) Is a logical statement that is assumed to be true, c) Can be contradicted by another
More informationGateLevel Minimization
MEC520 디지털공학 GateLevel Minimization JeeHwan Ryu School of Mechanical Engineering GateLevel MinimizationThe Map Method Truth table is unique Many different algebraic expression Boolean expressions may
More informationUnitIV Boolean Algebra
UnitIV Boolean Algebra Boolean Algebra Chapter: 08 Truth table: Truth table is a table, which represents all the possible values of logical variables/statements along with all the possible results of
More informationAssignment (36) Boolean Algebra and Logic Simplification  General Questions
Assignment (36) Boolean Algebra and Logic Simplification  General Questions 1. Convert the following SOP expression to an equivalent POS expression. 2. Determine the values of A, B, C, and D that make
More informationExperiment 3: Logic Simplification
Module: Logic Design Name:... University no:.. Group no:. Lab Partner Name: Mr. Mohamed ElSaied Experiment : Logic Simplification Objective: How to implement and verify the operation of the logical functions
More informationChapter 2. Boolean Expressions:
Chapter 2 Boolean Expressions: A Boolean expression or a function is an expression which consists of binary variables joined by the Boolean connectives AND and OR along with NOT operation. Any Boolean
More informationChapter 3. GateLevel Minimization. Outlines
Chapter 3 GateLevel Minimization Introduction The Map Method FourVariable Map FiveVariable Map Outlines Product of Sums Simplification Don tcare Conditions NAND and NOR Implementation Other TwoLevel
More informationGateLevel Minimization
GateLevel Minimization ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2011 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Outlines The Map Method
More informationCode No: R Set No. 1
Code No: R059210504 Set No. 1 II B.Tech I Semester Supplementary Examinations, February 2007 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science
More informationGate Level Minimization
Gate Level Minimization By Dr. M. Hebaishy Digital Logic Design Ch Simplifying Boolean Equations Example : Y = AB + AB Example 2: = B (A + A) T8 = B () T5 = B T Y = A(AB + ABC) = A (AB ( + C ) ) T8 =
More informationChapter 2: Combinational Systems
Uchechukwu Ofoegbu Chapter 2: Combinational Systems Temple University Adapted from Alan Marcovitz s Introduction to Logic and Computer Design Riddle Four switches can be turned on or off. One is the switch
More informationDigital logic fundamentals. Question Bank. Unit I
Digital logic fundamentals Question Bank Subject Name : Digital Logic Fundamentals Subject code: CA102T Staff Name: R.Roseline Unit I 1. What is Number system? 2. Define binary logic. 3. Show how negative
More informationCombinational Logic & Circuits
WeekI Combinational Logic & Circuits Spring' 232  Logic Design Page Overview Binary logic operations and gates Switching algebra Algebraic Minimization Standard forms Karnaugh Map Minimization Other
More informationLSN 4 Boolean Algebra & Logic Simplification. ECT 224 Digital Computer Fundamentals. Department of Engineering Technology
LSN 4 Boolean Algebra & Logic Simplification Department of Engineering Technology LSN 4 Key Terms Variable: a symbol used to represent a logic quantity Compliment: the inverse of a variable Literal: a
More informationExperiment 4 Boolean Functions Implementation
Experiment 4 Boolean Functions Implementation Introduction: Generally you will find that the basic logic functions AND, OR, NAND, NOR, and NOT are not sufficient to implement complex digital logic functions.
More informationChapter 2 Boolean algebra and Logic Gates
Chapter 2 Boolean algebra and Logic Gates 2. Introduction In working with logic relations in digital form, we need a set of rules for symbolic manipulation which will enable us to simplify complex expressions
More informationGateLevel Minimization
GateLevel Minimization ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2017 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Outlines The Map Method
More informationCS8803: Advanced Digital Design for Embedded Hardware
CS883: Advanced Digital Design for Embedded Hardware Lecture 2: Boolean Algebra, Gate Network, and Combinational Blocks Instructor: Sung Kyu Lim (limsk@ece.gatech.edu) Website: http://users.ece.gatech.edu/limsk/course/cs883
More informationCombinational Circuits
Combinational Circuits Combinational circuit consists of an interconnection of logic gates They react to their inputs and produce their outputs by transforming binary information n input binary variables
More informationChapter 2 Combinational
Computer Engineering 1 (ECE290) Chapter 2 Combinational Logic Circuits Part 2 Circuit Optimization HOANG Trang 2008 Pearson Education, Inc. Overview Part 1 Gate Circuits and Boolean Equations Binary Logic
More informationBinary logic. Dr.AbuArqoub
Binary logic Binary logic deals with variables like (a, b, c,, x, y) that take on two discrete values (, ) and with operations that assume logic meaning ( AND, OR, NOT) Truth table is a table of all possible
More informationUNIT4 BOOLEAN LOGIC. NOT Operator Operates on single variable. It gives the complement value of variable.
UNIT4 BOOLEAN LOGIC Boolean algebra is an algebra that deals with Boolean values((true and FALSE). Everyday we have to make logic decisions: Should I carry the book or not?, Should I watch TV or not?
More informationGateLevel Minimization. BME208 Logic Circuits Yalçın İŞLER
GateLevel Minimization BME28 Logic Circuits Yalçın İŞLER islerya@yahoo.com http://me.islerya.com Complexity of Digital Circuits Directly related to the complexity of the algebraic expression we use to
More informationDepartment of Electrical and Computer Engineering University of Wisconsin  Madison. ECE/CS 352 Digital System Fundamentals.
Department of Electrical and Computer Engineering University of Wisconsin  Madison ECE/C 352 Digital ystem Fundamentals Quiz #2 Thursday, March 7, 22, 7:158:3PM 1. (15 points) (a) (5 points) NAND, NOR
More informationLiteral Cost F = BD + A B C + A C D F = BD + A B C + A BD + AB C F = (A + B)(A + D)(B + C + D )( B + C + D) L = 10
Circuit Optimization Goal: To obtain the simplest implementation for a given function Optimization is a more formal approach to simplification that is performed using a specific procedure or algorithm
More information2.1 Binary Logic and Gates
1 EED2003 Digital Design Presentation 2: Boolean Algebra Asst. Prof.Dr. Ahmet ÖZKURT Asst. Prof.Dr Hakkı T. YALAZAN Based on the Lecture Notes by Jaeyoung Choi choi@comp.ssu.ac.kr Fall 2000 2.1 Binary
More informationCOMPUTER ARCHITECTURE AND DIGITAL DESIGN
SPECIAL MAKEUP  FINAL EXAMINATION COMPUTER ARCHITECTURE AND DIGITAL DESIGN 036026501 S C H O O L O F C O M P U T E R S C I E N C E  U N I V E R S I T Y O F W I N D S O R Fall 2008 Last Name: First
More informationENGINEERS ACADEMY. 7. Given Boolean theorem. (a) A B A C B C A B A C. (b) AB AC BC AB BC. (c) AB AC BC A B A C B C.
Digital Electronics Boolean Function QUESTION BANK. The Boolean equation Y = C + C + C can be simplified to (a) (c) A (B + C) (b) AC (d) C. The Boolean equation Y = (A + B) (A + B) can be simplified to
More informationNODIA AND COMPANY. GATE SOLVED PAPER Computer Science Engineering Digital Logic. Copyright By NODIA & COMPANY
No part of this publication may be reproduced or distributed in any form or any means, electronic, mechanical, photocopying, or otherwise without the prior permission of the author. GATE SOLVED PAPER Computer
More informationLOGIC CIRCUITS. Kirti P_Didital Design 1
LOGIC CIRCUITS Kirti P_Didital Design 1 Introduction The digital system consists of two types of circuits, namely (i) Combinational circuits and (ii) Sequential circuit A combinational circuit consists
More informationCombinational Logic Circuits
Chapter 2 Combinational Logic Circuits J.J. Shann (Slightly trimmed by C.P. Chung) Chapter Overview 21 Binary Logic and Gates 22 Boolean Algebra 23 Standard Forms 24 TwoLevel Circuit Optimization
More informationEE 8351 Digital Logic Circuits Ms.J.Jayaudhaya, ASP/EEE
EE 8351 Digital Logic Circuits Ms.J.Jayaudhaya, ASP/EEE 1 Logic circuits for digital systems may be combinational or sequential. A combinational circuit consists of input variables, logic gates, and output
More informationCS470: Computer Architecture. AMD Quad Core
CS470: Computer Architecture Yashwant K. Malaiya, Professor malaiya@cs.colostate.edu AMD Quad Core 1 Architecture Layers Building blocks Gates, flipflops Functional bocks: Combinational, Sequential Instruction
More informationReview: Standard forms of expressions
Karnaugh maps Last time we saw applications of Boolean logic to circuit design. The basic Boolean operations are AND, OR and NOT. These operations can be combined to form complex expressions, which can
More informationELCT201: DIGITAL LOGIC DESIGN
ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 3 Following the slides of Dr. Ahmed H. Madian محرم 1439 ه Winter
More informationX Y Z F=X+Y+Z
This circuit is used to obtain the compliment of a value. If X = 0, then X = 1. The truth table for NOT gate is : X X 0 1 1 0 2. OR gate : The OR gate has two or more input signals but only one output
More informationGet Free notes at ModuleI One s Complement: Complement all the bits.i.e. makes all 1s as 0s and all 0s as 1s Two s Complement: One s complement+1 SIGNED BINARY NUMBERS Positive integers (including zero)
More informationS1 Teknik Telekomunikasi Fakultas Teknik Elektro FEH2H3 2016/2017
S1 Teknik Telekomunikasi Fakultas Teknik Elektro FEH2H3 2016/2017 Karnaugh Map Karnaugh maps Last time we saw applications of Boolean logic to circuit design. The basic Boolean operations are AND, OR and
More informationDepartment of Electrical Engineering McGill University ECSE 221 Introduction to Computer Engineering Assignment 2 Combinational Logic
Department of Electrical Engineering McGill University ECSE 221 Introduction to Computer Engineering Assignment 2 Combinational Logic Question 1: Due October 19 th, 2009 A convenient shorthand for specifying
More informationSIDDHARTH GROUP OF INSTITUTIONS :: PUTTUR Siddharth Nagar, Narayanavanam Road QUESTION BANK (DESCRIPTIVE)
SIDDHARTH GROUP OF INSTITUTIONS :: PUTTUR Siddharth Nagar, Narayanavanam Road 517583 QUESTION BANK (DESCRIPTIVE) Subject with Code : STLD(16EC402) Year & Sem: IIB.Tech & ISem Course & Branch: B.Tech
More informationComputer Science. Unit4: Introduction to Boolean Algebra
Unit4: Introduction to Boolean Algebra Learning Objective At the end of the chapter students will: Learn Fundamental concepts and basic laws of Boolean algebra. Learn about Boolean expression and will
More informationBoolean Algebra. BME208 Logic Circuits Yalçın İŞLER
Boolean Algebra BME28 Logic Circuits Yalçın İŞLER islerya@yahoo.com http://me.islerya.com 5 Boolean Algebra /2 A set of elements B There exist at least two elements x, y B s. t. x y Binary operators: +
More informationContents. Chapter 3 Combinational Circuits Page 1 of 34
Chapter 3 Combinational Circuits Page of 34 Contents Contents... 3 Combinational Circuits... 2 3. Analysis of Combinational Circuits... 2 3.. Using a Truth Table... 2 3..2 Using a Boolean unction... 4
More informationChapter 3 Simplification of Boolean functions
3.1 Introduction Chapter 3 Simplification of Boolean functions In this chapter, we are going to discuss several methods for simplifying the Boolean function. What is the need for simplifying the Boolean
More informationVariable, Complement, and Literal are terms used in Boolean Algebra.
We have met gate logic and combination of gates. Another way of representing gate logic is through Boolean algebra, a way of algebraically representing logic gates. You should have already covered the
More informationInjntu.com Injntu.com Injntu.com R16
1. a) What are the three methods of obtaining the 2 s complement of a given binary (3M) number? b) What do you mean by Kmap? Name it advantages and disadvantages. (3M) c) Distinguish between a halfadder
More informationPART B. 3. Minimize the following function using Kmap and also verify through tabulation method. F (A, B, C, D) = +d (0, 3, 6, 10).
II B. Tech II Semester Regular Examinations, May/June 2015 SWITCHING THEORY AND LOGIC DESIGN (Com. to EEE, ECE, ECC, EIE.) Time: 3 hours Max. Marks: 70 Note: 1. Question Paper consists of two parts (PartA
More informationComputer Organization
Computer Organization (Logic circuits design and minimization) KR Chowdhary Professor & Head Email: kr.chowdhary@gmail.com webpage: krchowdhary.com Department of Computer Science and Engineering MBM Engineering
More information數位系統 Digital Systems 朝陽科技大學資工系. Speaker: FuwYi Yang 楊伏夷. 伏夷非征番, 道德經察政章 (Chapter 58) 伏者潛藏也道紀章 (Chapter 14) 道無形象, 視之不可見者曰夷
數位系統 Digital Systems Department of Computer Science and Information Engineering, Chaoyang University of Technology 朝陽科技大學資工系 Speaker: FuwYi Yang 楊伏夷 伏夷非征番, 道德經察政章 (Chapter 58) 伏者潛藏也道紀章 (Chapter 14) 道無形象,
More informationA B AB CD Objectives:
Objectives:. Four variables maps. 2. Simplification using prime implicants. 3. "on t care" conditions. 4. Summary.. Four variables Karnaugh maps Minterms A A m m m3 m2 A B C m4 C A B C m2 m8 C C m5 C m3
More informationBoolean Algebra and Logic Gates
Boolean Algebra and Logic Gates Binary logic is used in all of today's digital computers and devices Cost of the circuits is an important factor Finding simpler and cheaper but equivalent circuits can
More informationSUBJECT CODE: IT T35 DIGITAL SYSTEM DESIGN YEAR / SEM : 2 / 3
UNIT  I PART A (2 Marks) 1. Using Demorgan s theorem convert the following Boolean expression to an equivalent expression that has only OR and complement operations. Show the function can be implemented
More informationSWITCHING THEORY AND LOGIC CIRCUITS
SWITCHING THEORY AND LOGIC CIRCUITS COURSE OBJECTIVES. To understand the concepts and techniques associated with the number systems and codes 2. To understand the simplification methods (Boolean algebra
More informationELCT201: DIGITAL LOGIC DESIGN
ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 3 Following the slides of Dr. Ahmed H. Madian ذو الحجة 1438 ه Winter
More information10EC33: DIGITAL ELECTRONICS QUESTION BANK
10EC33: DIGITAL ELECTRONICS Faculty: Dr.Bajarangbali E Examination QuestionS QUESTION BANK 1. Discuss canonical & standard forms of Boolean functions with an example. 2. Convert the following Boolean function
More informationR10. II B. Tech I Semester, Supplementary Examinations, May
SET  1 1. a) Convert the following decimal numbers into an equivalent binary numbers. i) 53.625 ii) 4097.188 iii) 167 iv) 0.4475 b) Add the following numbers using 2 s complement method. i) 48 and +31
More informationNH 67, Karur Trichy Highways, Puliyur C.F, Karur District DEPARTMENT OF INFORMATION TECHNOLOGY CS 2202 DIGITAL PRINCIPLES AND SYSTEM DESIGN
NH 67, Karur Trichy Highways, Puliyur C.F, 639 114 Karur District DEPARTMENT OF INFORMATION TECHNOLOGY CS 2202 DIGITAL PRINCIPLES AND SYSTEM DESIGN UNIT 1 BOOLEAN ALGEBRA AND LOGIC GATES Review of binary
More informationMidTerm Exam Solutions
CS/EE 26 Digital Computers: Organization and Logical Design MidTerm Eam Solutions Jon Turner 3/3/3. (6 points) List all the minterms for the epression (B + A)C + AC + BC. Epanding the epression gives
More informationDigital Logic Lecture 7 Gate Level Minimization
Digital Logic Lecture 7 Gate Level Minimization By Ghada AlMashaqbeh The Hashemite University Computer Engineering Department Outline Introduction. Kmap principles. Simplification using Kmaps. Don tcare
More informationUNIT II. Circuit minimization
UNIT II Circuit minimization The complexity of the digital logic gates that implement a Boolean function is directly related to the complexity of the algebraic expression from which the function is implemented.
More informationModule 7. Karnaugh Maps
1 Module 7 Karnaugh Maps 1. Introduction 2. Canonical and Standard forms 2.1 Minterms 2.2 Maxterms 2.3 Canonical Sum of Product or SumofMinterms (SOM) 2.4 Canonical product of sum or ProductofMaxterms(POM)
More informationVALLIAMMAI ENGINEERING COLLEGE. SRM Nagar, Kattankulathur DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC6302 DIGITAL ELECTRONICS
VALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur603 203 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC6302 DIGITAL ELECTRONICS YEAR / SEMESTER: II / III ACADEMIC YEAR: 20152016 (ODD
More informationDigital Logic Design. Outline
Digital Logic Design GateLevel Minimization CSE32 Fall 2 Outline The Map Method 2,3,4 variable maps 5 and 6 variable maps (very briefly) Product of sums simplification Don t Care conditions NAND and NOR
More informationCOMBINATIONAL LOGIC CIRCUITS
COMBINATIONAL LOGIC CIRCUITS 4.1 INTRODUCTION The digital system consists of two types of circuits, namely: (i) Combinational circuits and (ii) Sequential circuits A combinational circuit consists of logic
More informationSpecifying logic functions
CSE4: Components and Design Techniques for Digital Systems Specifying logic functions Instructor: Mohsen Imani Slides from: Prof.Tajana Simunic and Dr.Pietro Mercati We have seen various concepts: Last
More informationBawar Abid Abdalla. Assistant Lecturer Software Engineering Department Koya University
Logic Design First Stage Lecture No.5 Boolean Algebra Bawar Abid Abdalla Assistant Lecturer Software Engineering Department Koya University Boolean Operations Laws of Boolean Algebra Rules of Boolean Algebra
More informationCh. 5 : Boolean Algebra &
Ch. 5 : Boolean Algebra & Reduction elektronik@fisika.ui.ac.id Objectives Should able to: Write Boolean equations for combinational logic applications. Utilize Boolean algebra laws and rules for simplifying
More informationEECS150 Homework 2 Solutions Fall ) CLD2 problem 2.2. Page 1 of 15
1.) CLD2 problem 2.2 We are allowed to use AND gates, OR gates, and inverters. Note that all of the Boolean expression are already conveniently expressed in terms of AND's, OR's, and inversions. Thus,
More informationLecture 4: Implementation AND, OR, NOT Gates and Complement
EE210: Switching Systems Lecture 4: Implementation AND, OR, NOT Gates and Complement Prof. YingLi Tian Feb. 13, 2018 Department of Electrical Engineering The City College of New York The City University
More informationChapter 2 Combinational Logic Circuits
Logic and Computer Design Fundamentals Chapter 2 Combinational Logic Circuits Part 2 Circuit Optimization Charles Kime & Thomas Kaminski 2008 Pearson Education, Inc. (Hyperlinks are active in View Show
More informationENDTERM EXAMINATION
(Please Write your Exam Roll No. immediately) ENDTERM EXAMINATION DECEMBER 2006 Exam. Roll No... Exam Series code: 100919DEC06200963 Paper Code: MCA103 Subject: Digital Electronics Time: 3 Hours Maximum
More informationDHANALAKSHMI SRINIVASAN COLLEGE OF ENGINEERING AND TECHNOLOGY
DHANALAKSHMI SRINIVASAN COLLEGE OF ENGINEERING AND TECHNOLOGY Dept/Sem: II CSE/03 DEPARTMENT OF ECE CS8351 DIGITAL PRINCIPLES AND SYSTEM DESIGN UNIT I BOOLEAN ALGEBRA AND LOGIC GATES PART A 1. How many
More informationR a) Simplify the logic functions from binary to seven segment display code converter (8M) b) Simplify the following using Tabular method
SET  1 1. a) Convert the decimal number 250.5 to base 3, base 4 b) Write and prove demorgan laws c) Implement two input EXOR gate from 2 to 1 multiplexer (3M) d) Write the demerits of PROM (3M) e) What
More informationR.M.D. ENGINEERING COLLEGE R.S.M. Nagar, Kavaraipettai
L T P C R.M.D. ENGINEERING COLLEGE R.S.M. Nagar, Kavaraipettai 601206 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC8392 UNIT  I 3 0 0 3 OBJECTIVES: To present the Digital fundamentals, Boolean
More informationMidterm Exam Review. CS 2420 :: Fall 2016 Molly O'Neil
Midterm Exam Review CS 2420 :: Fall 2016 Molly O'Neil Midterm Exam Thursday, October 20 In class, pencil & paper exam Closed book, closed notes, no cell phones or calculators, clean desk 20% of your final
More informationCombinational Circuits Digital Logic (Materials taken primarily from:
Combinational Circuits Digital Logic (Materials taken primarily from: http://www.facstaff.bucknell.edu/mastascu/elessonshtml/eeindex.html http://www.cs.princeton.edu/~cos126 ) Digital Systems What is a
More informationCS February 17
Discrete Mathematics CS 26 February 7 Equal Boolean Functions Two Boolean functions F and G of degree n are equal iff for all (x n,..x n ) B, F (x,..x n ) = G (x,..x n ) Example: F(x,y,z) = x(y+z), G(x,y,z)
More informationBawar Abid Abdalla. Assistant Lecturer Software Engineering Department Koya University
Logic Design First Stage Lecture No.6 Boolean Algebra Bawar Abid Abdalla Assistant Lecturer Software Engineering Department Koya University Outlines Boolean Operations Laws of Boolean Algebra Rules of
More informationBOOLEAN ALGEBRA. 1. State & Verify Laws by using :
BOOLEAN ALGEBRA. State & Verify Laws by using :. State and algebraically verify Absorption Laws. (2) Absorption law states that (i) X + XY = X and (ii) X(X + Y) = X (i) X + XY = X LHS = X + XY = X( + Y)
More informationSummary. Boolean Addition
Summary Boolean Addition In Boolean algebra, a variable is a symbol used to represent an action, a condition, or data. A single variable can only have a value of or 0. The complement represents the inverse
More informationObjectives: 1 Bolean Algebra. Eng. Ayman Metwali
Objectives: Chapter 3 : 1 Boolean Algebra Boolean Expressions Boolean Identities Simplification of Boolean Expressions Complements Representing Boolean Functions 2 Logic gates 3 Digital Components 4
More informationwww.vidyarthiplus.com Question Paper Code : 31298 B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER 2013. Third Semester Computer Science and Engineering CS 2202/CS 34/EC 1206 A/10144 CS 303/080230012DIGITAL
More informationLecture (05) Boolean Algebra and Logic Gates
Lecture (05) Boolean Algebra and Logic Gates By: Dr. Ahmed ElShafee ١ Minterms and Maxterms consider two binary variables x and y combined with an AND operation. Since eachv ariable may appear in either
More informationSimplification of Boolean Functions
COM111 Introduction to Computer Engineering (Fall 20062007) NOTES 5  page 1 of 5 Introduction Simplification of Boolean Functions You already know one method for simplifying Boolean expressions: Boolean
More informationCHAPTER2 STRUCTURE OF BOOLEAN FUNCTION USING GATES, KMap and QuineMcCluskey
CHAPTER2 STRUCTURE OF BOOLEAN FUNCTION USING GATES, KMap and QuineMcCluskey 2. Introduction Logic gates are connected together to produce a specified output for certain specified combinations of input
More informationDKT 122/3 DIGITAL SYSTEM 1
Company LOGO DKT 122/3 DIGITAL SYSTEM 1 BOOLEAN ALGEBRA (PART 2) Boolean Algebra Contents Boolean Operations & Expression Laws & Rules of Boolean algebra DeMorgan s Theorems Boolean analysis of logic circuits
More informationChapter 6. Logic Design Optimization Chapter 6
Chapter 6 Logic Design Optimization Chapter 6 Optimization The second part of our design process. Optimization criteria: Performance Size Power Twolevel Optimization Manipulating a function until it is
More informationCombinational Logic Use the Boolean Algebra and the minimization techniques to design useful circuits No feedback, no memory Just n inputs, m outputs
Combinational Logic Use the Boolean Algebra and the minimization techniques to design useful circuits No feedback, no memory Just n inputs, m outputs and an arbitrary truth table Analysis Procedure We
More informationPrinciples of Digital Techniques PDT (17320) Assignment No State advantages of digital system over analog system.
Assignment No. 1 1. State advantages of digital system over analog system. 2. Convert following numbers a. (138.56) 10 = (?) 2 = (?) 8 = (?) 16 b. (1110011.011) 2 = (?) 10 = (?) 8 = (?) 16 c. (3004.06)
More informationCSCI 220: Computer Architecture I Instructor: Pranava K. Jha. Simplification of Boolean Functions using a Karnaugh Map
CSCI 22: Computer Architecture I Instructor: Pranava K. Jha Simplification of Boolean Functions using a Karnaugh Map Q.. Plot the following Boolean function on a Karnaugh map: f(a, b, c, d) = m(, 2, 4,
More information