4M X 4 CMOS DYNAMIC RAM WITH EDO PAGE MODE. Rev. No. History Issue Date Remark

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1 4M X 4 CMOS DYNAMIC RAM WITH EDO PAGE MODE Document Title 4M X 4 CMOS DYNAMIC RAM WITH EDO PAGE MODE Revision History Rev. No. History Issue Date Remark 0.0 Initial issue June 13, 2001 Preliminary 0.1 Modify symbol HE dimensions in TSOP 24L package information July 10, Add -45 grade and modify the AC, DC data November 30, 2001 Add -U type spec. 0.3 Modify DC data and all parts guarantee self-refresh mode June 10, Final spec. release June 18, 2003 Final 1.1 Add Pb-Free order April 23, Delete 24/26L Pb-Free SOJ package type in ordering information October 18, 2004 (October, 2004, Version 1.2) AMIC Technology, Corp.

2 4M X 4 CMOS DYNAMIC RAM WITH EDO PAGE MODE Features Organization: 4,194,304 words X 4 bits Part Identification - A42L2604 (2K Ref.) Single 3.3V power supply/built-in VBB generator Low power consumption - Operating: 80mA (-45 max) - Standby: 1.0mA (TTL), 1.5mA (CMOS), 350µA (Self-refresh current) High speed - 45/50 ns access time - 20/22 ns column address access time - 12/13 ns access time - 18/20 ns EDO Page Mode Cycle Time General Description The A42L2604 is a new generation randomly accessed memory for graphics, organized in a 4,194,304-word by 4- bit configuration. This product can execute Write and Read operation via pin. The A42L2604 offers an accelerated Fast Page Mode cycle with a feature called Extended Data Out (EDO). Industrial operating temperature range: -40 C to +85 C for -U Fast Page Mode with Extended Data Out 2K Refresh Cycle in 32ms Read-modify-write, -only, -before-, Hidden refresh capability TTL-compatible, three-state I/O JEDEC standard packages - 300mil, 24/26-pin SOJ - 300mil, 24/26-pin TSOP type II package This allow random access of up to 2048(2K Ref.) words within a row at a 56/50 MHz EDO cycle, making the A42L2604 ideally suited for graphics, digital signal processing and high performance computing systems. Pin Configuration SOJ TSOP Pin Descriptions VCC I/O0 I/O1 NC A10 A0 A1 A2 A3 VCC A42L2604S 26 VSS VCC I/O0 I/O2 I/O1 A9 NC A8 A10 A7 A0 A6 A1 A5 A2 A4 A3 VSS VCC A42L2604V VSS I/O2 A9 A8 A7 A6 A5 A4 VSS Symbol A0 A10 I/O0 - VCC VSS NC Description Address Inputs (2K product) Data Input/Output Row Address Strobe Column Address Strobe Write Enable Output Enable 3.3V Power Supply Ground No Connection (October, 2004, Version 1.2) 1 AMIC Technology, Corp.

3 Selection Guide Symbol Description Unit trac Maximum Access Time ns taa Maximum Column Address Access Time ns tcac Maximum Access Time ns ta Maximum Output Enable ( ) Access Time ns trc Minimum Read or Write Cycle Time ns tpc Minimum EDO Cycle Time ns Functional Description The A42L2604 reads and writes data by multiplexing an 22- bit address into a 11-bit(2K) row and column address. and are used to strobe the row address and the column address, respectively. A Read cycle is performed by holding the signal high during / operation. A Write cycle is executed by holding the signal low during / operation; the input data is latched by the falling edge of or, whichever occurs later. The data inputs and outputs are routed through 4 common I/O pins, with,, and controlling the in direction. EDO Page Mode operation all 2048(2K) columns within a selected row to be randomly accessed at a high data rate. A EDO Page Mode cycle is initiated with a row address latched by followed by a column address latched by. While holding low, can be toggled to strobe changing column addresses, thus achieving shorter cycle times. The A42L2604 offers an accelerated Fast Page Mode cycle through a feature called Extended Data Out, which keeps the output drivers on during the precharge time (tcp). Since data can be output after goes high, the user is not required to wait for valid data to appear before starting the next access cycle. Data-out will remain valid as long as and are low, and is high; this is the only characteristic which differentiates Extended Data Out operation from a standard Read or Fast Page Read. A memory cycle is terminated by returning both and high. Memory cell data will retain its correct state by maintaining power and accessing all 2048(2K) combinations of the 11-bit(2K) row addresses, regardless of sequence, at least once every 32ms through any cycle (Read, Write) or Refresh cycle ( -only, CBR, or Hidden). The CBR Refresh cycle automatically controls the row addresses by invoking the refresh counter and controller. Power-On The initial application of the VCC supply requires a 200 µs wait followed by a minimum of any eight initialization cycles containing a clock. During Power-On, the VCC current is dependent on the input levels of and. It is recommended that and track with VCC or be held at a valid VIH during Power-On to avoid current surges. (October, 2004, Version 1.2) 2 AMIC Technology, Corp.

4 Block Diagram Control Clocks VBB Generator Vcc Vss Refresh Timer Row Decoder A0~A10 Refresh control Refresh Counter Row Address Buffer Memory Array 4,194,304 X 4 Cells Sense Amps & I/O Data in Buffer Data out Buffer I/O0 to A0~A10 Col. Address Buffer Column Decoder Recommended Operating Conditions (Ta = 0 C to +70 C or -40 C to +85 C) Symbol Description Min. Typ. Max. Unit VCC Power Supply V VSS Input High Voltage V VIH Input High Voltage VCC V VIL Input Low Voltage V (October, 2004, Version 1.2) 3 AMIC Technology, Corp.

5 Truth Table Function Address I/Os Standby H H X X X High-Z Read: Word L L H L Row/Col. Data Out Read L L H L Row/Col. Data Out Write: Word (Early) L L L X Row/Col. Data In Write (Early) L L L X Row/Col. Data In Read-Write L L H L L H Row/Col. Data Out Data In EDO-Page-Mode Read: Hi-Z -First cycle -Subsequent Cycles L L H L H L H H H L H L Row/Col. Col. Data Out Data Out EDO-Page-Mode Write (Early) -First cycle -Subsequent Cycles L L H L H L L L X X Row/Col. Col. Data In Data In EDO-Page-Mode Read-Write -First cycle -Subsequent Cycles L L H L H L H L H L L H L H Row/Col. Col. Data Out Data In Data Out Data In Hidden Refresh Read L H L L H L Row/Col. Data Out Hidden Refresh Write L H L L L X Row/Col. Data In High-Z -Only Refresh L H X X Row High-Z CBR Refresh H L L X X X High-Z Self Refresh H L L H X X High-Z (October, 2004, Version 1.2) 4 AMIC Technology, Corp.

6 Absolute Maximum Ratings* Input Voltage (Vin) V to +4.6V Output Voltage (Vout) V to +4.6V Power Supply Voltage (VCC) V to +4.6V Operating Temperature (TOPR) C to +70 C Storage Temperature (TSTG) C to +150 C Soldering Temperature X Time (TSOLDER) C X 10sec Power Dissipation (PD) W Short Circuit Output Current (Iout) mA Latch-up Current mA *Comments Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of these specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. DC Electrical Characteristics (VCC = 3.3V ± 0.3V, VSS = 0V, Ta = 0 C to +70 C or -40 C to +85 C) Symbol Parameter Min. Max. Min. Max. Unit Test Conditions Notes IIL Input Leakage Current µa 0V Vin Vin + 0.3V Pins not under Test = 0V IOL Output Leakage Current µa DOUT disabled, 0V Vout + VCC ICC1 Operating Power Supply Current ma,u,l and Address cycling; trc = min. 1, 2 ICC2 TTL Standby Power Supply Current ma =U =L =VIH ICC3 Average Power Supply Current, Refresh Mode ma and Address cycling, U =L = VIH, trc = min. 1 ICC4 EDO Page Mode Average Power Supply Current ma = VIL, U,L and Address cycling; tpc = min. 1, 2 ICC5 -before- Refresh Power Supply Current ma, U and L cycling; trc = min. 1 ICC6 ICC7 CMOS Standby Power Supply Current Self Refresh Mode Current ma =U =L = VCC - 0.2V µa = VSS+0.2V All other input high levels are VCC-0.2V or input low levels are VSS +0.2V VOH V IOUT = -2.0mA Output Voltage VOL V IOUT =2.0mA (October, 2004, Version 1.2) 5 AMIC Technology, Corp.

7 AC Characteristics (VCC = 3.3V ± 0.3V, VSS = 0V, Ta = 0 C to +70 C or -40 C to +85 C) Test Conditions: Input timing reference level: VIH/VIL=2.0V/0.8V Output reference level: VOH/VOL=2.0V/0.8V Output Load: 2TTL gate + CL (50pF) Assumed tt=2ns # Std Symbol Parameter Min. Max. Min. Max. Unit Notes tt Transition Time (Rise or Fall) ns 4, 5 1 trc Random Read or Write Cycle Time ns 2 trp Precharge Time ns 3 t Pulse Width 45 10K 50 10K ns 4 t Pulse Width 7 10K 8 10K ns 5 trcd to Delay Time ns 6 6 trad to Column Address Delay Time ns 7 7 trsh to Hold Time ns 8 tcsh Hold Time ns 9 tcrp to Precharge Time ns 10 tasr Row Address Setup Time ns 11 trah Row Address Hold Time ns 12 tclz to Output in Low Z ns 8 13 trac Access Time from ns 6,7 14 tcac Access Time from ns 6, taa Access Time from Column Address ns 7, ta Access Time from ns 17 tar Column Address Hold Time from ns 18 trcs Read Command Setup Time ns 19 trch Read Command Hold Time ns 9 (October, 2004, Version 1.2) 6 AMIC Technology, Corp.

8 AC Characteristics (continued) (VCC = 3.3V ± 0.3V, VSS = 0V, Ta = 0 C to +70 C or -40 C to +85 C) Test Conditions: Input timing reference level: VIH/VIL=2.0V/0.8V Output reference level: VOH/VOL=2.0V/0.8V Output Load: 2TTL gate + CL (50pF) Assumed tt=2ns A42L2604 Series # Std Symbol Parameter Min. Max. Min. Max. Unit Notes 20 trrh Read Command Hold Time Reference to ns 9 21 tral Column Address to Lead Time ns 22 TCOH Output Hold After Low ns 23 toff Output Buffer Turn-Off Delay Time ns 8, tasc Column Address Setup Time ns 25 tcah Column Address Hold Time ns 26 ts Low to High Set Up ns 27 twcs Write Command Setup Time ns twch Write Command Hold Time ns twcr Write Command Hold Time to ns 30 twp Write Command Pulse Width ns 31 trwl Write Command to Lead Time ns 32 tcwl Write Command to Lead Time ns 33 tds Data-in setup Time ns 34 tdh Data-in Hold Time ns 35 tdhr Data-in Hold Time to ns 36 trwc Read-Modify-Write Cycle Time ns 37 trwd to Delay Time (Read-Modify-Write) ns tcwd to Delay Time (Read-Modify-Write) ns tawd Column Address to Delay Time (Read-Modify-Write) ns 11 (October, 2004, Version 1.2) 7 AMIC Technology, Corp.

9 AC Characteristics (continued) (VCC = 3.3V ± 0.3V, VSS = 0V, Ta = 0 C to +70 C or -40 C to +85 C) Test Conditions: Input timing reference level: VIH/VIL=2.0V/0.8V Output reference level: VOH/VOL=2.0V/0.8V Output Load: 2TTL gate + CL (50pF) Assumed tt=2ns # Std Symbol Parameter Min. Max. Min. Max. Unit Notes 40 th Hold Time from ns 41 tp High Pulse Width ns 42 tpc Read or Write Cycle Time (EDO Page) ns tcpa Access Time from Precharge (EDO Page) ns tcp Precharge Time ns 45 tpcm EDO Page Mode RMW Cycle Time ns 46 tcrw EDO Page Mode Pulse Width (RMW) ns 47 tp Pulse Width (EDO Page) K K ns 48 tcsr Setup Time ( -before- ) ns 3 49 tchr Hold Time ( -before- ) ns 3 50 trpc to Precharge Time ns 51 tz Output Buffer Turn-off Delay from ns 8 52 ts pulse width ( C -B-R self refresh) µs 53 trps precharge time ( C -B-R self refresh) ns 54 tchs hold time ( C -B-R self refresh) ns (October, 2004, Version 1.2) 8 AMIC Technology, Corp.

10 Notes: 1. ICC1, ICC3, ICC4, and ICC5 depend on cycle rate. 2. ICC1 and ICC4 depend on output loading. Specified values are obtained with the outputs open. 3. An initial pause of 200µs is required after power-up followed by any 8 cycles before proper device operation is achieved. In the case of an internal refresh counter, a minimum of 8 -before- initialization cycles instead of 8 cycles are required. 8 initialization cycles are required after extended periods of bias without clocks. 4. AC Characteristics assume tt = 2ns. All AC parameters are measured with a load equivalent to two TTL loads and 50pF, VIL (min.) GND and VIH (max.) VCC. 5. VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL. 6. Operation within the trcd (max.) limit insures that trac (max.) can be met. trcd (max.) is specified as a reference point only. If trcd is greater than the specified trcd (max.) limit, then access time is controlled exclusively by tcac. 7. Operation within the trad (max.) limit insures that trac (max.) can be met. trad (max.) is specified as a reference point only. If trad is greater than the specified trad (max.) limit, then access time is controlled exclusively by taa. 8. Assumes three state test load (5pF and a 500Ω Thevenin equivalent). 9. Either trch or trrh must be satisfied for a read cycle. 10. toff (max.) defines the time at which the output achieves the open circuit condition; it is not referenced to output voltage levels. 11. twcs, twch, trwd, tcwd and tawd are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If twcs twcs (min.) and twch twch (min.), the cycle is an early write cycle and data-out pins will remain open circuit, high impedance, throughout the entire cycle. If trwd trwd (min.), tcwd tcwd (min.) and tawd tawd (min.), the cycle is a read-modify-write cycle and the data out will contain data read from the selected cell. If neither of the above conditions is satisfied, the condition of the data out at access time is indeterminate. 12. Access time is determined by the longer of taa or tcac or tcpa. 13. tasc tcp to achieve tpc (min.) and tcpa (max.) values. (October, 2004, Version 1.2) 9 AMIC Technology, Corp.

11 Word Read Cycle trc(1) t(3) tcsh(8) trcd(5) trsh(7) t(4) trad(6) tral(21) tasr(10) trah(11) Address Row Address Column Address tar(17) trcs(18) trch(19) trrh(20) ta(16) tcac(14) taa(15) toff(23) trac(13) tz(51) I/O0 ~ High-Z Valid Data-out tclz(12) (October, 2004, Version 1.2) 10 AMIC Technology, Corp.

12 Word Write Cycle (Early Write) trc(1) t(3) tcsh(8) trcd(5) trsh(7) t(4) tar(17) trad(6) tral(21) tasr(10) trah(11) Address Row Address Column Address twcr(29) tcwl(32) trwl(31) twp(30) twcs(27) twch(28) tdhr(35) I/O0 ~ tds(33) tdh(34) Valid Data-in (October, 2004, Version 1.2) 11 AMIC Technology, Corp.

13 Word Write Cycle (Late Write) trc(1) t(3) tcsh(8) trcd(5) trsh(7) t(4) tar(17) trad(6) tral(21) tasr(10) trah(11) Address Row Address Column Address tcwl(32) trwl(31) twcr(29) twp(30) th(40) tdhr(35) tds(33) tdh(34) I/O0 ~ High-Z Vaild Data-in (October, 2004, Version 1.2) 12 AMIC Technology, Corp.

14 Word Read-Modify-Write Cycle trwc(36) t(3) tcsh(8) trcd(5) trsh(7) tar(17) trad(6) tasr(10) trah(11) Address Row Address Column Address tawd(39) trcs(18) trwd(37) tcwd38) tcwl(32) trwl(31) twp(30) ta(16) tz(51) tcac(14) th(40) taa(15) tds(33) tdh(34) trac(13) I/O0 ~ High-Z tclz(12) Data-out Data-in (October, 2004, Version 1.2) 13 AMIC Technology, Corp.

15 EDO Page Mode Word Read Cycle tp(47) trcd(5) tcsh(8) t(4) tcp(44) t(4) tpc(42) trsh(7) t(4) tasr(10) trad(6) trah(11) tcsh(8) tar(16) tral(21) Address Row Column Column Column trcs(18) trcs(18) trch(19) trcs(18) trch(25) taa(15) tcpa(43) taa(15) trrh(20) ta(16) ta(16) ts(26) trac(13) tcac(14) tp(41) toff(23) tcac(14) tclz(12) tcoh(22) tcac(14) tz(51) tz(51) I/O0 ~ Data-out Data-out Data-out tclz(12) (October, 2004, Version 1.2) 14 AMIC Technology, Corp.

16 EDO Page Mode Early Word Write Cycle tp(47) tcsh(8) tpc(42) trsh(7) trcd(5) t(4) tcp(44) t(4) tcp(44) t(4) tral(21) trad(6) tasr(10) trah(11) Address Row Column Column Column tcwl(32) tcwl(32) tcwl(32) trwl(31) twcs(27) twcs(27) twcs(27) twch(28) twch(28) twch(28) twp(30) twp(30) twp(30) tdh(34) tdh(34) tdh(34) tds(33) tds(33) tds(33) I/O0 ~ Data-in Data-in Data-in (October, 2004, Version 1.2) 15 AMIC Technology, Corp.

17 EDO Page Mode Word Read-Modify-Write Cycle tp(47) trcd(5) tcsh(8) tcrw(46) tcp(44) tcrw(46) tpcm(45) tcp(44) trsh(7) tcrw(46) trad(6) tral(21) tasr(10) trah(11) Address Row Column Column Column tcwl(32) tcwl(32) tcwl(32) trwd(37) trwl(31) trcs(18) tcwd(38) tcwd(38) tcwd(38) twp(30) twp(30) twp(30) tawd(39) tawd(39) tawd(39) ta(16) ta(16) ta(16) th(40) tcac(14) tcpa(43) tcpa(43) taa(15) taa(15) taa(15) tz(51) tz(51) tz(51) I/O0 ~ High-Z trac(13) tds(33) tdh(34) tds(33) tclz(12) tclz(12) tclz(12) Data-out Data-in Data-in Data-out tdh(34) tds(33) Data-in Data-out tdh(34) (October, 2004, Version 1.2) 16 AMIC Technology, Corp.

18 Only Refresh Cycle trc(1) t(3) trpc(50) tasr(10) trah(11) Address Row Note:, = Don't care. Before Refresh Cycle trc(1) t(3) trpc(50) tchr(49) tpc(44) tcsr(48) I/O0 ~ toff(23) High-Z Note:,, Address = Don't care. (October, 2004, Version 1.2) 17 AMIC Technology, Corp.

19 Hidden Refresh Cycle (Word Read) trc(1) trc(1) t(3) t(3) tar(17) trcd(5) trsh(7) tchr(49) U L trad(6) tral(21) tasr(10) trah(11) A0~A8 Row Column trcs(18) trrh(20) taa(15) ta(16) tz(51) tcac(14) toff(23) tclz(12) trac(13) I/O0 ~ I/O15 High-Z Valid Data-out (October, 2004, Version 1.2) 18 AMIC Technology, Corp.

20 Hidden Refresh Cycle (Early Word Write) trc(1) trc(1) t(3) t(3) tar(17) trcd(5) trsh(7) tchr(49) trad(6) tral(21) tasr(10) trah(11) Address Row Column twcs(27) twch(28) twp(30) tds(33) tdh(34) I/O0 ~ Valid Data-in (October, 2004, Version 1.2) 19 AMIC Technology, Corp.

21 EDO Page Mode Read-Early-Write Cycle (Pseudo Read-Modify-Write) tp(47) tcsh(8) tpc(42) tpc(42) trsh(7) trcd(5) t(4) tcp(44) t(4) tcp(44) t(4) tcpr(9) tasr(10) trah(11) trad(6) tral(21) Address Row Column Column Column trch(19) trcs(18) twcs(27) twch(28) taa(15) trac(13) taa(15) tcap(43) tds(33) tdh(34) tcac(14) tcac(14) ta(16) tcoh(22) I/O0 ~ Data-out Data-out Data-in (October, 2004, Version 1.2) 20 AMIC Technology, Corp.

22 Self Refresh Mode ts(52) trps(53) trpc(50) tcsr(48) tchs(54) U L tcp(44) tasr(10) A0 ~ A10 ROW COL toff(23) I/O0 ~ High-Z Note:, = Don't care. Self Refresh Mode. a. Entering the Self Refresh Mode: The A42L2604 Self Refresh Mode is entered by using before cycle and holding and signal low longer than 100µs. b. Continuing the Self Refresh Mode: The Self Refresh Mode is continued by holding low after entering the Self Refresh Mode. It does not depend on being high or low after entering the Self Refresh Mode continue the Self Refresh Mode. c. Exiting the Self Refresh Mode: The A42L2604 exits the Self Refresh Mode when the signal is brought high. (October, 2004, Version 1.2) 21 AMIC Technology, Corp.

23 Capacitance (f = 1MHz, Ta = Room Temperature, VCC = 3.3V ± 10%) Symbol Signals Parameter Max. Unit Test Conditions CIN1 A0 A10 5 pf Vin = 0V CIN2,, Input Capacitance 7 pf Vin = 0V, CI/O I/O0 - I/O Capacitance 7 pf Vin = Vout = 0V Ordering Codes Part No. Access Time (ns) Package Refresh Cycle Self-Refresh A42L2604S-45 24/26L SOJ 2K Yes A42L2604V-45 24/26L TSOP(II) 2K Yes A42L2604V-45U 45 24/26L TSOP(II) 2K Yes A42L2604V-45F 24/26L Pb-Free TSOP(II) 2K Yes A42L2604V-45UF 24/26L Pb-Free TSOP(II) 2K Yes A42L2604S-50 24/26L SOJ 2K Yes A42L2604V-50 24/26L TSOP(II) 2K Yes A42L2604V-50U 50 24/26L TSOP(II) 2K Yes A42L2604V-50F 24/26L Pb-Free TSOP(II) 2K Yes A42L2604V-50UF 24/26L Pb-Free TSOP(II) 2K Yes Note: -U is for industrial operating temperature range. (October, 2004, Version 1.2) 22 AMIC Technology, Corp.

24 Package Information SOJ 24/26L (300mil) Outline Dimensions unit: inches/mm 24 D E1 E Pin 1 Identifier 12 A2 A C A1 A A - y - S b b2 e E2 θ Seating Plane y Symbol Dimensions in inches Dimensions in mm Min Nom Max Min Nom Max A A A b b C D E E E e S θ Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E1 does not include resin fins. 3. Dimension E2 is for PC Board surface mount pad pitch design reference only. 4. Dimension S includes end flash. (October, 2004, Version 1.2) 23 AMIC Technology, Corp.

25 Package Information TSOP 24/26L (TYPE II) (300mil) Outline Dimensions unit: inches/mm E HE L1 θ 1 D 12 A2 A c S e B D y A1 L1 L Symbol Dimensions in inches Dimensions in mm Min Nom Max Min Nom Max A A A B c D E e HE L L S y θ Notes: 1. Dimension D&E do not included interlead flash. 2. Dimension B does not included dambar protrusion / intrusion. 3. Dimension S includes end flash. (October, 2004, Version 1.2) 24 AMIC Technology, Corp.

4M X 4 CMOS DYNAMIC RAM WITH EDO PAGE MODE. Rev. No. History Issue Date Remark

4M X 4 CMOS DYNAMIC RAM WITH EDO PAGE MODE Document Title 4M X 4 CMOS DYNAMIC RAM WITH EDO PAGE MODE Revision History Rev. No. History Issue Date Remark 0.0 Initial issue July 23, 2003 1.0 Remove 24/26-pin