1. DESCRIPCION EN VHDL DE UN BIESTABLE D SINCRONO POR FLANCO ASCENDENTE CON RESET SINCRONO
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1 INGENIERIA ELECTRONICA Cátedra Técnicas Digitales I 3º Año DESCRIPCION EN VHDL 1. DESCRIPCION EN VHDL DE UN BIESTABLE D SINCRONO POR FLANCO ASCENDENTE entity biestabled is Port ( reloj : in STD_LOGIC; reset : in STD_LOGIC; D : in STD_LOGIC; Q : out STD_LOGIC end biestabled; architecture Behavioral of biestabled is process (reloj) Q <= '0'; Q <= D; 2. DESCRIPCION EN VHDL DE UN BIESTABLE T SINCRONO POR FLANCO ASCENDENTE entity biestablet is Técnicas Digitales I Página 1 de 5
2 Port ( reloj : in STD_LOGIC; T : in STD_LOGIC; Q : out STD_LOGIC; reset: in STD_LOGIC end biestablet; architecture Behavioral of biestablet is signal Dp, Qp : STD_LOGIC; process (reloj) Qp <= '0'; Qp <= Dp; --- Lógica del estado siguiente with T select Dp <= Qp when '0', not (Qp) when others; --- Lógica de salida Q <= Qp ; 3. DESCRIPCION EN VHDL DE UN BIESTABLE JK SINCRONO POR FLANCO ASCENDENTE entity biestablejk is Port ( reloj : in STD_LOGIC; reset : in STD_LOGIC; J,K : in STD_LOGIC; Q : out STD_LOGIC end biestablejk; architecture Behavioral of biestablejk is signal Qp,Dp : STD_LOGIC; signal JK : STD_LOGIC_VECTOR (1 downto 0 Técnicas Digitales I - Página 2 de 5
3 process (reloj) Qp <= '0'; Qp <= Dp; --- Lógica del estado siguiente JK <= J&K ; with JK select DP <= Qp when "00", '0' when "01", '1' when "10", not (Qp) when others; ---- Lógica de salida Q <= Qp ; 4. SUMADOR DE DOS NUMEROS DE 4 BITS C/U (VHDL) a. MODULO SUMADOR DE 4 BITS use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.ALL; entity sumador_4bits is Port ( Ent1 : in STD_LOGIC_VECTOR (3 downto 0 Ent2 : in STD_LOGIC_VECTOR (3 downto 0 Resultado : out STD_LOGIC_VECTOR (3 downto 0 Carry : out STD_LOGIC end sumador_4bits; architecture Behavioral of sumador_4bits is signal C1,C2,C3 : std_logic; COMPONENT sumador_medio PORT ( A : IN std_logic; B : IN std_logic; Cout : OUT std_logic; Suma : OUT std_logic ) ; END COMPONENT Técnicas Digitales I - Página 3 de 5
4 COMPONENT sumador_completo PORT ( A : IN std_logic; B : IN std_logic; Cin : IN std_logic; Cout : OUT std_logic; Suma : OUT std_logic ) ; END COMPONENT Inst_sumador_medio : sumador_medio PORT MAP ( A => Ent1(0), B => Ent2(0), Cout => C1, Suma => Resultado(0) Inst_sumador_completo1 : sumador_completo PORT MAP ( A => Ent1(1), B => Ent2(1), Cin => C1, Cout => C2, Suma => Resultado(1) Inst_sumador_completo2 : sumador_completo PORT MAP ( A => Ent1(2), B => Ent2(2), Cin => C2, Cout =>C3, Suma => Resultado(2) Inst_sumador_completo3 : sumador_completo PORT MAP ( A => Ent1(3), B => Ent2(3), Cin =>C3, Cout =>Carry, Suma =>Resultado(3) b. MODULO SUMADOR MEDIO Técnicas Digitales I - Página 4 de 5
5 entity sumador_medio is Port ( A : in STD_LOGIC; B : in STD_LOGIC; Suma : out STD_LOGIC; Cout : out STD_LOGIC end sumador_medio; architecture Behavioral of sumador_medio is SUMA <= (B xor A) ; COUT <= (B and A) ; c. MODULO SUMADOR TOTAL (1 Instancia) entity sumador_completo is Port ( A : in STD_LOGIC; B : in STD_LOGIC; Cin : in STD_LOGIC; Cout : out STD_LOGIC; Suma : out STD_LOGIC end sumador_completo; architecture Behavioral of sumador_completo is SUMA <= (B xor A) xor CIN ; COUT <= (B and A) or (( B xor A ) and CIN ) ; o o o O o o o Técnicas Digitales I - Página 5 de 5
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