3D IC Packaging 3D IC Integration. John H. Lau ASM Pacific Technology Kung Yip Street, Kwai Chung, Hong Kong ,

Transcription

1 3D IC Packaging 3D IC Integration John H. Lau ASM Pacific Technology Kung Yip Street, Kwai Chung, Hong Kong , CPMT Distinguish Lecture, San Diego Chapter, February 23,

2 Contents 3D IC Packaging (without TSV) Stack Chips by Wire Bonding Package-on-Package (PoP) Chip-to-Chip Interconnects Embedded Fan-Out Wafer Level Package (ewlp) Infineon, Freescale, TSMC s ewlp Infineon, ASE, Amkor, STATSchippac, STMicroelectroinc s 3D ewlp 3D IC Integration Memory-Chip Stacking in Production Hybrid Memory Cube (HMC) Intel s Knight s Landing with HMC Fujitsu s Supercomputer with HMC Altera s FPGA with HMC Wide I/O DRAM and Wide I/O 2 High Bandwidth Memory (HBM) Samsung s Widcon Technology for Mobile Products 2.5D IC Integration Xilinx/TSMC s Interposer Altera/TSMC s Interposer ITRI s Interposer for 3D IC Integration Supply Chains and Ownerships for 2.5D/3D IC Integration Recent Advances in Package Substrates Coreless Substrates Thin-Film Layer on Build-up Package Substrate Embedded Interposer/Bridge 3D MEMS and IC Integration 3D CIS and IC Integration Summary and Q&A 2

3 Maturity 3D Integration Technologies Don t use TSV Use TSV technology 3D IC Packaging 3D IC Integration 3D Si Integration Mass Production Full swing production for memories. Volume production for mobile products. Commercia -lization Applied R&D Basic/ Applied R&D Die Stacking with wire bonds Package on Package (PoP) Stacking C2C, C2W, W2W Stacking Active applied R&D is undertaken by Research Institutes. TSV cost is the key. In the phase of industrialization. Still in upstream research, technological challenges such as KGD, yield & device architecture and EDA are key issues. W2W Stacking Technology 3 Lau, IEEE-ECTC PDC, 2009

4 3D IC Packaging (No TSV) Memory Stacked with Wirebonds Solder Bumped Flip Chip Assembly Package-on-Package (PoP) Chip-to-Chip Interconnects Embedded Fan-Out Wafer Level Package (ewlp) 4

5 Memory Stacked with Wirebonds 5

6 Memory chips stacking by die attach and wire bonding [1994, nchip] Memory chips Die attach material Substrate Chip 3 Chip 2 Chip 1 Bevel or Notch Bond wires 6

7 Samsung s Eight-Stack Flash in Apple s iphone 4s SK Hynix s MLC (Multi Level Cell) 8GB (Gigabyte) NAND Flash in Apple s iphone 5s Wire bonding Nand Flash chips FBGA (Fine-pitch Ball Grid Array) Molding 7

8 Amkor s 3D IC Packaging with Cu Wires Top Chip Cu Wires Bottom Chip Substrate 8

9 Package-on-Package (PoP) 9

10 PoP (Package-on-Package) Format (Apple A7 Application Processor Chipset) Apple s A7 processor Elpida s 1GB LPDDR Build-up package substrate 10

11 Top-View and Cross Section View of the PoP (for Mobile DRAM and A8 Processor) inside iphone 6 Plus Top-side of the bottom PoP (426-ball) Elpida s 1GB LPDDR3 (EDF8164A3PM-GD-F) Application Processor Package Substrate for LPDDR3 Package Substrate for A8 processor Not-to-scale Apple s application processor (POXY99001)

12 Top-View and Cross Section View of the PoP (for Mobile DRAM and Application Processor) iphone 6 Plus iphone 6S Elpida s 1GB LPDDR3 (EDF8164A3PM-GD-F) 2GB LPDDR4 Package Substrate for LPDDR3 Package Substrate for LPDDR4 Package Substrate for A8 processor Package Substrate for A9 processor A8 application processor fabricated by 20nm process Not-to-scale A9 application processor fabricated by 14/16nm Fin-FET process

13 Samsung s Next Generation High-End Smartphones LPDDR3 Exynos Microprocessor Conventional Solution Flash chip-set PCB epop Solution epop (Flash and LPDDR3 combination) epop Exynos Microprocessor A 40% PCB saving! PCB

14 Chip-to-Chip Interconnects 14

15 IME s Stacked Silicon Module Attached on a Substrate Heat spreader/sink (optional) Microbump Mother Chip Daughter Chip Solder Bump Rigid or Flex Substrate Solder Ball PCB Chip-to-Chip and Face-to-Face Lim, Lau, et.al., Process Development and Reliability of Microbumps, IEEE/EPTC, 2008, pp Also, IEEE Transactions on CPMT, 2010, pp

16 SONY's CXD53135GG used a 5-chip stack. (Wire bonding and solder bump) Solder bumps Wire bonds Face-to-face (Chip-to-chip) Processor: 250μm. All the other chips: Samsung 2-Gb mobile DDR2 SDRAMs 100 to 125μm a spacer die Samsung 2-Gb mobile DDR2 SDRAMs Samsung 1-Gb wide I/O SDRAM Processor 16

17 Amkor s POSSUM assembly where the daughter die (e.g., memory) is mounted face-to-face with the larger mother die (e.g., SoC). The mother die is then flip chip mounted onto a substrate Cu Pillar Micro-bumps Daughter Die 17

18 Amkor s Double POSSUM multi-stacked die configurations without the use of TSVs Daughter Die Grandma Die PCB Package Substrate Cu Pillar Micro-bumps with SnAg solder caps Mother Die SnAg Cu Sutanto, J., POSSUM TM, Die Design as a Low Cost 3D Packaging Alternative, 3D Packaging, Issue No. 25, November 2012, pp

19 Amkor s POSSUM Package showing Altera s FPGA and ASIC Package Substrate FPGA 40μm-pitch Cu-pillar + solder cap microbumps ASIC 200μm-pitch Cupost + solder Solder balls Heat spreader cap FPGA Package Substrate Solder balls ASIC Heat spreader cap FPGA Package Substrate ASIC Lau Package Substrate FPGA ASIC 40μm-pitch Cu-pillar + solder cap microbumps 200μm-pitch Cupost + solder Xie, J., and D. Patterson, Realizing 3D IC Integration with Face-to-Face Stacking, Chip Scale Review, May-June Issue, 2013, 19 pp

20 Embedded Fan-Out Wafer Level Package (ewlp) 20

21 Infineon s Embedded Wafer-Level Test for KGD Ball Grid Array (ewlb) Molded reconfigured wafer Fan-Out Area (Mold) Chip Redistribution Layer (RDL) Schematic process flow for a fan-out wafer-level package Brunnbauer, et.al., An Embedded Device Technology Based on a Molded Reconfigured Wafer, IEEE/ECTC, 2006, pp

22 a) Laminate Carrier, b) Pick and Place, c) Molding, d) Release Tape, and e) Peal Tape 2-side tape Carrier Chip face-down Molding Infineon picked a modified, commercially available tape, which is equipped with a thermorelease layer. It is loosing its adhesive properties once it is heated above a specific temperature, which is higher than any processing temperature before. Peal tape ECTC

23 Infineon was the First Company to Commercialize its own ewlb Packaging Technology in an LGE cell-phone in early 2009 Mold Baseband SoC PCB RDLs Solder ball Infineon s chip is a wireless baseband SoC with multiple integrated functions (GPS, FM radio, BT ). The same ewlb product has also been in production in Nokia handsets since LGE (wireless baseband), Samsung (baseband modem), and Nokia (baseband modem and RF transceiver) have used Infineon s ewlb in their cell phone products. Infineon ewlb (wireless operation acquired by Intel in 2011) Intel RF IC 5 mm x 5 mm x 0.67 mm with 139 I/Os and 0.4mm ball pitch Intel LTE analog baseband 23

24 Freescale s Redistributed Chip Package (RCP) Place die active side down on substrate and encapsulated with a silica-filled epoxy molding compound Remove substrate and turn the whole around Redistribute signal, power and ground 200mm RCP panel with 82 17mmx17mm 208 I/O packages Deposit BGA solder balls Saw panel into individual package A 208 I/O 13mmx13mm PBGA with 0.65mm pitch can be shrunk to a 9mmx9mm RCP with 0.5mm pitch Keser, et.al., The Redistributed Chip Package: A Breakthrough for Advanced Packaging, IEEE/ECTC, 2007, pp

25 Fan-Out ewlp (Embedded Wafer-Level Packaging) Solder balls Pads RDLs KGD 25

26 Embedded Fan-Out Wafer Level Package (ewlp) vs. PBGA (Plastic Ball Grid Array) Fan-out area (Molded Compound) Face-down Chip Redistribution layer (RDL) Solder Balls Underfill Molded Compound Face-down Chip Substrate Solder Balls Solder Bumps Eliminate solder bumps, underfill, and package substrate. Lower Profile! 26

27 Companies who are Manufacturing/Working on ewlp Infineon s Embedded Wafer-Level Ball Grid Array (ewlb) Package licensed by ASE, STATS ChipPAC, NANIUM, STMicroelectronics Freescale s Redistributed Chip Package (RCP) licensed by NEPES TSMC s Integrated Fan-Out Wafer-Level Package (InFO-WLP) ASE s 3D Fan-Out Wafer-Level PoP (FOPOP) AMKOR s Wafer-Level Fan-Out (WLFO) Package SPIL s Panel Fan-out (P-FO) Package STATSChipPAC s Embedded Wafer Level PoP (ewlb-pop) PTI (NEPES) Fan-Out Wafer-Level Package (FOWLP (RCP)) J-DEVICES Wafer-Level Fan-Out Package (WFOP) ADL Engineering s Panel Wafer-Level BGA Package (pwlp) STMicroelectronics Embedded Wafer Level LGA (ewll) NANIUM s Fan-Out Wafer-Level Package (FO-WLP) DECA s Fan-Out Wafer-Level Packaging (FOWLP) Embedded Fan-Out Wafer-Level Package (ewlp) 27

28 TSMC InFO-WLP (Integrated Fan-Out WLP) At the TSMC Technology Symposium in San Jose, CA in April 2014, TSMC announced the latest InFO-WLP platforms: 8mm x 8mm is targeted at RF and WiFi chips 15mm x 15mm is targeted at application processor and baseband chips 25mm x 25mm could be applied to GPU and networking chips 28

29 High-Performance Integrated Fan-Out Wafer Level Packaging (InFO-WLP): Technology and System Integration Christianto C. Liu, Shuo-Mao Chen, Feng-Wei Kuo, Huan-Neng Chen, En-Hsiang Yeh, Cheng-Chieh Hsieh, Li-Hsien Huang, Ming-Yen Chiu, John Yeh, Tsung-Shu Lin, Tzu-Jin Yeh, Shang-Yun Hou, Jui-Pin Hung, Jing-Cheng Lin, Chewn-Pu Jou, Chuei-Tang Wang, Shin-Puu Jeng, Douglas C.H. Yu Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, Taiwan, chris IEEE/IEDM2012

30 Transceiver Transceiver Thermal Management between PBGA and InFO-WLP of Baseband Chip Set (TSMC Results) Baseband Processor PBGA Baseband Processor InFO-WLP Not-to-Scale

31 Thermal Result between PBGA and InFO-WLP PBGA Max. Tem = 90.5 o C Thermal resistant = 32.5 o C/W InFO-WLP Max. Tem = 81.5 o C Thermal resistant = 28.0 o C/W First, omission of the substrate layer in InFO-WLP reduces both form factor and chip-to-board thermal path, the latter especially vital in applications without heat sinks where heat primarily travels towards the board. Second, junction-to-ambient thermal path is reduced with InFO- WLP s more efficient multi-chip packaging. Third, reduced die separation in InFO-WLP improves lateral heat spreading, as shown by the more uniform heat distribution among the dies. Overall, thermal resistance of InFO-WLP technology is about 14% better than conventional MCM (28.0 versus 32.5 o C/W). Here, the difference in thermal resistance translates to a 9.0 o C reduction in maximum temperature.

32 3D ewlb Horizontal and Vertical Interconnects for Integration of Passive Components M. Wojnowski1, G. Sommer1, K. Pressel2, G. Beer2 1Infineon Technologies AG, Am Campeon 1-12, Neubiberg, Germany 2Infineon Technologies AG, Wernerwerkstraße 2, Regensburg, Germany Chip Through Encapsulant Via (TEV) Mold Compound RDLs Chip 32 IEEE/ECTC2013

33 3D IC Packaging: PoP Chip Through Encapsulant Via (TEV) Mold Compound RDLs Chip 33

34 Through Encapsulant Via (TEV) Laser Drilled Through Encapsulant Via ( µm) Sputter the Ti/Cu + Cu plating 34

35 STMicroelectronics 3D ewlb Chip 1 Chip 2 Chip 3 Chip 1 Chip 2 35

36 ASE s Double Sided 3D FOWLP Package on Package (FOPOP) RDLs MC Chip Top Package Through Mold Via Chip MC Bottom Package RDLs SEMICON West

37 AMKOR s Wafer-Level Fan-Out (WLFO) Package Wire Bonds Memory Chips Chip Solder Bump Redistribution Layers Substrate Through Mold Vias 3D Packaging, November

38 STATSChipPac s 3D IC Packaging 38

39 Maturity 3D Integration Technologies Don t use TSV Use TSV technology 3D IC Packaging 3D IC Integration 3D Si Integration Mass Production Full swing production for memories. Volume production for mobile products. Commercia -lization Applied R&D Basic/ Applied R&D Die Stacking with wire bonds Package on Package (PoP) Stacking C2C, C2W, W2W Stacking Active applied R&D is undertaken by Research Institutes. TSV cost is the key. In the phase of industrialization. Still in upstream research, technological challenges such as KGD, yield & device architecture and EDA are key issues. W2W Stacking Technology 39 Lau, IEEE-ECTC PDC, 2009

40 TSV (Through-Silicon Via) 40

41 TSV (Through-Silicon Via) William Shockley (co-invented the transistor) filed a patent, Semiconductive Wafer and Method of Making the Same on October 23, 1958 and was granted the US patent (3,044,909) on July 17, William Shockley (1956 Nobel laureate) Deep Pits (Holes), We call TSV today 41

42 Intel s TSV (Through-Silicon Via) for the Shortest Chip-to-Chip Interconnects A four stack wire-bonded die package Wirebonds Wirebonds are replaced by TSVs Wire TSV Microbumps Thin chips Advantages: Smaller formfactor Low power consumption Wider bandwidth Better performance 42 Lau, Reliability of 3D IC Interconnects, 2011

43 3D IC Integration Memory chip stacking Wide I/O DRAM, Wide I/O 2, or Hybrid Memory Cube (HMC) High Bandwidth Memory (HBM) 43

44 3D IC Integration (The right thing to do!) Said the 1965 Nobel Physics laureate, Richard Feynman at the Gakushuin University (Tokyo) in 1985: Another direction of improvement (of computing power) is to make physical machines three dimensional instead of all on a surface of a chip (2D). That can be done in stages instead of all at once you can have several layers and then add many more layers as time goes on. Thin Chip TSV Micro Bumps 44

45 3D IC Integration (The right thing to do!) Thin Chip TSV Micro Bumps TSVs straight through the same memory chips to: enlarge the memory capacity lower the power consumption increase the bandwidth lower the latency (enhance electrical performance) reduce the form factor will be the major applications of 3D IC Integration! 45

46 Potential Applications of 3D IC Integration Memory-Chip Stacking DRAM or NAND Flash stacking with TSVs on organic substrate Over molding the DRAMs or NAND Flash Wide I/O DRAM (Hybrid Memory Cube) DRAM stacking with TSVs on Logic Controller with TSVs Over molding the DRAMs Wide I/O Interface (2.5D IC Integration) TSV-less chips on a device-less wafer (interposer) with TSVs Underfill is needed between chips and the interposer Organic Package Substrate PCB Underfill is needed between the active/passive TSV interposer and the organic substrate 46

47 Memory chip stacking 47

48 Samsung s 3D Stacking with TSV (Through Silicon Via) 16Gb Flash memory (8 x 2Gb) 560μm TSV Micro bump Thin Chip Wafer before back-grinding 8-stack chips (50μm each) connected with TSV and microbumps 720μm 560μm 48

49 Samsung Mass-Produces Industry's First TSV-based DDR4 DRAM (August 27, 2014) Server Farm The 64GB DDR4 DRAM module consists of 36 DDR4 DRAM chips, each of which consists of four 4-gigabit (Gb) DDR4 DRAM dies. Use Samsung s 20nm process technology and 3D TSV packaging technology. Perform twice as fast as a module that uses wire bonding packaging, while consuming approximately half the power. Samsung 49

50 Potential Applications of 3D IC Integration Memory-Chip Stacking DRAM or NAND Flash stacking with TSVs on organic substrate Over molding the DRAMs or NAND Flash Wide I/O DRAM (Hybrid Memory Cube) DRAM stacking with TSVs on Logic Controller with TSVs Over molding the DRAMs Wide I/O Interface (2.5D IC Integration) TSV-less chips on a device-less wafer (interposer) with TSVs Underfill is needed between chips and the interposer Organic Package Substrate PCB Underfill is needed between the active/passive TSV interposer and the organic substrate 50

51 Hybrid Memory Cube (HMC) 51

52 Hybrid Memory Cube (HMC) Over-Mold Underfill Microbump TSV TSV Organic Substrate DRAMs Logic Controller

53 Hybrid Memory Cube (HMC) The HMC consortium already has 8 members: Micron Samsung Altera ARM IBM Open-Silicon SK Hynix Xilinx DRAM Layers (Memory cube) Logic Controller The SPEC was published on April 2, 2013 and is primarily targeted at: HPC (high performance computing) Networking Energy, Wireless communications Transportation Security High-end servers More than 120 adopters! 53

54 Hybrid Memory Cube (HMC) Architecture Each DRAM die is divided into 16 "cores" and then stacked. The logic base is at the bottom, with 16 different logic segments, each segment controlling four (or eight) DRAMs that sit on top. This type of memory architecture supports more DRAM I/O pins and, therefore, more bandwidth (as high as 400GB/s). According to the Hybrid Memory Cube Consortium, a single HMC can deliver more than 15X the performance of a DDR3 module and consume 70% less energy per bit than DDR TSVs on each DRAM 54

55 55

56 Hybrid Memory Cube DRAM Layers (Memory cube) Micron fabricate the memory cube Logic Controller 56

57 Hybrid Memory Cube DRAM Layers (Memory cube) Logic Controller IBM fabricate the Logic Controller 57

58 Micron s First HMC Sample Shipped in the Last Week of September 2013 DRAM Stack Package Substrate The hybrid memory cube is a 4- DRAM (each one with TSVs) on a logic controller (which size is slightly larger than the DRAMs) with TSVs The hybrid memory cube is on an organic package substrate. The TSV-DRAM is ~50-μm thick. The TSV-DRAM is with 20-μm (tall) Cu pillar + solder cap. The memory cube is assembled one DRAM at a time with thermal compression bonding. The heat dissipation is from 10W to 20W. TSV diameter ~ 5 to 6-μm. Volume production will be in next summer. 58

59 Altera s Stratix V FPGA with Micron HMC Stratix V FPGA 10/100/1000 Ethernet Connectors ATX Form Factor Hybrid Memory Cube (HMC) ATX Power Supply Connector By providing equivalent bandwidth of greater than eight (8) DDR DIMMs using a single HMC device. Altera White Paper, Addressing Next-Generation Memory Requirements Using Altera FPGAs and HMC Technology, Altera Corporation, January

60 Rik Myslewski, Intel teams with Micron on next-gen many-core Xeon Phi with 3D DRAM Introduces new 'fundamental building 60 block of HPC systems' with Intel Omni Scale Fabric, Posted in HPC, June Intel s Knight s Landing with 8 HMC Fabricated by Micron (2015 production) 5X the bandwidth vs. GDDR5 Up to 16GB One-third the footprint Half the energy per bit Managed memory stack for optimal levels of reliability, availability and serviceability Hybrid Memory Cube (HMC)

61 Fujitsu s Tofu2 integrated Components: SPARC64 Xifx and CPU Memory Board Three CPUs 3 x 8 Hybrid Memory Cubes (HMCs) core CPU Hybrid Memory Cube (HMC) SPARC64 Xifx CPU Memory Board Yoshida, SPARC64 Xifx: Fujitsu s next generation processor for HPC, Hot Chips: A Symposium on High Performance Chips, August 11,

62 Wide I/O DRAM 62

63 Wide I/O Single Date Rate JEDEC Standard (JESD229), December 2011 Target: 1mm Micron s Suggestion Target: 10mmx10mm Max. The minimum determined by contact grid TSVs Contact Grid TSVs Face-down Face-up Memory Cube with TSVs SoC with TSVs Solder Balls (a) C4 Bumps (b) 63

64 Wide I/O 2 64

65 JEDEC Standard - Wide I/O 2 (JESD229-2, Wide I/O 2, August 29, 2014) 40µm 40µm 2880µm 1000µm 120µm 200µm

66 HIGH Bandwidth Memory (HBM) 66

67 High Bandwidth Memory (HBM) DRAM (Mainly for Graphic applications) JEDEC Standard (JESD235), October 2013 HBM is designed to support bandwidth from 128GB/s to 256GB/s Hynix s HMC TSV/RDL Interposer GPU/CPU/SoC TSV HBM Interface HBM DRAM Optional Base Chip Organic Package Substrate PCB PCB Underfill is needed between the interposer and the organic substrate. Also, underfill is needed between the interposer and the GPU/CPU and the memory cube 67

68 Memory Stacking with TSVs Memory Structure Bandwidth (GBps) Voltage (V) Standard Applications RDIMMs DDR4 Servers, Cloud, data center, etc. Wide IO JESD229-2 High-end smartphones HMC 160 to HMC SPEC High-end servers, networking, graphics, HPC, FPGA, etc. HBM 128 to JESD235 High-end graphics, networking, HPC, etc.

69 Samsung s Widcon (wide I/O connection) Technology 69

70 Top-View and Cross Section View of the PoP (for Mobile DRAM and A8 Processor) inside iphone 6 Plus Top-side of the bottom PoP (426-ball) Elpida s 1GB LPDDR3 (EDF8164A3PM-GD-F) Application Processor Package Substrate for LPDDR3 Package Substrate for A8 processor Not-to-scale Apple s application processor (POXY99001)

71 Mobile Application Processor (AP) Chip Set (AP + LPDDR3) (PoP vs. 3D IC Integration) Wide I/O DRAMs PoP 3D IC Integration Microbump TSV Wide I/O DRAMs Package Substrate for LPDDR3 AP AP Package Substrate for AP Package Substrate for AP Chip Set Samsung s Widcon Technology Very low profile Widest memory bandwidth Lower power consumption

72 Samsung s Widcon Technology vs. PoP

73 Samsung s Widcon Technology vs. PoP

74 2.5D IC Integration 74

75 Potential Applications of 3D IC Integration Memory-Chip Stacking DRAM or NAND Flash stacking with TSVs on organic substrate Over molding the DRAMs or NAND Flash Wide I/O DRAM (Hybrid Memory Cube) DRAM stacking with TSVs on Logic Controller with TSVs Over molding the DRAMs Wide I/O Interface (2.5D IC Integration) TSV-less chips on a device-less wafer (interposer) with TSVs Underfill is needed between chips and the interposer Organic Package Substrate PCB Underfill is needed between the active/passive TSV interposer and the organic substrate 75

76 On October 21, 2013 Xilinx and TSMC have jointly announced production release of the Virtex-7 HT family, what the pair claims is the industry's first heterogeneous 3D ICs in production. 2FPGAs TSV/RDL Interposer Transceiver Organic Package Substrate The Xilinx Virtex-7 HT FPGAs feature up to sixteen, 28Gbps and seventy-two, 13.1Gbps transceivers. In addition to the Virtex-7 HT FPGAs, two other homogeneous devices in the 3D IC family have been in volume production since early 2013 Virtex T and Virtex-7 X1140T series. 4 FPGAs TSV/RDL Interposer Organic Package Substrate 76

77 Xilinx/TSMC s 2.5D IC Integration with FPGA PTH Build-up Layers Chip Core Package Substrate Chip Interposer C4 Bumps Devices (Cannot see) Metal Layers Metal Contacts Si Solder Balls Micro Bump Cu Pillar Solder 4RDLs Interposer TSV The package substrate is at least (5-2-5) RDLs: 0.4μm-pitch line width and spacing Each FPGA has >50,000 μbumps on 45μm pitch Interposer is supporting >200,000 μbumps 77

78 Xilinx s Passive Interposers with TSV and RDL for Wide I/O Interface in FPGA Products For better manufacturing yield (to save cost), a very large SoC has been sliced into 4 smaller chips (2011) (10,000+) With 4 RDLs Lau 78 Lau, IEEE/ECTC2011 3D IC Integration PDC

79 Altera/TSMC s 2.5D IC Integration with FPGA Interposer C4 Bumps Chip Build-up Layers Package Substrate Solder Cu Pillar Solder Balls The package substrate is at least (6-2-6) Interposer TSV RDLs 4RDLs on top of the interposer and there isn t any at the bottom 79

80 2.5D IC Integration (Interposers) Underfill UBM Cu Pillar Chip 1 Chip 2 Solder RDLs (Redistribution layers) Underfill TSV RDLs for lateral communications Si Interposer UBM Solder Bumps Package Substrate Build-up Layers Solder Balls Not-to-scale 80

81 Thus, passive TSV/RDL interposers are for extremely finepitch, high-i/o, high-performance, and high-density semiconductor IC applications. 81

82 Recent Advances in Package substrates Coreless Substrates Build-Up Package Substrates

83 Coreless Substrates 83

84 Comparison between the Substrate with Build-up Layers and Coreless Substrate Conventional Build-up Package substrate Chip Underfill Bump Build-up Layers Core Build-up Layers Filled Micro Via Coreless Package substrate Chip Underfil Bump l Build-up Layers Layers Filled Micro Via Low Profile: Good for mobile products 84

85 Coreless Substrates Advantages Lower cost by eliminating the core Better electrical performance (good high-speed transmission characteristic) Higher wiring ability (by eliminating the core) Smaller form factor Disadvantages Larger warpage (because of low rigidity) New manufacturing infrastructure is necessary Easier to have laminate chipping Poor solder joint yield 85

86 Build-up Package Substrates 86

87 Development of Organic Multi Chip Package for High Performance Application N. Shimizu, W. Kaneda, H. Arisaka, M. Koizumi, S. Sunohara, A. Rokugawa, and T. Koyama Shinko Electric Industries Co., Ltd. 36 Kita Owaribe Nagano-shi, , Japan , 87

88 Shinko s 4+(2-2-3) Thin-Film on Build-up Layer Test Vehicle: 2μm Cu trace and 40μm pitch pad Thin-Film layers Build-up layers Core 2μm line width/spacing 40μm pad pitch 10μm stack via 100μm PTH 50μm buildup via 10μm stack via 2μm line width 1.9μm spacing 2μm thick Cu 10μm stack via 11.8μm thick pad 25μm (dia.) Cu pad 88

89 Future Package Substrates In general, a package substrate with 8-build-up-layer (4-2-4) and 20μm line-width and spacing is more than adequate to support most of the chips. Thus, interposers are not needed. Also, in the past 3 years, Substrate Houses have been developing package substrates with high build-up layers (5-2-5) and fine (12-15μm) line-width and spacing. Recently, Shinko s thin-film layers on build-up layers can make 2μm line width and spacing and 40μm pad pitch. All these activities are keeping interposers away from volume production, except for very niche (such as extremely high-performance, high-density, and fine-pitch) applications. 89

90 Embedded Interposer/Bridge 90

91 Multi-chips on a TSV interposer Semi-Embedded on a Substrate/PCB with Stress Relief Gap TSV Underfill between the chips and TSV interposer and the chips and organic substrate/pcb is necessary The advantages of this design are: (1) Low profile and low cost (2) Free to use any Moore s law chips without TSVs (3) RDLs allow chip - to - chip short interconnect (4) TSVs can be used for powers, grounds, and some signals (5) Very reliable (because the stress relief gap reduces the thermal expansion mismatch between the embedded TSV interposer and the organic substrate/pcb Lau, J. H., S. T. Wu, and H. C. Chien, Nonlinear Analyses of Semi-Embedded Through-Silicon Via (TSV) Interposer with Stress Relief Gap Under Thermal Operating and Environmental Conditions, IEEE EuroSime Proceedings, Chapter 11: Thermo-Mechanical Issues in Microelectronics, Lisbon, Portugal, April 2012, pp. 1/6 6/6.

92 ITRI/Unimicron s Packaging Substrate Having Embedded Interposer and Fabrication Method Thereof (US2013/ A1) (Publication Date: Feb. 7, 2013, Filed Date: Aug. 3, 2012)

93 Intel s Bridge Interconnect with Air Gap in Package Assembly (US 2014/ A1) (Publication Date: Mar. 13, 2014, Filed Date: Sept. 11, 2012)

94 Intel s Bridge Interconnect with Air Gap in Package Assembly (US 2014/ A1) Intel Newsroom on Aug 27, 2014 (Publication Date: Mar. 13, 2014, Filed Date: Sept. 11, 2012) RDL Via Bridge Chip Chip Chip Solder Bumps Substrate Solder Balls Solder Bumps Bridge RDL Air Gap Embedded Multi-die Interconnect Bridge (EMIB)

95 3D MEMS and IC Integration 95

96 Avago s FBAR MEMS Filter with TSV TSV TSV Rx die Tx die Au CAP TSV CAP TSV CAP 96

97 Photo images of the FBAR hermetic package. (a) Cap wafer with IC device, TSVs, internal connections, and cavity for the FBAR. (b) FBAR wafer with FBAR, pads, internal connections, and cavity for IC device TSV ICP ICP TSV TSV TSV TSV TSV Pad ICP Pad Pad Pad Pad Pad ICP (a) Cap Wafer (b) FBAR Wafer 97

98 TSV TSV Top: IC cap wafer to FBAR wafer Au-Au bonding. (b) Cross section SEM image of the bonded FBAR MEMS package with IC cap Au Pads IC Cap Wafer FBAR Circuit FBAR Wafer Au Pads Au IC Cap Wafer 300µm FBAR FBAR Wafer TSV Circuit 98

99 3D CIS and IC Integration 99

100 Front-illuminated (FI) CIS. Some of the lights are blocked (reflected) by the transistors and metal wirings Light Micro Lens Color Filter Transistors and Metal Wiring Line of receiving surface PD Si-Substrate 100

101 (TOP) Schematic of Back-illuminated (BI) CIS. (Bottom) Cross section SEM image of a BI-CIS Light Line of receiving surface Micro Lens Color Filter Backside PD Si-substrate Transistors and Metal Wiring Line of receiving surface Micro Lens Color Filter Backside Si-substrate PD 101

102 SONY s BI-CIS: conventional vs. new 3D stacking Circuits Pixels Pixels Circuits Supporting Substrate (Si) Conventional BI-CIS Logic Process Substrate (Si) New Stacked BI-CIS 102

103 3D CIS pixel chip and logic IC integration 103

104 CIS (insulator) wafer to logic (insulator) wafer bonding BI-CIS Process Technology On chip color filter and micro lens CIS (Si) W2W Bonding Surface CIS (Insulator) Logic (Insulator) Logic Process Technology Logic (Si) 50µm 104

105 TSVs connecting the CIS pixel chip and the logic circuit chip CIS (Si) On chip color filter and micro lens Logic (Si) TSV 105

106 SUMMARY AND RECOMMENDATION (3D IC Integration) TSVs straight through the same memory chips to: enlarge the memory capacity lower the power consumption increase the bandwidth lower the latency (enhance electrical performance) reduce the form factor will be the major applications of 3D IC Integration! Memory chip stacking with TSV has been in production for servers by Samsung. The Hybrid Memory Cube (HMC) will be used by Intel, Altera, Fujitsu, etc. this year for high performance products! The High Bandwidth Memory (HBM) will be used by Hynix, AMD, Nvidia, etc. for graphic applications. 106

107 SUMMARY AND RECOMMENDATION (2.5D IC Integration - Interposers) In general, interposers are for extremely high-i/o, high-performance, high-density, and fine-pitch semiconductor IC applications. In general, the build-up package substrates are more than adequate to support the semiconductor IC chips in high-end smartphones and an interposer is not necessary. Thin-film RDLs on top of the build-up package substrate invented by Shinko is the right way to go. The industry should strive to commercialize it. Try not to use the interposer unless the build-up package substrates are not adequate to support the very high I/O, highperformance, high-density, and fine-pitch chips. Now, with the thinfilm RDLs on top of the build-up package substrate, the highvolume production of interposer will be pushed out even further. 107

108 SUMMARY AND RECOMMENDATION (3D IC Packaging) 3D IC Packaging such as Stacked dies with wire bonding PoP have been and will be used for mobile products such as smartphones and tablets. 3D Chip-to-Chip and Face-to-Face will soon be used for mid-range performance applications. 108

109 SUMMARY AND RECOMMENDATION (ewlp) ewlp is expected to grow substantially in the next few years. Most of the OSATs (the top 6) are developing their ewlp technologies. ewlp package is just right for smaller size of chip. ewlp package is just right for smartphones, tablets, and wearables because it is low profile, light weight, and low cost. ewlp package cannot house very large chips (e.g., 15mm x 15mm) like the PBGA package. ewlp package size cannot be too big (e.g., 45mm x 45mm like the PBGA package. 109

110 ACKNOWLEDGEMENTS The author would like to thank his colleagues at IME, HKUST, ITRI, ASM and throughout the packaging community for their useful help, strong support, and stimulating discussions. 110

111 Thank You Very Much for Your Attention! 111