Packaging of Selected Advanced Logic in 2x and 1x nodes. 1 I TechInsights

Transcription

1 Packaging of Selected Advanced Logic in 2x and 1x nodes 1 I TechInsights

2 Logic: LOGIC: Packaging of Selected Advanced Devices in 2x and 1x nodes Xilinx-Kintex 7XC 7 XC7K325T TSMC 28 nm HPL HKMG planar MediatekMT6592 TSMC 28 nm HP HKMG planar Qualcomm MDM9215 Samsung 28 nm Poly planar Qualcomm MDM9235 TSMC 20 nm HKMG planar Samsung Exynos 5430 Samsung 20 nm HKMG planar Intel i Ivy Bridge Intel 22 nm HKMG finfet Intel Valley View Atom Z3740 Intel 22 nm HKMG finfet Intel Broadwell 5Y70 Intel 14 nm HKMG finfet General comments on logic packaging 2 I TechInsights

3 Logic: Packages, planar 28 nm Top: TSMC, 28 nm Xilinx Kintex-7 Top: TSMC, 28 nm Mediatek MT6592 Top: Samsung, 28 nm Qualcomm MDM9215 Bottom: Xilinx Kintex-7 3 I TechInsights Bottom: Mediatek MT6592 Bottom: Qualcomm MDM9215

4 Logic: X-ray Packages, planar 28 nm X-Ray: TSMC, 28 nm Xilinx Kintex-7 Single die is flip-chip bumped to a printed wiring board The package contains copper heat spreader X-Ray: TSMC, 28 nm Mediatek MT6592 Single die is flip-chip bumped to a printed wiring board X-Ray: Samsung, 28 nm Qualcomm MDM9215 Two dies are in the package. The memory die is on top of the baseband processor. The processor is flip-chip bumped to a printed wiring board 4 I TechInsights

5 Logic: Die planar 28 nm Die Photo: TSMC, 28 nm Xilinx Kintex-7 Die Area: 16.8 mm x 9.8 mm = mm² Die Photo: TSMC, 28 nm Mediatek MT6592 Die Area: 6.2 mm x 6.0 mm = mm² Die Photo: Samsung, 28 nm Qualcomm MDM I TechInsights Die Area: 7.2 mm x 5.8 mm = mm²

6 Logic: Bond Pad planar 28 nm, Bond pads are in Al Regular octagon shaped bump pads distributed across the die Bump pads fabricated from Al based metal Bond Pad: TSMC, 28 nm Xilinx Kintex-7 Bond Pad: TSMC, 28 nm Mediatek MT6592 Bond Pad: Samsung, 28 nm Qualcomm MDM I TechInsights

7 Logic: Bond Pad planar 28 nm Solder ball connecting bond pad: TSMC 28 nm, Xilinx Kintex-7 Cu-pillar connecting bond Pad: TSMC 28 nm, Mediatek MT6592 Solder ball connecting bond pad: Samsung 28 nm, Qualcomm MDM9215 UBM over polymide: Xilinx Kintex-7 7 I TechInsights Cu-Pillar on top of polymide: Mediatek MT6592 UBM over polymide: Qualcomm MDM9215 Polymide on passivation is used by all these manufacturers and it helps in mitigating stress TSMC uses Cu-pillar on Al at 28 nm node for Mediatek TSMC uses solder bond at 28 nm for Xilinx, ATI-Radeon and Nvidia

8 Logic: Packages, planar 20 nm Top: TSMC, 20 nm Qualcomm MDM9235 Top: Samsung, 20 nm Samsung Exynos 5430 (After removing the memory die that was attached on top of it) Bottom: TSMC, 20 nm Qualcomm MDM9235 Bottom: Samsung, 20 nm Samsung Exynos I TechInsights

9 Logic: X-ray Packages, planar 20nm X-Ray: TSMC, 20 nm Qualcomm MDM9235 Two dies are in the package. The memory die is on top of the baseband processor. The processor is flip-chip and connected with copper pillars to the printed wiring board X-Ray: Samsung, 20 nm Samsung Exynos 5430 Two dies are in the package. The memory die is on top of the baseband processor. The processor is flip-chip bumped to a printed wiring board 9 I TechInsights

10 Logic: Die photo, planar 20 nm Die Photo: TSMC, 20nm Qualcomm MDM9235 Die Photo: Samsung, 20 nm Samsung Exynos 5430 Die Area: 5.5 mm x 4.3 mm = mm² Die Area: 10.3 mm x 10.7 mm = mm² 10 I TechInsights

11 Logic: Bond Pad, planar 20 nm Bond Pad: TSMC, 20 nm Qualcomm MDM9235 Bond Pad: Samsung, 20 nm Samsung Exynos 5430 Bond pad is made on Al The bond pads are patterned into the aluminum redistribution layer (RDL). 11 I TechInsights

12 Logic: Bond Pad, planar 20 nm TSMC uses Cu-Pillar on Al bond pad Cu-pillar connecting bond Pad: TSMC, 20 nm, Qualcomm MDM9235 Solder connecting bond Pad: Samsung, 20 nm, Samsung Exynos 5430 Samsung uses UBM and solder on Al bond pad Cu-Pillar on top of polymide : TSMC, 20 nm, Qualcomm MDM9235 UBM over polymide: Samsung 20 nm, Samsung Exynos I TechInsights

13 Logic: Packages, finfet 2x & 1x Top: Intel 22 nm i Ivy Bridge Top: Intel 22 nm Valley View Atom Z3740 Top: Intel 14 nm Broadwell 5Y70 Bottom: Intel, 22 nm i Ivy Bridge 13 I TechInsights Bottom: Intel, 22 nm Valley View Atom Z3740 Bottom: Intel, 14 nm Broadwell 5Y70

14 Logic: X-ray Packages, finfet 2x & 1x X-Ray: Intel 22 nm i Ivy Bridge There is a single die in the package. Flip chip land grid array FC-LGA package with copper pillar bumping technology is used. The package contains integrated heat spreader 14 I TechInsights X-Ray: Intel 22 nm Valley View Atom Z3740 The package contains a single die Flip chip ball grid array FCBGA package with copper pillar bumping technology is used. X-Ray: Intel 14 nm Broadwell 5Y70 The package contains two dies placed side by side on a PCB Flip chip ball grid array FCBGA package with copper pillar bumping technology is used.

15 Logic: Die photo, finfet 2x & 1x nm Die Photo: Intel, 22 nm i Ivy Bridge Die Photo: Intel, 22 nm Atom Z3740 Die Photo: Intel, 14 nm Broadwell 5Y70 Die Area: 19.6 mm x 8.0 mm = mm² Die Area: 10.4 mm x 9.7 mm = mm² Die Area: 13.3 mm x 5.9 mm = 78.5 mm² 15 I TechInsights

16 Logic: Die photo, finfet 2x & 1x nm Bond Pad: Intel, 22 nm i Ivy Bridge Bond Pad: Intel, 22 nm Atom Z3740 Bond Pad: Intel, 14 nm Broadwell 5Y70 16 I TechInsights Bond pad is made on Cu For Intel 22 nm bump pads (copper pillars) are connected to metal 9 lines through pad openings. Bump pads are elliptical in shape These two pictures do not have Cu-pillars, they are removed Bond pad is made on Cu The Broadwell chip has bump pads are cylindrical in shape and make direct contact to metal 13 through openings In this picture Cu-pillars are present

17 Logic: Bond Pad, finfet 2x & 1x nm Metal 9 (Cu) with passivation: Intel 22 nm, i Ivy Bridge Cu-pillar connects to metal 9 (Cu): Intel 22 nm, Atom Z3740 Cu-pillar connects to metal 13(Cu): Intel 14 nm, Broadwell 5Y70 Cu pillar on top of polymide: Intel, 22 nm, i Ivy Bridge Cu pillar through passivation: Intel, 22 nm, Atom Z3740 Cu pillar through passivation: Intel 14 nm, Broadwell 5Y70 17 I TechInsights Since 32 nm node, Intel is using Cu-pillars on Cu bond pads The copper and solder in the pillar are electroplated Cu pillar is over the polymide layer, which is on top of passivation layer

18 Logic: Table All devices below 28 nm technology node have metal 0 Metal 0 is not included in the count of metal levels TSMC and Intel use Cu-pillars 18 I TechInsights

19 General Remarks: Logic Packaging In all cases the logic die is always flip-chip bumped to the underlying substrate TSMC at 28 & 20 nm uses Cu-pillars TSMC uses Cu-pillar on Al bond pads Intel is using Cu-pillar bumping technology since 32 nm node Sn based solder is capping the copper pillars. The solder on Cu-pillar is electroplated. The process of Cu-pillars is the following Pattern the bond pads, Deposit the passivation layers Pattern the openings to expose the top surface of the aluminum. Deposit a polyimide layer Pattern polymide to have an opening. Deposit a barrier layer of followed by a seed layer (Cu) Apply photoresist and pattern to form a mold for the pillar Electro- deposit the pillar material using the seed layer as nucleation site Cap the cu-pillar with Ni to prevent oxidation and for adhesion with solder Deposit solder deposition. Remove the photoresist and pattern the barrier layers using the pillar as a mask 19 I TechInsights

20 General Remarks: Logic Packaging All the manufacturers use Al at the last level of metallization, except for Intel Intel uses Cu in the last metal level Manufacturers using Al in their last metal level are using a polymide level over the passivation layer and then an under bump metallization (UBM) The UBM is fabricated with a thin Ti-based film, a thin Cu layer and a thick Ni layer over the openings in polymide and passivation layers followed by Sn based solder Most packages are FCBGA and in some case when there are multiple dies in the package a PoP (Package on Package) configuration is used. Qualcomm MDM9215 (28 nm Samsung), Qualcomm MDM9235 (20 nm TSMC) and Samsung Exynos 5430 (20 nm Samsung) use a multi-chip structure in Package on Package configuration (PoP). The memory die is placed on top of the processor 20 I TechInsights

21 General Remarks: Logic Packaging Intel Broadwell 5Y70 uses a multichip package, where two devices are placed sided by side on a packaging substrate Samsung Exynos (20 nm), and all the three Intel devices ( 22 nm & 14 nm) have more than 1000 pin counts All devices below 28 nm node use M0; (when counting number of metal levels M0 is not included) For all devices the bond pad pitch is around 0.1 mm None of the logic devices are using ultra-thin wafers (less than 50 µm) Samsung Exynos 20 nm and Qualcomm MDM9235 (TSMC 20 nm) have the minimum die thickness around 90 µm The ratio of package area to the die area ratio is varying from 2 to 9 Larger ratio suggests that the package contains a heat spreader or has multiple dies 21 I TechInsights

22 Additional Information Detailed structural analysis exists for all the devices discussed in this presentation. The detailed structural analysis includes gate structures, SRAM cells and metallization-ild layers. Comparison reports also exist that highlight the commonalities and the differences between these devices 22 I TechInsights