Building IBIS-AMI Models for DDR5 Applications. Todd Westerhoff, SiSoft

Transcription

1 Building IBIS-AMI Models for DDR5 Applications Todd Westerhoff, SiSoft

2 SPEAKERS Image Todd Westerhoff VP, Semiconductor Relations, SiSoft Todd has over 37 years of experience in electronic system modeling and simulation, including 20 years in signal integrity. He is responsible for SiSoft's activities working with semiconductor vendors to develop high-quality simulation models and has been heavily involved with the IBIS- AMI modeling specification since its inception. He has held senior technical and management positions for Cisco and Cadence and worked as an independent signal integrity consultant. 2

3 IBIS-AMI Models Goals Interoperable: different vendor models work together Portable: one model runs in multiple simulators Flexible: supports Statistical and Time-Domain simulation High Performance: simulates a million bits per CPU minute Accurate: high correlation to simulations / measurement Secure: represents IP behavior without exposing internal details Assumptions Analog I/O operates in linear region High impedance node between analog I/O & equalization circuitry Equalization behavior modeled by code linked into simulator Equalization models use AMI API AMI 3

4 IBIS-AMI Modeling Challenges AMI Algorithmic models: o Compiled objects linked into EDA simulator at runtime o Interface defined in C language Skills required: o IBIS-AMI specification o C/C++ software programming o Communications analysis o Analog circuit design / modeling o Digital signal processing o Control loop theory You shouldn t have to be a wizard to create an IBIS-AMI model! 4

5 AMI Model Development Goals Interactive development environment o High level modeling language not C/C++ o Library of configurable building blocks / examples o User extensible; can add new model controls and algorithms o Import test case data from real world (customer) topologies o No need to run compilers from the command line Faithfully model data path and control algorithms Portable, compliant IBIS-AMI models 5

6 Wouldn t It Be Great If When AMI models weren t working properly in your favorite channel simulator 6

7 Wouldn t It Be Great If You could push into an AMI model to see how it was constructed 7

8 Wouldn t It Be Great If and edit MATLAB code for the different model blocks 8

9 Wouldn t It Be Great If then rerun your simulation using updated models? 9

10 SiSoft / MathWorks Integration QCD/QSI Simulink/MATLAB Integrated AMI channel simulation and AMI model development 10

11 AMI Model Development Flow Simulink / MATLAB Generate test case data Interactive design & debug IBIS-AMI model creation Tight analysis loop speeds three critical phases of AMI development o Test case definition & generation Identify cases of interest Done? Regression testing o Interactive algorithmic development o Regression testing / issue identification Quantum-SI IBIS-AMI validation & distribution 11

12 Quantum-SI: Test Case Definition & Generation Circuit topology Data rate & simulation setup Different test setups Driver strength / terminations TX/RX EQ settings 12

13 AMI Modeling Development Environment Simulink o General purpose, time-domain modeling / simulation environment o Libraries of sources / sinks / building blocks o Integrated MATLAB support with interactive debugging o C code generation with embedded support for IBIS-AMI API 13

14 AMI Case 2: TX: Init-only RX: Getwave-only Configure Simulink to act like an AMI simulator h AC (t) Bit stream b(t) o Fixed time step analysis TX AMI_Init TX AMI_Init o Static ( Init ) TX equalization h AC (t) h TE (t) h AC (t) h TE (t) o o Dynamic ( GetWave ) RX equalization Clock recovery performed by RX model Bit stream b(t) g RE [ b(t) h AC (t) h TE (t) ] h AC (t) g RE [ b(t) h AC (t) h TE (t) ] AMI models are generated from TX/RX subsystems in the Simulink model RX AMI_Getwave Post-processing Time-Domain Flow Static TX EQ, Dynamic RX EQ RX AMI_Getwave Post-processing Time-Domain Flow Static TX EQ, Dynamic RX EQ AMI Specification Simulink Setup 14

15 Simulink AMI Model Development Setup Channel Impulse Response Stimulus TX ( Init ) RX ( GetWave ) Replicates the IBIS-AMI Tx_Init / Rx_Getwave analysis flow 15

16 Importing Test Case Data QSI Simulink Channel model Data rate Stimulus TX/RX EQ settings Simulation setup 16

17 AMI Algorithm Development Start / stop / step simulation Waveform & scope displays MATLAB code debugger Examine / modify model variables Stop on breakpoint or user-defined condition Modify algorithms & rerun 17

18 AMI Code Generation / Compilation C code automatically generated & compiled Create different models for internal / external use Models conform to IBIS-AMI API 18

19 Comparing Simulation Results Simulink Waveforms Eyes DFE Taps QCD/QSI 19

20 Automated AMI Regression Testing 1. Setup tests in QSI 2. Simulations run in parallel 3. Metrics & plots presented in SiViewer Setup & run 1,000 s of simulations using QSI s solution space QSI extracts performance metrics and compliance pass/fail criteria Scalable high performance simulation o Compiled models run 5-7x faster o Run simulations in parallel o Speedups >100x are possible 20

21 Unique DDR5 Modeling Needs IBIS-AMI was originally developed for lossy, differential serial channel applications DDR5 presents new AMI modeling challenges o Single-ended signaling o DRAM DFE training performed by controller o Clock forwarding vs. Rx clock recovery o Representing I/O nonlinearity, power and noise 21

22 Single-Ended AMI This is a tricky one! o Because AMI simulations use an impulse response for the channel, DC bias information technically gets lost during AMI model processing o One way to address this is to extract the DC bias from the analog channel analysis and add it back after EQ processing This approach allows us to directly leverage existing AMI algorithms, many of which have the expectation of differential signaling baked in to the code. 22

23 Modeling DRAM DFE Training DDR5 controllers set DRAM DFE taps by training at system startup Modeling training sequences with AMI models is difficult & time consuming Manually optimizing DRAM DFE settings through simulation is difficult & time consuming Approach: let DRAM DFE taps adapt, then lock settings when Ignore_Bits is reached 23

24 Modeling Clock Forwarding DDR5 transfers use DQS signals to sample the incoming data Traditional AMI models recover the sampling clock from the incoming data stream AMI provides no facility for a separate clock input to the algorithmic model Approach: model the CDR in the algorithmic model as usual, lock adaptation as Ignore_Bits is reached, use Rx jitter parameters to include sampling clock noise 24

25 AMI Model Development Flow 1. Define test cases: Topologies, data rates, transfers, terminations, TX/RX equalization & simulation settings. 2. Load a test case into AMI development environment. 3. Design & debug TX/RX modeling algorithms. 6. Run regression tests to validate compiled models & identify issues. 4. Create compiled AMI models. 5. Run compiled models with original test cases. 25

26 Portable, Compliant Models Eye Diagram Output Clock Output Control Inputs Performance Test Simulation Time Reference Time Relative Speed Statistical 1 sec 1 sec 1.000x TimeDomain_008spb 1.46 min/mbit 1.30 min/mbit 0.889x TimeDomain_016spb 1.87 min/mbit 1.46 min/mbit 0.783x TimeDomain_032spb 3.33 min/mbit 2.60 min/mbit 0.781x TimeDomain_064spb 7.97 min/mbit 6.02 min/mbit 0.755x TimeDomain_128spb min/mbit min/mbit 0.814x Simulation Speed Compliance - Samples/Bit Compliance - Block Size Validation tests show generated AMI models work as well as models created by hand 26

27 Thank You! --- QUESTIONS? 27