Matsushita MN2DS0015 System on a Chip for DVD Players 65 nm CMOS Process Structural Analysis

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1 June 12, 2006 Matsushita MN2DS0015 System on a Chip for DVD Players 65 nm CMOS Process Structural Analysis For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor technology, please call Sales at Chipworks Richmond Road, Suite 500, Ottawa, ON K2H 5B7, Canada Tel: Fax:

2 Structural Analysis Report Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Company Profile 1.4 Introduction 1.5 Device Summary 1.6 Process Summary 2 Device Overview 2.1 Package and Die 2.2 Die Features 3 Process Analysis 3.1 General Device Structure 3.2 Bond Pads 3.3 Dielectrics 3.4 Metallization 3.5 Vias and Contacts 3.6 Transistors and Poly 3.7 Isolation 3.8 Wells and Substrate 4 Memory Cell Analysis 4.1 Memory Overview 4.2 6T-SRAM Cell 4.3 6T-SRAM Plan-View Analysis 4.4 6T-SRAM Cross-Sectional Analysis (Parallel to Bit Line) 4.5 8T-SRAM Cell 4.6 8T-SRAM Plan-View Analysis 4.7 ROM Plan-View Analysis Rev. 1.0 April 5, 2006 SAR

3 Structural Analysis Report 5 Materials Analysis 5.1 TEM-EDS Analysis of the Dielectrics 5.2 TEM-EDS and EELS Analysis of the Metal Liners and Silicide 6 Critical Dimensions 6.1 Die 6.2 Horizontal Dimensions 6.3 Vertical Dimensions 7 References Appendix A: Change to Reported Minimum Via Pitch A.1 Overview A.2 Cross-Sectional Analysis of Minimum Pitch Via 1 Pairs A.3 Plan-View Analysis of Via 3s Report Evaluation Rev. 1.0 May 4, 2006 SAR

4 Overview Overview 1.1 List of Figures 2 Device Overview Magnavox MSR90D6 DVD Recorder Front-View Magnavox MSR90D6 DVD Recorder Back-View MN2DS0015 on Main PCB Package Top Package Bottom Package X-Ray MN2DS0015 Die Annotated MN2DS0015 Die Die Markings Die Corner a Die Corner b Die Corner c Die Corner d Bond Pads Bond Pads Detail Logic Cells 3 Process Analysis General Structure of the MN2DS Die Edge Die Seal Structure Bond Pad and Ball Bond Bond Pad Edge Passivation and ILD Passivation and ILD 7 TEM ILD ILD 6-3 Detail TEM ILD 6-1 Detail TEM ILD ILD 5-1 and ILD 5-2 Detail TEM ILD 4 and ILD ILD 3, ILD 2 and ILD ILD 4 TEM ILD 3 TEM ILD 2 TEM ILD 1 TEM PMD PMD TEM PMD and STI Metal Metal 8 Spacing Minimum Pitch Metal 7 Rev. 2.0 May 1, 2006 SAR

5 Overview Metal 7 Liner Bottom TEM Minimum Pitch Metal Metal 6 TEM Minimum Pitch Metal Minimum Pitch Metal 5 TEM Metal 5 Detail TEM Minimum Pitch Metal Metal 4 TEM Minimum Pitch Metal Metal 3 TEM Minimum Pitch Metal TEM Metal 4 TaN Liner Minimum Pitch Metal Minimum Pitch Metal 1 TEM Metal 1 TaN Liner TEM Minimum Pitch Via 6s Via 6 TEM Minimum Pitch Via 5s Stacked Vias and Contacts Via 4s Via 3s Via 2s Via 1s Via 2 TEM Via 1 TEM Minimum Pitch Contacts to Diffusion Contact Top TEM Butted Contacts Butted Contacts TEM Minimum Pitch Contacts to Poly Contact to Poly TEM MOS Transistors Glass-Etch NMOS Transistors Si-Etch PMOS Transistors Si-Etch Minimum Poly Glass-Etch Dummy Poly Plan-View MOS Transistor TEM MOS Transistor TEM MOS Transistor Gate TEM MOS Transistor Gate Detail TEM MOS Transistor SWS Detail TEM MOS Transistor Contact to Gate Detail TEM Lattice Image Logic Gate Oxide TEM Minimum Pitch Polycide TEM MOS Gate Width TEM Rev. 2.0 May 1, 2006 SAR

6 Overview Large I/OTransistors Glass-Etch Large I/O Transistors TEM Thick Gate Oxide TEM Minimum Width STI Poly Over STI Detail TEM Poly Over STI Poly Over STI Detail TEM Wells SCM P-Well SRP P-Well SRP 4 Memory Cell Analysis MN2DS0015 Quarter 2 at Metal 4 Showing Memory Blocks T-SRAM Cell T-SRAM Metal 2 V DD Power Buses and Bit Lines T-SRAM Metal 1 Local Interconnects T-SRAM Gates T-SRAM at Diffusion PMOS Transistors PMOS Pull-Up Transistor TEM T-SRAM Cell T-SRAM Metal 1 Local Interconnects T-SRAM Gates T-SRAM SRAM at Diffusion ROM at Poly ROM at Diffusion 5 Materials Analysis Dielectric and Metal Stack TEM-EDS Passivation TEM-EDS ILD TEM-EDS ILD TEM-EDS ILD TEM-EDS ILD TEM-EDS ILD TEM-EDS ILD TEM-EDS ILD TEM-EDS PMD TEM-EDS of TaN Metal Liner TEM-EELS Line Scan of TaN Metal 1 Liner TEM-EDS Gate Nickel Polycide TEM-EDS of Source/Drain Silicide Rev. 2.0 May 1, 2006 SAR

7 Overview 1-4 A A.2.1 A.3.1 A.3.2 A.3.3 A.3.4 A.3.5 A.3.6 A.3.7 A.3.8 A.3.9 Overview Minimum 0.20 µm Pitch Via 1 Pair Via 3s with 0.25 µm Pitch Plan-View Via 3s Plan-View Via 3s Plan-View 1.2 List of Tables 1 Overview Device Summary Process Summary 2 Device Overview Die Dimensions 3 Process Analysis Dielectric Thicknesses Metallization Vertical Dimensions Metallization Horizontal Dimensions Via and Contact Dimensions Transistor and Poly Horizontal Dimensions Transistor and Poly Vertical Dimensions Isolation Vertical Dimensions Wells Vertical Dimensions 4 Memory Cell Analysis SRAM Cell Sizes T-SRAM Transistor Sizes T-SRAM Transistor Sizes 5 Materials Analysis Dielectric Layer Composition 6 Critical Dimensions Die Dimensions Minimum Pitch Metals Via and Contact Dimensions Transistors, Poly and Isolation SRAM Cell Sizes Vert ical Dimensions Rev. 1.0 May 4, 2006 SAR

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