Class 04 MUX / DMUX and Full Adder

Transcription

1 lss 4 MUX / DMUX nd Full dder June 3, 23 2 Multiplexer MUX S S Y D D D 2 D 3 S S Y 3 D 3 D 3 D 23 D 33 Y 2 D 2 D 2 D 22 D 32 Y D D D 2 D 3 Y D D D 2 D 3

2 June 3, 23 3 Multiplexer MUX ENTITY mux4sel IS s: IN IT_VETOR downto ; d: IN IT_VETOR 3 downto ; y: OUT IT; END mux4sel; RHITETURE OF mux4sel IS EGIN - Selected Signl ssignment MUX4: WITH s SELET y < d WHEN "", d WHEN "", d2 WHEN "", d3 WHEN ""; END ; ENTITY mux4cse IS d, d, d2, d3: IN IT; -- dt inputs s: IN IT_VETOR downto ; -- select inputs y: OUT IT; END mux4cse; RHITETURE mux4to OF mux4cse IS EGIN -- Monitor select inputs nd execute if they chnge PROESSs EGIN SE s IS WHEN "" > y < d; WHEN "" > y < d; WHEN "" > y < d2; WHEN "" > y < d3; WHEN others > y < ''; END SE; END PROESS; END mux4to; June 3, 23 4 Demultiplexer DMUX S S 2

3 June 3, 23 5 Demultiplexer DMUX ont. ENTITY dmux8 IS s: IN STD_LOGI_VETOR2 downto ; d: IN STD_LOGI; y: OUT STD_LOGI_VETOR to 7; END dmux8; RHITETURE OF dmux8 IS SIGNL inputs : STD_LOGI_VETOR3 downto ; EGIN inputs < d & s; s: selector WITH inputs SELET y < "" WHEN "", "" WHEN "", "" WHEN "", "" WHEN "", "" WHEN "", "" WHEN "", "" WHEN "", "" WHEN "", "" WHEN others; END ; & d & WHEN, d: signl June 3, 23 6 Hlf dder out Hlf dder out 3

4 4 June 3, 23 7 Full dder out IN out June 3, 23 8 Prllel inry dder Ripple rry inry dder

5 June 3, 23 9 Full dder LIRRY ieee; USE ieee.std_logic_64.ll; ENTITY full_dd IS,, : IN STD_LOGI;, : OUT STD_LOGI; END full_dd; RHITETURE dder OF full_dd IS EGIN < xor nd or nd ; < xor xor ; out LIRRY ieee; USE ieee.std_logic_64.ll; June 3, 23 2-it Full dder ENTITY dd2pr IS c: IN STD_LOGI;, : IN STD_LOGI_VETOR2 downto ; c2: OUT STD_LOGI; : OUT STD_LOGI_VETOR2 downto ; END dd2pr; LIRRY ieee; USE ieee.std_logic_64.ll; ENTITY full_dd IS,, : IN STD_LOGI;, : OUT STD_LOGI; END full_dd; RHITETURE dder OF full_dd IS EGIN < xor nd or nd ; < xor xor ; Lel is needed Ech component should hve different lel nme RHITETURE dder OF dd2pr IS -- omponent declrtion OMPONENT full_dd,, : IN STD_LOGI;, : OUT STD_LOGI; END OMPONENT; -- Define signl for internl crry its SIGNL c : STD_LOGI_VETOR downto ; EGIN -- Two omponent Instntition Sttements dder: full_dd PORT MP >, >, > c, > c, > ; dder2: full_dd PORT MP > 2, > 2, > c, > c2, > 2; onnect of dder to of dder2 5

6 LIRRY ieee; USE ieee.std_logic_64.ll; June 3, 23 2-it Full dder ont. LIRRY ieee; USE ieee.std_logic_64.ll; ENTITY dd4gen IS c: IN STD_LOGI;, : IN STD_LOGI_VETOR2 downto ; c2: OUT STD_LOGI; : OUT STD_LOGI_VETOR2 downto ; END dd4gen; RHITETURE dder OF dd4gen IS -- omponent declrtion OMPONENT full_dd,, : IN STD_LOGI;, : OUT STD_LOGI; END OMPONENT; -- Define signl for internl crry its SIGNL c : STD_LOGI_VETOR 2 downto ; EGIN c < c; dder: full_dd PORT MP,, c, c, ; Lel is needed dders: FOR i IN to 2 GENERTE dder: full_dd PORT MP i, i, ci-, ci, i; END GENERTE; c2 < c2; dder2: full_dd PORT MP 2, 2, c, c2, 2; ENTITY dd2pr IS c: IN STD_LOGI;, : IN STD_LOGI_VETOR2 downto ; c2: OUT STD_LOGI; : OUT STD_LOGI_VETOR2 downto ; END dd2pr; RHITETURE dder OF dd2pr IS -- omponent declrtion OMPONENT full_dd,, : IN STD_LOGI;, : OUT STD_LOGI; END OMPONENT; -- Define signl for internl crry its SIGNL c : STD_LOGI_VETOR downto ; EGIN -- Two omponent Instntition Sttements dder: full_dd PORT MP >, >, > c, > c, > ; dder2: full_dd PORT MP > 2, > 2, > c, > c2, > 2; June 3, 23 2 Full dder with Unspecified Width LIRRY ieee; Defult vlue USE ieee.std_logic_64.ll; required, ut cn ENTITY ddxgen IS e redefined. GENERI width : INTEGER : 8; c: IN STD_LOGI;, : IN STD_LOGI_VETORwidth downto ; c_mx: OUTSTD_LOGI; : OUT STD_LOGI_VETORwidth downto ; END ddxgen; RHITETURE dder OF ddxgen IS -- omponent declrtion OMPONENT full_dd,, : IN STD_LOGI;, : OUT STD_LOGI; END OMPONENT; -- Define signl for internl crry its SIGNL c : STD_LOGI_VETOR width downto ; EGIN c < c; dders: FOR i IN to width GENERTE dder: full_dd PORT MP i, i, ci-, ci, i; END GENERTE; c_mx < cwidth; LIRRY ieee; USE ieee.std_logic_64.ll; ENTITY dd6gen IS c: IN STD_LOGI;, :IN STD_LOGI_VETOR6 downto ; c6: OUT STD_LOGI; : OUT STD_LOGI_VETOR6 downto ; END dd6gen; RHITETURE dder of dd6gen IS OMPONENT ddxgen GENERI width : INTEGER; c: IN STD_LOGI;, : IN STD_LOGI_VETORwidth downto ; c_mx: OUT STD_LOGI; : OUT STD_LOGI_VETORwidth downto ; END OMPONENT; EGIN dd6 : ddxgen GENERI MPwidth > 6 PORT MPc,,, c6, ; Included components should e in the sme Qurtus project s well. width is specified in GENERI MP 6

7 June 3, 23 3 The Procedure to Import VHDL ode to lock Digrm/Schemtic File The procedure to import VHDL full-dder to.df file to construct four-it full dder:. rete qurtus project with entity nme dder 2. rete new full_dd.vhd file nd sve it s full_dd.sf file. File rete/updte rete Symol File 3. rete new dder.df file the file nme is its entity nme 4. Incude full_dd.sf file s component into dder.df f ull_dd 5. Pin ssignment to complete the design V V s LIRRY ieee; USE ieee.std_logic_64.ll; inst f ull_dd ENTITY full_dd IS,, : IN STD_LOGI;, : OUT STD_LOGI; END full_dd; RHITETURE dder OF full_dd IS EGIN < xor nd or nd ; < xor xor ; full_dd.vhd f ull_dd inst full_dd.sf V V V V V V inst f ull_dd inst2 f ull_dd inst3 dder.df s2 s3 s5 s4 June 3, 23 4 L 4 Prt : Design MUX/DMUX Use utton2-utton s the selectors to decide which slide switch mong SW7-SW is selected to show its sttus on its corresponding LED. The LEDs tht re not selected should e turned off. For exmple: - When utton2 is pushed, the sttus of SW4 is shown on LEDG4. - When utton2 nd utton re oth pushed, the sttus of SW5 is shown on LEDG5. Prt 2: Full dder Implement 4-it full dder: - SW7-4 is the first 4-it opernd, nd SW3- is the second 4-it opernd. - Plese show the result on LEDs, where LEDG4 is the crry of the MS it, nd LEDG3- re 3-, respectively. n LED is on when the corresponding it is. 7

8 June 3, 23 5 Pushutton nd Slide Switches Pin numer Pin numer 3 Pushutton switches: Not pressed Logic High Pressed Logic Low Slide switches Sliders: Up Logic High Down Logic June 3, 23 6 LEDs Pin numer LEDs Opuput high LED on Output low LED off 8

9 June 3, Segment Displys Pin numer ctive-low 9