Memory Technology. (ROM) (Nonvolatile) (Nonvolatile) SerialInIn (SIPO) Erasable Erasable. Erasable Erasable Programmable
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1 M2 Systems
2 M2 line Hierarchy Cache Blocking Cache Aware Programming S, D Virtual Virtual Machines Non-volatile, Persistent NVM
3
4 Technology Arrays Arrays Random RandomAccess Access Read/Write Read/Write () () Static Static (S) (S) Dynamic Dynamic (D) (D) Mask Mask (P) (P) Access Access Content ContentAddressable Addressable Read ReadOnly Only Shift Registers Shift Registers () () InIn (EP) (EP) InIn (EEP) (EEP) InIn Flash Flash Last LastInIn
5 Technology Arrays Arrays Random RandomAccess Access Read/Write Read/Write () () Static Static (S) (S) Dynamic Dynamic (D) (D) Mask Mask (P) (P) Access Access Content ContentAddressable Addressable Read ReadOnly Only Shift Registers Shift Registers () () InIn (EP) (EP) InIn (EEP) (EEP) InIn Flash Flash Last LastInIn
6 Technology Arrays Arrays Random RandomAccess Access Read/Write Read/Write () () Static Static (S) (S) Dynamic Dynamic (D) (D) Mask Mask (P) (P) Access Access Content ContentAddressable Addressable Read ReadOnly Only Shift Registers Shift Registers () () InIn (EP) (EP) InIn (EEP) (EEP) InIn Flash Flash Last LastInIn
7 Technology Arrays Arrays Random RandomAccess Access Read/Write Read/Write () () Static Static (S) (S) Dynamic Dynamic (D) (D) Mask Mask (P) (P) Access Access Content ContentAddressable Addressable Read ReadOnly Only Shift Registers Shift Registers () () InIn (EP) (EP) InIn (EEP) (EEP) InIn Flash Flash Last LastInIn
8 Technology Arrays Arrays Random RandomAccess Access Read/Write Read/Write () () Static Static (S) (S) Dynamic Dynamic (D) (D) Mask Mask (P) (P) Access Access Content ContentAddressable Addressable Read ReadOnly Only Shift Registers Shift Registers () () InIn (EP) (EP) InIn (EEP) (EEP) InIn Flash Flash Last LastInIn
9 Technology Arrays Arrays Random RandomAccess Access Read/Write Read/Write () () Static Static (S) (S) Dynamic Dynamic (D) (D) Mask Mask (P) (P) Access Access Content ContentAddressable Addressable Read ReadOnly Only Shift Registers Shift Registers () () InIn (EP) (EP) InIn (EEP) (EEP) InIn Flash Flash Last LastInIn
10 Array Organized as 2n words of 2m bits each Usually n >> m (1M vs. 64) n = 20; m = 6 26 bits 2 words 20...
11 Array Organized as 2n words of 2m bits each Usually n >> m (1M vs. 64)
12 Array Organized as 2n words of 2m bits each Usually n >> m (1M vs. 64) Fold array to 2n-k rows x 2m+k columns 26 bits 212 bits 214 words 2 words 20...
13 Array Word Line cell Address Address Decoder Decoder 2n word lines n address bits m bit lines
14 Array wordlines wordlines bitline bitlineconditioning conditioning bitlines bitlines rowdecoder decoder row n-k n-k nn memory memorycells: cells: n-k 22n-krows rowsxx m+kcolumns 22m+k columns column column circuitry circuitry kk column column decoder decoder 22mm bits bits
15 6T Static Cell word (row select) 0 0 bit 1 1 bit
16 6T S Cell Operation Read: Precharge bit, bit_b Raise wordline Cell puts value into bit and its complement in bit_b Sense amplifiers sense difference between bit and bit_b
17 6T S Cell Operation Write: Drive data onto bit, bit_b Raise wordline Access transistors set the cell to new state
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+1 (479)
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