CHAPTER 8. Array Subsystems. VLSI Design. Chih-Cheng Hsieh

Transcription

1 CHAPTER 8 Array Subsystems

2 Outline 2 1. SRAM 2. DRAM 3. Read-Only Memory (ROM) 4. Serial Access Memory 5. Content-Addressable Memory 6. Programmable Logic Array

3 Memory Arrays 3 Memory Arrays Random Access Memory Serial Access Memory Content Addressable Memory (CAM) Read/Write Memory (RAM) (Volatile) Read Only Memory (ROM) (Nonvolatile) Shift Registers Queues Static RAM (SRAM) Dynamic RAM (DRAM) Serial In Parallel Out (SIPO) Parallel In Serial Out (PISO) First In First Out (FIFO) Last In First Out (LIFO) Mask ROM Programmable ROM (PROM) Erasable Programmable ROM (EPROM) Electrically Erasable Programmable ROM (EEPROM) Flash ROM

4 row decoder Array Architecture 2 n words of 2 m bits each If n >> m, fold by 2 k into fewer rows of more columns wordline s bitline conditioning bitlines 4 memory cells: 2 n-k rows x 2 m+k columns Good regularity easy to design Very high density if good cells are used n-k n k column decoder 2 m bits column circuitry

5 SRAM Cell Decoders Column Circuitry Multiple Ports SRAM Architecture 5

6 12T SRAM Cell Basic building block: SRAM Cell Holds one bit of information, like a latch Must be read and written 12-transistor (12T) SRAM cell Use a simple latch connected to bitline 46 x 75 l unit cell write bit 6 write_b read read_b

7 6T SRAM Cell Cell size accounts for most of array size Reduce cell size at expense of complexity 6T SRAM Cell Used in most commercial chips Data stored in cross-coupled inverters Read: Precharge bit, bit_b bit Raise wordline word Write: Drive data onto bit, bit_b Raise wordline bit_b 7

8 SRAM Read 8 Precharge both bitlines high Then turn on wordline One of the two bitlines will be pulled down by the cell Ex: A = 0, A_b = 1 bit discharges, bit_b stays high But A bumps up slightly Read stability A must not flip N1 >> N2 (N1 is stronger than N2) word bit bit_b N2 P1 P2 N4 A A_b N1 N3 A_b bit_b word bit 0.5 A time (ps)

9 SRAM Write Drive one bitline high, the other low Then turn on wordline Bitlines overpower cell with new value Ex: A = 0, A_b = 1, bit = 1, bit_b = 0 Force A_b low, then A rises high 1.5 Writability bit_b 1.0 Must overpower feedback 0.5 word inverter 0.0 N4 >> P2 word bit N2 A A_b P1 N1 A P2 N time (ps) A_b 9 bit_b N4

10 SRAM Column Example 10 Read Write Bitline Conditioning 1 Bitline Conditioning word_q1 More Cells word_q1 bit_v1f word_q1 More Cells out_v1r bit_v1f H SRAM Cell H bit_b_v1f write_q1 bit_v1f SRAM Cell bit_b_v1f out_b_v1r out_v1r data_s1

11 SRAM Sizing High bitlines must not overpower inverters during reads But low bitlines must write new value into cell 11 word bit med weak bit_b med A strong A_b

12 SRAM Layout Cell size is critical: 26 x 45 l (even smaller in industry) Tile cells sharing V DD, GND, bitline contacts 12 GND BIT BIT_B GND VDD WORD Cell boundary

13 Decoders n:2 n decoder consists of 2 n n-input AND gates One needed for each row of memory Build AND from NAND or NOR gates 13 Static CMOS Pseudo-nMOS A1 A0 A1 A0 A1 A word 1/2 A0 A word word0 word1 word2 word3 word0 word1 word2 word3

14 Decoder Layout Decoders must be pitch-matched to SRAM cell Requires very skinny gates 14 A3 A3 A2 A2 A1 A1 A0 A0 VDD word GND NAND gate buffer inverter

15 Large Decoders For n > 4, NAND gates become slow Break large gates into multiple smaller gates 15 A3 A2 A1 A0 word0 word1 word2 word3 word15

16 Predecoding Many of these gates are redundant Factor out common gates into predecoder Saves area Same path effort A3 A2 A1 A0 16 predecoders 1 of 4 hot predecoded lines word0 word1 word2 word3 word15

17 Column Circuitry Some circuitry is required for each column Bitline conditioning Sense amplifiers Column multiplexing 17

18 Bitline Conditioning Precharge bitlines high before reads 18 Equalize bitlines to minimize voltage difference when using sense amplifiers bit bit_b

19 Sense Amplifiers Bitlines have many cells attached Ex: 32-kbit SRAM has 256 rows x 128 cols 256 cells on each bitline t pd (C/I) DV Even with shared diffusion contacts, 128C of diffusion capacitance (big C) Discharged slowly through small transistors (small I) Sense amplifiers are triggered on small voltage swing (reduce DV) 19

20 Differential Pair Amp Differential pair requires no clock But always dissipates static power 20 sense_b bit P1 N1 N2 P2 sense bit_b N3

21 Clocked Sense Amp Clocked sense amp saves power Requires sense_clk after enough bitline swing Isolation transistors cut off large bitline capacitance 21 bit bit_b sense_clk isolation transistors regenerative feedback sense sense_b

22 Twisted Bitlines Sense amplifiers also amplify noise Coupling noise is severe in modern processes Try to couple equally onto bit and bit_b Done by twisting bitlines 22 b0 b0_b b1 b1_b b2 b2_b b3 b3_b

23 Column Multiplexing Recall that array may be folded for good aspect ratio Ex: 2 kword x 16 folded into 256 rows x 128 columns Must select 16 output bits from the 128 columns Requires 16 8:1 column multiplexers 23

24 Tree Decoder Mux Column mux can use pass transistors Use nmos only, precharge outputs One design is to use k series transistors for 2 k :1 mux No external decoder logic needed 24 A0 A0 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 A1 A1 A2 A2 Y to sense amps and write circuits Y

25 Single Pass-Gate Mux Or eliminate series transistors with separate decoder A1 A0 25 B0 B1 B2 B3 Y

26 Ex: 2-way Muxed SRAM 26 2 word_q1 More Cells More Cells A0 A0 write0_q1 2 write1_q1 data_v1

27 Multiple Ports We have considered single-ported SRAM One read or one write on each cycle Multiported SRAM are needed for register files Examples: Multicycle MIPS must read two sources or write a result on some cycles Pipelined MIPS must read two sources and write a third result each cycle Superscalar MIPS must read and write many sources and results each cycle 27

28 Dual-Ported SRAM Simple dual-ported SRAM Two independent single-ended reads Or one differential write worda wordb bit bit_b 28 Do two reads and one write by time multiplexing Read during ph1, write during ph2

29 Multi-Ported SRAM Adding more access transistors hurts read stability Multiported SRAM isolates reads from state node Single-ended design minimizes number of bitlines 29 worda wordb wordc wordd worde wordf wordg ba bb bc bd be bf bg write circuits read circuits

30 SRAM Scaling 30

31 Outline SRAM 2. DRAM 3. Read-Only Memory (ROM) 4. Serial Access Memory 5. Content-Addressable Memory 6. Programmable Logic Array

32 DRAM 32 DV V 2 DD C Ccell C cell bit

33 Subarray Architecture 33

34 Bitline Architectures 34 Bitline capacitance in a subarray is an order of magnitude higher than that in the cell Small V and need sense amplifier Open bitlines: use another subarray as reference Higher density Noise affect one array more than the other appears as differential noise. Folded bitlines: take the neighbor cell in the same subarry as reference Noise appears as common mode Larger layout area

35 Bitline Architectures 35 Open bitlines Folded bitlines

36 Outline SRAM 2. DRAM 3. Read-Only Memory (ROM) 4. Serial Access Memory 5. Content-Addressable Memory 6. Programmable Logic Array

37 Read-Only Memories Read-Only Memories are nonvolatile Retain their contents when power is removed Mask-programmed ROMs use one transistor per bit Presence or absence determines 1 or 0 37

38 ROM Example 38 4-word x 6-bit ROM Represented with dot diagram Dots indicate 1 s in ROM Word 0: Word 1: A1 A0 weak pseudo-nmos pullups Word 2: Word 3: :4 DEC ROM Array Y5 Y4 Y3 Y2 Y1 Y0 Looks like 6 4-input pseudo-nmos NORs

39 ROM Array Layout Unit cell is 12 x 8 l (about 1/10 size of SRAM) 39

40 Row Decoders ROM row decoders must pitch-match with ROM Only a single track per word! 40

41 Complete ROM Layout 41

42 PROMs and EPROMs Programmable ROMs Build array with transistors at every site Burn out fuses to disable unwanted transistors Electrically Programmable ROMs Use floating gate to turn off unwanted transistors EPROM, EEPROM, Flash 42 Source Gate Drain Polysilicon Floating Gate Thin Gate Oxide (SiO 2) n+ n+ p bulk Si

43 Building Logic with ROMs Use ROM as lookup table containing truth table n inputs, k outputs requires 2 n words x k bits Changing function is easy reprogram ROM Finite State Machine n inputs, k outputs, s bits of state Build with 2 n+s x (k+s) bit ROM and (k+s) bit reg inputs n DEC 2 n wordlines ROM Array inputs n ROM k s state outputs k s 43 k outputs

44 Let s build an Ant Sensors: Antennae (L,R) 1 when in contact Actuators: Legs Forward step F Ten degree turns TL, TR Example: RoboAnt L R 44 Goal: make our ant smart enough to get out of a maze Strategy: keep right antenna on wall (RoboAnt adapted from MIT OpenCourseWare by Ward and Terman)

45 Lost in space 45 Action: go forward until we hit something Initial state

46 Bonk!!! 46 Action: turn left (rotate counterclockwise) Until we don t touch anymore

47 A little to the right 47 Action: step forward and turn right a little Looking for wall

48 Then a little to the right 48 Action: step and turn left a little, until not touching

49 Whoops a corner! 49 Action: step and turn right until hitting next wall

50 Simplification Merge equivalent states where possible 50

51 State Transition Table 51 Lost RCCW Wall1 Wall2 S 1:0 L R S 1:0 TR TL F X X X X X

52 ROM Implementation 16-word x 5 bit ROM S 1 S 0 L R 52 L, R ROM S' 1:0 S 1:0 TL, TR, F 4:16 DEC S 1 ' S 0 ' TR'TL' F'

53 ROM Implementation 16-word x 5 bit ROM S 1 S 0 L R 53 L, R ROM S' 1:0 S 1:0 TL, TR, F 4:16 DEC S 1 ' S 0 ' TR'TL' F'

54 Outline SRAM 2. DRAM 3. Read-Only Memory (ROM) 4. Serial Access Memory 5. Content-Addressable Memory 6. Programmable Logic Array

55 Serial Access Memories Serial access memories do not use an address Shift Registers Tapped Delay Lines Serial In Parallel Out (SIPO) Parallel In Serial Out (PISO) Queues (FIFO, LIFO) 55

56 Shift Register Shift registers store and delay data Simple design: cascade of registers Watch your hold times! 56 clk Din 8 Dout

57 Denser Shift Registers Flip-flops aren t very area-efficient For large shift registers, keep data in SRAM instead Move read/write pointers to RAM rather than data Initialize read address to first entry, write to last Increment address on each cycle clk Din counter counter readaddr writeaddr dual-ported SRAM reset Dout

58 Tapped Delay Line A tapped delay line is a shift register with a programmable number of stages Set number of stages with delay controls to mux Ex: 0 63 stages of delay 58 clk Din SR32 SR16 SR8 SR4 SR2 SR1 Dout delay5 delay4 delay3 delay2 delay1 delay0

59 Serial In Parallel Out 1-bit shift register reads in serial data After N steps, presents N-bit parallel output 59 clk Sin P0 P1 P2 P3

60 Parallel In Serial Out Load all N bits in parallel when shift = 0 Then shift one bit out per cycle 60 shift/load clk P0 P1 P2 P3 Sout

61 Queues Queues allow data to be read and written at different rates. Read and write each use their own clock, data Queue indicates whether it is full or empty Build with SRAM and read/write counters (pointers) 61 WriteClk WriteData FULL Queue ReadClk ReadData EMPTY

62 FIFO, LIFO Queues First In First Out (FIFO) Initialize read and write pointers to first element Queue is EMPTY On write, increment write pointer If write almost catches read, Queue is FULL On read, increment read pointer Last In First Out (LIFO) Also called a stack Use a single stack pointer for read and write On write, pointer is incremented, on read, pointer is decremented. Reach last element = Full, reach 1 st element = EMPTY 62

63 Outline SRAM 2. DRAM 3. Read-Only Memory (ROM) 4. Serial Access Memory 5. Content-Addressable Memory 6. Programmable Logic Array

64 CAMs Extension of ordinary memory (e.g. SRAM) Read and write memory as usual Also match to see which words contain a key 64 adr data/key read write CAM match

65 10T CAM Cell Add four match transistors to 6T SRAM 56 x 43 l unit cell 65 word bit bit_b match cell cell_b

66 CAM Cell Operation 66 Read and write like ordinary SRAM For matching: Leave wordline low Precharge matchlines Place key on bitlines Matchlines evaluate address row decoder CAM cell clk weak miss match0 match1 match2 read/write Miss line Pseudo-nMOS NOR of match lines Goes high if no words match column circuitry data match3

67 Outline SRAM 2. DRAM 3. Read-Only Memory (ROM) 4. Serial Access Memory 5. Content-Addressable Memory 6. Programmable Logic Array

68 PLAs A Programmable Logic Array performs any function in sum-of-products form. Literals: inputs & complements Products / Minterms: AND of literals AND Plane Outputs: OR of Minterms Example: Full Adder s abc abc abc abc c ab bc ac out OR Plane a b c s cout Inputs Outputs bc ac ab abc abc abc abc 68 Minterms

69 NOR-NOR PLAs 69 ANDs and ORs are not very efficient in CMOS Dynamic or Pseudo-nMOS NORs are very efficient Use DeMorgan s Law to convert to all NORs AND Plane OR Plane AND Plane OR Plane bc bc ac ac ab ab abc abc abc abc abc abc abc abc a b c s c out a b c s c out

70 PLA Schematic & Layout 70 AND Plane OR Plane bc ac ab abc abc abc abc a b c s c out

71 PLAs vs. ROMs The OR plane of the PLA is like the ROM array The AND plane of the PLA is like the ROM decoder PLAs are more flexible than ROMs No need to have 2 n rows for n inputs Only generate the minterms that are needed Take advantage of logic simplification 71

72 Example: RoboAnt PLA Convert state transition table to logic equations 72 S 1:0 L R S 1:0 TR TL F X X X X X TR S S TL S F S S 1 0

73 RoboAnt Dot Diagram 73 S1' S S LS LRS S0' R LS LS 1 0 AND Plane OR Plane TR TL S S S F S S 1 0 S 0 S 1 S 0 LS 0 LS R 1 LRS LS 0 1 SS 1 0 S S 1 0 L R S 1 ' S ' 0 TR TL F

74 PLAs vs. ROMs 74 L, R ROM S' 1:0 S 1:0 TL, TR, F S1' S S LS LRS, S0' R LS LS TR S S, TL S, F S S S 1 S 0 L R AND Plane OR Plane :16 DEC S S 1 0 L R S 1 ' S ' 0 TR TL F S 0 S 1 S 0 LS 0 LS R 1 LRS LS 0 1 SS 1 0 S 1 ' S 0 ' TR'TL' F'

75 Reliability and Yield Semiconductor memories trade-off noise margin for density and performance 75 Thus, they are highly sensitive to noise (cross talk, supply noise) High density and large die size causes yield problems # of good chips / wafer Yield=100 # of chips / wafer Y = [(1 e AD )/(AD)] 2 Increase yield using error correction and redundancy

76 Alpha Particles 76 α -particle WL V DD BL n _ + _ SiO 2 1 Particle ~ 1 Million Carriers

77 Redundancy in the Memory Structure 78 Fuse bank Redundant row Row address Redundant columns Column address

78 Redundancy and Error Correction 79