Telematics group University of Göttingen, Germany

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1 Computer Science II Part 3 Assembly Language Prof. Dr. Dieter Hogrefe Dr. Xiaoming Fu Kevin Scott, M.A. Telematics group University of Göttingen, Germany Table of Content Introduction MIPS architecture CPU registers Memory map Basis of MIPS assembly language Use of labels Addressing Input/Output Instructions MIPS programming skills Control structures Stack and procedure calls How to write assembly language programs Summary 2 1

2 What is Assembly Language Assembly language is the symbolic representation of a computer s machine language More readable than coding in bits: instructions, registers, labels of memory units Directly operate hardware, using instructions defined by the CPU architecture We are going to study the assembly language for MIPS architecture (a family of RISC architecture) MIPS assembly language 3 Java/ Cprogram Compiler Translation of Programs: a Hierarchy Assembly language program High Level Language (HLL) programs first compiled (possibly into assembly), then linked and finally loaded into main memory. Assembler Compiler: translate programs in HLL into an equivalent program in machine or assembly language Assembler: translate assembly language into binary instructions. Linker: Combine a collection of object and library files into an executable file (machine language) that the computer can run Object: Machine language module Linker Object: Library routine (machine language) Executable: Machine language program Loader Memory 4 2

3 Execution Cycle Instruction Fetch Instruction Decode Operand Fetch Execute Result Store Next Instruction Load instruction from program storage Determine required actions and instruction size Locate and obtain operand data Compute result value or status Deposit results in storage for later use Determine next instruction 5 Levels of Abstraction High Level Language Program (e.g., C) Assembly Language Program (e.g., MIPS) Machine Language Program (MIPS) Datapath Transfer Specification Compiler Assembler Machine Interpretation temp = v[k]; v[k] = v[k+1]; v[k+1] = temp; lw $15, 0($2) lw $16, 4($2) sw$16, 0($2) sw$15, 4($2) IR Imem[PC]; PC PC + 4 ALUOP[0:3] InstReg[9:11] & MASK C code Assembly code Machine code Reasons to use HLL language? When is appropriate for using ASM language? 6 3

4 Review C Operators/Operands Operators: +, -, *, /, % (mod); (7/4==1, 7%4==3) Operands: Variables: fahr, celsius Constants: 0, 1000, -17, 15.4 In C (and most High Level Languages) variables declared and given a type first Example: int fahr, celsius; int a, b, c, d, e; 7 C Operators/Operands This is the Computation Model by ``State-Effects''. Programs move from state to state by means of assignments changing their state Assignment Statement: Variable = expression, e.g., celsius = 5*(fahr-32)/9; a = b+c+d-e; 8 4

5 Assembly Operators Syntax of Assembly Operator 1) operation by name Mnemonics'' 2) operand getting result Register or Memory 3) 1st operand for operation 4) 2nd operand for operation Ex. add b to c and put the result in a: add a, b, c Called an Assembly Language Instruction Equivalent assignment statement in C: a = b + c; 9 Assembly Operators/Instructions MIPS Assembly Syntax is rigid: 1 operation, 3 variables Why? Keep Hardware simple via regularity How to do the following C statement? a = b + c + d - e; Break into multiple instructions add a, b, c # a = sum of b & c add a, a, d # a = sum of b,c,d sub a, a, e # a = b+c+d-e To right of sharp sign (#) is a comment terminated by end of the line. Applies only to current line. C comments have format /* comment */, can span many lines 10 5

6 Assembly Operators/Instructions Note: Unlike C (and most other HLLs), each line of assembly contains at most one instruction add a,b,c add d,e,f add a,b,c add d,e,f WRONG RIGHT 11 Directives A directive is an instruction for the assembler (not the CPU) for reserving memory, telling the assembler where to place instructions, etc. E.g., in MIPS assembly language.data # data memory tmp:.word 0 # 32 bit variable.text.align 2.globl main # program memory # word alignment # main is global Here.data and.text are used by the assembler to decide where to put corresponding segments 12 6

7 Compilation How to turn the notation that programmers prefer into notation computer understands? Program to translate C statements into Assembly Language instructions; called a compiler Example: compile by hand this C code: a = b + c; d = a - e; Easy: add a, b, c sub d, a, e Big Idea: compiler translates notation from one level of computing abstraction to lower level 13 Compilation 2 Example: compile by hand this C code: f = (g + h) - (i + j); First sum of g and h. Where to put result? Add f, g, h # f contains g+h Now sum of i and j. Where to put result? Cannot use f! Compiler creates temporary variable to hold sum: t1 add t1, i, j # t1 contains i+j Finally produce difference sub f, f, t1 # f = (g+h)-(i+j) 14 7

8 Compilation -- Summary C statement (5 operands, 3 operators): f = (g + h) - (i + j); Becomes 3 assembly instructions (6 unique operands, 3 operators): add f,g,h # f contains g+h add t1,i,j # t1 contains i+j sub f,f,t1 # f=(g+h)-(i+j) In general, each line of C produces many assembly instructions One reason why people program in C vs. Assembly; fewer lines of code Other reasons? (many!) 15 Assembly Design: Key Concepts Assembly language is essentially directly supported in hardware, therefore... It is kept very simple! Limit on the type of operands Limit on the set operations that can be done to absolute minimum. if an operation can be decomposed into a simpler operation, don t include it. 16 8

9 Comments in Assembly Another way to make your code more readable: comments! Hash (#) is used for MIPS comments anything from hash mark to end of line is a comment and will be ignored Note: Different from C. C comments have format /* comment */, so they can span many lines 17 Getting Started: SPIM a MIPS Simulator SPIM is a simulator for MIPS assembly language reads a MIPS assembly language program. simulates each instruction. displays values of registers and memory supports breakpoints and single stepping provides simple I/O for interacting with user. 18 9

10 SPIM Versions SPIM is the command line version. XSPIM is X-Windows version (Unix workstations). (This is the version you will be using in the lab.) There is also a Windows version PCSpim. You can use any of these at home and they can be downloaded from: 19 SPIM Program MIPS assembly language. Must include a label main this will be called by the SPIM startup code (allows you to have command line arguments). Can include named memory locations, constants and string literals in a data segment

11 General Layout Data definitions start with.data directive Code definition starts with.text directive text is the traditional name for the memory that holds a program. Usually have a bunch of subroutine definitions and a main. 21 Simple Example.data # data memory tmp:.word 0 # 32 bit variable.text.align 2.globl main # program memory # word alignment # main is global main: lw $a0,tmp Please look at the example as shown in my PCspim window (what do you see?) 22 11

12 An Example Window in PCspim 23 Table of Content Introduction MIPS architecture CPU registers Memory map Basis of MIPS assembly language Use of labels Addressing Input/Output Instructions MIPS programming skills Control structures Stack and procedure calls How to write assembly language programs Summary 24 12

13 MIPS Architecture (Summary) Instruction Categories Load/Store Computational Jump and Branch Floating Point (coprocessor) Memory Management Special Registers R0 - R31 PC HI LO 3 Instruction Formats: all 32 bits wide R: I: J: OP Rs Rt rd sa funct OP Rs Rt Immediate OP jump target 25 Assembly Variables: Registers (1/4) Unlike HLL, assembly cannot use variables Why not? Keep Hardware Simple Assembly Operands are registers limited number of special locations built directly into the hardware operations can only be performed on these! Benefit: Since registers are directly in hardware, they are very fast 26 13

14 Assembly Variables: Registers (2/4) Drawback: Since registers are in hardware, there are a predetermined number of them Solution: MIPS code must be very carefully put together to efficiently use registers 32 registers in MIPS Why 32? Smaller is faster Each MIPS register is 32 bits wide Groups of 32 bits called a word in MIPS 27 Assembly Variables: Registers (3/4) Registers are numbered from 0 to 31 Each register can be referred to by number or name Number references: $0, $1, $2, $30, $

15 Assembly Variables: Registers (4/4) By convention, each register also has a name to make it easier to code For now: $16 - $22 $s0 - $s7 (correspond to C variables) $8 - $15 $t0 - $t7 (correspond to temporary variables) In general, use register names to make your code more readable 29 Example $0 is hardwired to value 0; it can also be written as $zero. This makes it convenient to initialize registers to specific values E.g., we can initiate the content of $t0 to the value 0 or to the value 16 as follows: add $t0, $0, $0 # initialize $t0 to the value 0 addi $t0, $0, 16 # initialize $t0 to the value 16 This is also useful to move values between registers E.g., if we wish to move the content of register $t0 to $t7: add $t7, $t0, $zero Of course, alternatively one can use move instruction: move $t7, $t

16 Memory Addresses As the purpose of cache is to transparently speed up memory access, our abstract view of memory does not show cache. Data: MIPS memory is an array of 2 32 bytes. Each byte has a 32-bit address. Each byte can hold an 8-bit data, one of the 256 possible 8-bit data. The addresses of MIPS main memory range from 0x to 0xFFFFFFFF. However, user programs and data are restricted to the first 2 31 bytes. The last half of the address space is used for specialized purposes. OPERATIONS: The CPU interacts with memory by moving data between memory and its registers. Load: a bit pattern starting at a designated address in memory is copied into a register inside the processor. Store: a bit pattern is copied from a processor register to memory at a designated address. Data are copied between the memory and the processor in groups of 1, 2, 4 or 8 contiguous bytes. Only the address of the first byte of memory is specified. 0xFFFF FFFF... 0x x x x Main memory addresses 31 MIPS Memory Map 0x x : reserved (unavailable by user programs) Text segment stores machine-level instructions starting at 0x Instructions are 32-bit words and are constrained to be stored starting on word boundaries. Data segment starts at 0x , stores data in memory. Data can be either static (e.g, char, static int) or dynamic (e.g., malloc(), free() in c). Stack segment locates below 0x7FFFFFFF. With high level languages, local variables and parameters are pushed and popped on the stack as procedures are activated and deactivated. Each segment should be 32-bit aligned (padded) 0xFFFF FFFF. 0x x7FFFFFFF 0x x x Reserved for ROM and OS Stack Segment Data Segment Text Segment Reserved MIPS memory map 32 16

17 Table of Content Introduction MIPS architecture CPU registers Memory map Basis of MIPS assembly language Use of labels Addressing Input/Output Instructions MIPS programming skills Control structures Stack and procedure calls How to write assembly language programs Summary 33 True Assembly Language MIPS (Million Instructions Per Second) Pseudo-instruction: A MIPS instruction that doesn t turn directly into a machine language instruction. This makes the MIPS assembly language to be more programmer friendly What happens with pseudo instructions? They re broken up by the assembler into several real MIPS instructions. But what is a real MIPS instruction? 34 17

18 Example Pseudoinstructions Register Move move reg2,reg1 Expands to: add reg2,$zero,reg1 Load Immediate li reg,value If value fits in 16 bits: ori reg,$zero,value else: lui reg,upper 16 bits of value ori reg,$zero,lower 16 bits 35 True Assembly Language MAL (MIPS Assembly Language): the set of instructions that a programmer may use to code in MIPS; this includes pseudoinstructions TAL (True Assembly Language): the set of instructions that can actually get translated into a single machine language instruction (32-bit binary string) A program must be converted from MAL into TAL before it can be translated into 1s and 0s

19 Labels also allow Programmer-Friendly Consider a data directives as follows:.data L1:.word 0x22 # start of data segment # therefore L1 is address 0x L2:.asciiz Print me! # Print me! only uses 9 bytes + 1byte # for null termination character.align 2 # this lets the assembler to move to # next word boundary, L3:.space 32 # thus the value of L3 is 0x Here, L1, L2 and L3 are labels. The value of a label is actually a memory address 37 Table of Content Introduction MIPS architecture CPU registers Memory map Basis of MIPS assembly language Use of labels Addressing Input/Output Instructions MIPS programming skills Control structures Stack and procedure calls How to write assembly language programs Summary 38 19

20 Assembly Operands: Memory C variables map onto registers; what about large data structures like arrays? 1 of 5 components of a computer: memory contains such data structures But MIPS arithmetic instructions only operate on registers, never directly on memory. Data transfer instructions transfer data between registers and memory: Memory to register Register to memory Addressing mode: the way of which addresses for memory access are constructed. 39 Data Transfer: Memory to Reg (1/4) To transfer a word of data, we need to specify two things: Register: specify this by number (0-31), or name ($t0..) Memory address: more difficult - Think of memory as a single one-dimensional array, so we can address it simply by supplying a pointer to a memory address. This pointer can be a label or content of a register. - Other times, we want to be able to offset from this pointer

21 Data Transfer: Memory to Reg (2/4) To specify a memory address to copy from, specify two things: A register which contains a pointer to memory A numerical offset (in bytes) The desired memory address is the sum of these two values. Example:8($t0) specifies the memory address pointed to by the value in $t0, plus 8 bytes 41 Data Transfer: Memory to Reg (3/4) Load Instruction Syntax: 1 2, 3(4) where 1) operation (instruction) name (lw, lui, etc) 2) register that will receive value 3) numerical offset in bytes 4) register containing pointer to memory Instruction Name: lw (meaning Load Word, so 32 bits or one word are loaded at a time) 42 21

22 Example: lw Data Transfer: Memory to Reg (4/4) $t0, 12($s0) This instruction will take the pointer in $s0, add 12 bytes to it, and then load the value from the memory pointed to by this calculated sum into register $t0 Notes: $s0 is called the base register 12 is called the offset offset is generally used in accessing elements of array or structure: base register points to beginning of array or structure 43 Data Transfer: Reg to Memory Also want to store value from a register into memory Store instruction syntax is identical to Load instruction syntax Instruction Name: sw (meaning Store Word, so 32 bits or one word are loaded at a time) Example: sw $t0, 12($s0) This instruction will take the pointer in $s0, add 12 bytes to it, and then store the value from register $t0 into the memory address pointed to by the calculated sum 44 22

23 Pointers vs. Values Key Concept: A register can hold any 32-bit value. That value can be a (signed) int, an unsigned int, a pointer (memory address), etc. If you write lw $t2, 0($t0) then, $t0 better contain a pointer What if you write add $t2,$t1,$t0 then, $t0 and $t1 must contain? 45 Addressing: Byte vs. word Every word in memory has an address, similar to an index in an array Early computers numbered words like C numbers elements of an array: Memory[0], Memory[1], Memory[2], Called the address of a word Computers needed to access 8-bit bytes as well as words (4 bytes/word) Today machines address memory as bytes, hence word addresses differ by 4 Memory[0], Memory[4], Memory[8], 46 23

24 Notes about Memory Forgetting that sequential word addresses in machines with byte addressing do not differ by 1. Many assembly language programmers have endured the errors made by assuming that the address of the next word can be found by incrementing the address in a register by 1 instead of by the word size in bytes. So REMEMBER that for both lw and sw, the sum of the base address and the offset must be a multiple of 4 (to be word aligned) 47 More Notes about Memory: Alignment MIPS requires that all words start at addresses that are multiples of 4 bytes Bytes in Word Aligned Not Aligned Word Location Called Alignment: objects must fall on address that is multiple of their size

25 Role of Registers vs. Memory What if more variables than registers? Compiler tries to keep most frequently used variable in registers Writing less frequently used to memory: spilling Why not keep all variables in memory? Smaller is faster: registers are faster than memory Registers more versatile: MIPS arithmetic instructions can read 2, operate on them, and write 1 per instruction MIPS data transfer only read or write 1 operand per instruction, and no operation 49 Big Idea: Stored-Program Concept Computers built on 2 key principles: 1) Instructions are represented as numbers. 2) Therefore, entire programs can be stored in memory to be read or written just like numbers (data). Simplifies SW/HW of computer systems: Memory technology for data also used for programs 50 25

26 Result #1: Everything Addressed Since all instructions and data are stored in memory as numbers, everything has a memory address: instructions, data words both branches and jumps use these C pointers are just memory addresses: they can point to anything in memory Unconstrained use of addresses can lead to nasty bugs; up to you in C; limits in Java One register keeps address of instruction being executed: Program Counter (PC) Basically a pointer to memory: Intel calls it Instruction Address Pointer, which is better 51 Result #2: Binary Compatibility Programs are distributed in binary form Programs bound to specific instruction set Different version for Macintosh and IBM PC New machines want to run old programs ( binaries ) as well as programs compiled to new instructions Leads to instruction set evolving over time Selection of Intel 8086 in 1981 for 1st IBM PC is major reason latest PCs still use 80x86 instruction set (Pentium 4); could still run program from 1981 PC today 52 26

27 Table of Content Introduction MIPS architecture CPU registers Memory map Basis of MIPS assembly language Use of labels Addressing Input/Output Instructions MIPS programming skills Control structures Stack and procedure calls How to write assembly language programs Summary 53 I/O How a MIPS program to communicate with the user? I/O provides means for writing to the console and reading from console. Example: suppose we d like to print $t0 content to the console as an integer value, following 3 steps: Place $t0 content in $a0 (e.g., add $a0, $t0, $0) Place a code print integer (1) in $v0 (e.g., addi $v0, $0, 1) Execute the instruction syscall Code:.text addi $v0, $0, 1 #place the value 1 in $v0 add $a0, $t0, $0 #place $t0 content in $a0 syscall MIPS defines other I/O functions, e.g., print character (4), read from console (5). We now study MIPS ASM I/O by examples 54 27

28 I/O Example (1) How to print string Enter Number: to the console? Note the code for print string is 4.data str:.asciiz Enter Number:.text addi $v0, $0, 4 #code for print string la $a0, str syscall #$a0 = string address # will cause the string to # be printed in the console Here, a new instruction la (load address) is used to place the value of str into a register. $a0 content is the starting address of the string (str). The string Enter Number: is terminated in memory by a null termination character. 55 I/O Example (2) How to get the value typed in the console window (by the user) into a register? There is a I/O syscall with code 5 for doing this. The value will be stored in the register $v0, and can be later moved to other space..data str:.asciiz Enter Number: L1:.word 0x0 # has the same effect as.space 4.text addi $v0, $0, 4 #code for print string la $a0, str #$a0 = string address syscall # print string in the console addi $v0, $0, 5 #code for reading from console syscall # read the value typed in the console sw $v0, L1($0) # store the value into the data segment 56 28

29 Table of Content Introduction MIPS architecture CPU registers Memory map Basis of MIPS assembly language Use of labels Addressing Input/Output Instructions MIPS programming skills Control structures Stack and procedure calls How to write assembly language programs Summary 57 Instructions: a Review (registers): C variables: $s0-$s7 Temporary variables: $t0-$t9 Zero: $zero Register content is viewed as single 32-bit number (such as signed or unsigned integer): We have learnt some memory access instructions: lw, sw Arithmetic: add, addi, sub Branches and jumps View register content in bit-wise way: Logical instructions shifts 58 29

30 DataPath Diagram Program Counter (PC) Cache Memory Out Instruction Register ALU Address Control Logic Rs Rd Rt Data In Register File 4 59 Addition and Subtraction Syntax of Instructions: 1 2, 3, 4 where: 1) operation by name 2) operand getting result (destination) 3) 1st operand for operation (source1) 4) 2nd operand for operation (source2) Syntax is rigid: 1 operator, 3 operands Why? Keep Hardware simple via regularity 60 30

31 Instructions as Numbers Currently all data we work with is in words (32-bit blocks): Each register is a word. lw and sw both access memory one word at a time. So how do we represent instructions? Remember: Computer only understands 1s and 0s, so add $t0,$0,$0 is meaningless. MIPS wants simplicity: since data is in words, make instructions be words... One word is 32 bits, so divide instruction word into fields. Each field tells computer something about instruction. We could define different fields for each instruction, but MIPS is based on simplicity, so define 3 basic types of instruction formats: R-format I-format J-format 61 Three Instruction Word Formats Register Format Op-Code Rs Rt Rd Code Op-Code Rs Rt Rd Code Immediate Format Op-Code Rs Rt 16 - Bit Immediate Value Op-Code Rs Rt 16 - Bit Immediate Value Jump Format Op-Code Bit Bit Current Current Segment Address Address

32 A Register Transfer Description of the Control Logic IR = Mem[PC] PC = PC + 4 Decode Instruction lw or sw Read from Reg. File Address = Rs + Offset R-Type sw Memory[Address] = Rt lw beqz If (Rs == 0 ) then PC = PC + Offset Reg. File[Rt] = Memory[Address] Reg. File[Rd] = Rs operation Rt 63 Branches and jumps Branch instructions (beq, bgez, bne, beqz, ble, bnez, etc.) use a signed 16-bit offset field; hence they can jump 2^15-1 instructions (not bytes) forward or 2^15 instructions backward. How do we usually use branches? Answer: if-else, while, for Function calls and unconditional jumps are done using jump instructions (j and jal), not the branches. The jump instruction contains a 26-bit address field

33 Branch Example (1/2) MIPS Code: Loop: beq $9,$0,End add $8,$8,$10 addi $9,$9,-1 j Loop End: Immediate Field in page 62: Number of instructions to add to (or subtract from) the PC, starting at the instruction following the branch. In this case, immediate = 3 65 Branch Example (2/2) MIPS Code: Loop: beq $9,$0,End add $8,$8,$10 End: addi $9,$9,-1 j Loop decimal representation: binary representation:

34 Translation of if then -- else if ($t8 < 0) then {$s0 = 0 - $t8; $t1 = $t1 +1} else {$s0 = $t8; $t2 = $t2 + 1} Translation of pseudocode to MIPS assembly language. Comments are very useful - notice how the comments in the code below help to make the connection back to the original pseudocode. bgez $t8, else # if ($t8 is > or = zero) branch to else sub $s0, $zero, $t8 # $s0 gets the negative of $t8 addi $t1, $t1, 1 # increment $t1 by 1 b next # branch around the else code else: ori $s0, $t8, 0 # $s0 gets a copy of $t8 addi $t2, $t2, 1 # increment $t2 by 1 next: 67 Translation of a While statement $v0 = 1 While ($a1 < $a2) do {$t1 = mem[$a1]; $t2 = mem[$a2]; If ($t1!= $t2) go to break; $a1 = $a1 +1; $a2 = $a2 1;} return break: $v0 = 0 return Here is a translation of the above while pseudocode into MIPS assembly language code. li $v0, 1 # Load $v0 with the value 1 loop: bgeu $a1, $a2, done # If( $a1 >= $a2) Branch to done lb $t1, 0($a1) # Load a Byte: $t1 = mem[$a1 + 0] lb $t2, 0($a2) # Load a Byte: $t2 = mem[$a2 + 0] bne $t1, $t2, break # If ($t1!= $t2) Branch to break addi $a1, $a1, 1 # $a1 = $a1 + 1 addi $a2, $a2, -1 # $a2 = $a2-1 b loop # Branch to loop break: li $v0, 0 # Load $v0 with the value 0 done: 68 34

35 Translation of a for loop $a0 = 0; For ( $t0 =10; $t0 > 0; $t0 = $t0-1) do {$a0 = $a0 + $t0} The following is a translation of the above for-loop pseudocode to MIPS assembly language code. li $a0, 0 # $a0 = 0 li $t0, 10 # Initialize loop counter to 10 loop: add $a0, $a0, $t0 addi $t0, $t0, -1 # Decrement loop counter bgtz $t0, loop # If ($t0 >0) Branch to loop 69 Things to Remember Simplifying MIPS: Define instructions to be same size as data (one word) so that they can use the same memory (can use lw and sw). Machine Language Instruction: 32 bits representing a single instruction R I opcode rs rt rd shamt funct opcode rs rt immediate Computer actually stores programs as a series of these

36 I-Format Problem (1/2) It is possible addi, lw, and sw will use immediates small enough to fit in the immediate field. New instruction: lui register, immediate stands for Load Upper Immediate takes 16-bit immediate and puts these bits in the upper half (high order half) of the specified register sets lower half to 0s 71 I-Format Problem (2/2) Solution to the Problem (continued): So how does lui help us? Example: addi $t0,$t0, 0xABABCDCD becomes: lui $at, 0xABAB ori $at, $at, 0xCDCD add $t0,$t0,$at Now each I-format instruction has only a 16-bit immediate

37 Some Logical Instructions NOT rdest, rsrc OR rd, rs, rt ORI rt, rs, imm AND rd, rs, rt ANDI rt, rs, imm and so on 73 Table of Content Introduction MIPS architecture CPU registers Memory map Basis of MIPS assembly language Use of labels Addressing Input/Output Instructions MIPS programming skills Control structures Stack and procedure calls How to write assembly language programs Summary 74 37

38 Structured Programming MIPS assembly language allows us build programs for MIPS processors, based on a the MIPS instruction set To build a reliable program, structured programming is useful. Programs are build up of certain blocks, each with a single entry point and a single exit point. No jump into a block, or bugs may happen Q: How is a code block implemented in assembly language? 75 Three control structures of programming Code blocks in sequence Instructions are executed in sequence by default Alternation (If-then-else) of two code blocks In implementation, this may involve branch and other instructions Q: is if-endif also structured programming? Iteration (while-loop) of a code block Q: Would it be a good idea to implement a complicated code block as a subroutine (as a procedure call / function)? 76 38

39 Building Structures in Assembly Language Way: by using two types of instructions Jump instructions j instruction (jump) Conditional branch instructions beq instruction (branch equal) bne instruction (branch not equal) 77 Jump instruction jump corresponds to a change in PC (which needs a branch delay to be finished) J-format instruction can only specify 26-bit address j target # after a delay of one machine cycle # PC addr of target This 26bit address is transformed into a 32bit address as follows: 6bit 26bit Machine code: PC: bit jump-addr: Q: Before jumping to the 32bit jump-address, which address is in the PC? 78 39

40 Conditional Branches A conditional branch instruction branches to a new address only if a certain condition is true. beq u,v,addr # if register $u == register $v # PC addr (after a branch delay) #else # no effect. The same restriction as jump instruction is that they should also be limited to 26bit addr ( local ) 79 Ifs and whiles Branch instructions are used to implement both loops and branches. An example based on beq:... # load values into $8 and $9 beq $8,$9,cont # branch if equal nop # branch delay slot... # conditionally... # executed... # instructions cont: add $10,$10,$11 # always executed CONT beq $8, $9, CONT Conditionally executed instructions $8 == $

41 Alternations A conditional branch (e.g., beq) + a jump... # load values into # $8 and $9 beq $8,$9,equal # branch if equal nop # branch delay slot... #... # false branch... # j cont nop equal:... #... # true branch... # cont: add $10,$10,$11 # always executed $8 $9 $8 == $9 beq $8, $9, CONT False Branch CONT True Branch 81 Loop and branch example: string length str:.data.asciiz "Time is space." This represents a string Time\0x20is\0x20the\0x20ghost\0x20of\0x20space.\0x00 How this is stored in MIPS memory? Data segment e m i T _ si _ c aps /.e [0x ] 0x656d6954 0x x x00002e65 Q: Should \0x00 (null) also be counted as 1 byte of the string? 82 41

42 .data string:.asciiz "Time is space." ## End of file String length (cont.) ## start ## Count the characters in a string ## ## Registers: count = 0 ## $8 --- count ## $9 --- pointer to the char ## $ the char (in low order byte) point to first char ##.text.globl main # Initialize char is null? YES main: ori $8,$0,0 # count = 0 lui $9, 0x1001 # point to first char # while not ch==null do loop: lbu $10, ($9) # get the char count ++ $10, $0, done # exit loop if char == null addiu,, # count ++ addiu,, # point at next char point to next char j loop # finish done: sll $0,$0,0 # shift left logically, cause a branch delay end 83 How viruses work Virus usually written in assembly language Inserted into another program Virus dormant until program executed Then infects other programs Eventually executes its payload Types: companion, executable program, memory, boot sector, macro, source code 84 42

43 Starting address Virus example: executable program Executable program Header a) b) c) d) A non-infected executable program in the file system With a parasitic virus at the front at the end Spread over free space within the program (cavity virus) When run the infected file, the virus is loaded into memory and may infect others Q: Which instruction in ASM will be the first instruction on start of a text segment? Executable program Virus Header Virus Executable program Header Virus Virus Virus Virus Header 85 Table of Content Introduction MIPS architecture CPU registers Memory map Basis of MIPS assembly language Use of labels Addressing Input/Output Instructions MIPS programming skills Control structures Stack and procedure calls How to write assembly language programs Summary 86 43

44 Stack Stack: LIFO (Last In First Out) data structure Stack pointer register in MIPS Point to the top of the stack $sp, namely $29 Push: Pop: 0x7FFFFFFC 0x7FFFFFF9 0x7FFFFFF5 # PUSH the item in $t0: sub $sp,$sp,4 # point to the place for the new item, sw $t0,($sp) # store $t0 content as the new top. # POP the item into $t0: lw $t0,($sp) # Copy top the item to $t0. add $sp,$sp,4 # Point to the item beneath the old top. Q: When an item in the stack is popped, does the item value remain in memory? $sp $sp Run-time Stack Data and stack segments shares a section of memory space With a program runs: the stack grows downward into the available space the data segment grows upward Initial value of $sp is 0x7FFFFFFC 0xFFFF FFFF. 0x x7FFFFFFF 0x x x Reserved for ROM and OS Stack Segment Data Segment Text Segment Reserved MIPS memory map 88 44

45 Subroutine All high level languages have the concept of a subroutine (sometimes called procedure, function, or method). A subroutine is a logical division of the code that may be regarded as a self-contained operation. A subroutine might be executed several times with different data as the program executes. In assembly languages, there is also such concept. 89 Callers and Callees A subroutine call is when a main routine (or other routine) passes control to a subroutine. The main routine is said to be the CALLER and the subroutine is said to be the CALLEE. A return from a subroutine is when a subroutine passes control back to its CALLER

46 Callers and Callees (cont.) When the CALLEE finishes execution it normally returns control to its CALLER, i.e., load the PC (program counter) with the return address. The next instruction fetch of the machine cycle will get the instruction from that address. Q: How should the return address be passed to the subroutine? (i) By placing it in main memory somewhere, or (ii) By placing it in a register designated for this purpose. 91 jal instruction The register that is used for linkage is register $31, namely $ra. It holds the return address for a subroutine. jal instruction puts the return address into $ra. How the jal instruction works? # when the jal is loaded the PC has 0x # next (in the machine cycle) the PC is increased to 0x jal sub: $ra PC+4 # $ra 0x (address 8 bytes away from the jal) PC sub # load the PC with 0x (the subroutine entry point) 92 46

47 jr instruction The jr instruction is used to return to the callee. It copies the contents of e.g., $ra into the PC: jr $ra # PC $ra 93 Simple Subroutine Conventions A subroutine is called using jal. A subroutine will NOT call another subroutine. The subroutine returns to its caller using jr $ra. Register use is as follows: $t0 - $t9 The subroutine is free to change these registers. $s0 - $s7 The subroutine must not change these registers. $a0 - $a3 These registers contain arguments for the subroutine. The subroutine can change them. $v0 - $v1 These registers contain values returned from the subroutine. $ra return address $sp stack pointer $gp global pointer, used to access static variables 94 47

48 What happens while executing a subroutine Before entering: Pass arguments into registers $a1-$a3 from left to right, and pushing any other arguments into the stack from right to left. Save registers used by the caller (PUSH) Execute a jal instruction to jump to a callee s first instruction and save the return address in $ra. When returning: Place in the return values in registers $v0-$v1 Restore all registers saved while entering (POP) End subroutine with a jump register instruction (jr $ra) 95 Example Goal: to read three integers from the user and compute the sum Outline of the program: # read first integer # read second integer # read third integer # compute the sum # write out the result 96 48

49 Subroutine pread # pread -- prompt for and read an integer # # on entry: # $ra -- return address # # on exit: # $v0 -- the integer.text.globl pread pread: la $a0,prompt # print string li $v0,4 # service 4 syscall li $v0,5 # read int into $v0 syscall # service 5 # return.data prompt:.asciiz "Enter an integer:" 97 Main program.text.globl main main: jal # read first integer move $s0,$v0 # save it in $s0 jal # read second integer move $s1,$v0 # save it in $s1 jal # read third integer move $s2,$v0 # save it in $s2 addu $s0,$s0,$s1 # compute the sum addu $a0,$s0,$s2 li $v0,1 # print the sum syscall li $v0,10 # exit syscall 98 49

50 Table of Content Introduction MIPS architecture CPU registers Memory map Basis of MIPS assembly language Use of labels Addressing Input/Output Instructions MIPS programming skills Control structures Procedure call How to write assembly language programs Summary 99 Programming in assembly language Task analysis, divide it into modules (blocks) Draw a flow chart for each module. Create pseudo-codes as comments without executable instructions. Distinguish between constants and variables needed Constant strings ASCII text in the program.data area Variables registers (or RAM when large amount) & allocation Identify the right places of labels for Entry points to module Return points for loops Destination of forward branch Work through the flow chart to implement the assembly instructions Test by assembling the program and running it Testing can be done on the actual target machine or using a simulator. In our case we use SPIM simulator

51 Summary Assembly language v.s. High-level languages Assembly language is machine-specific MIPS ASM is for MIPS machines, a RISC architecture MIPS registers: PC, $sp, $ra, other general registers Memory map and addressing, ref. CPU datapath cycle Basic arithmetic & memory operations, data segment & alignment Concept of pseudo-instructions Input/Output Branch and jump instructions control structures Stack and procedure calls; register usage conventions MIPS assembly language programming by examples; run & test in SPIM simulator 101 Instruction Categories Load/Store Computational (arithmetic) Jump and Branch Floating Point (coprocessor) Memory Management Special: I/O MIPS Architecture (Summary) Registers R0 - R31 PC HI LO 3 Instruction Formats: all 32 bits wide R: I: J: OP Rs Rt rd sa funct OP Rs Rt Immediate OP jump target MIPS memory map 0xFFFF FFFF. 0x x7FFFFFFF 0x x x Reserved for ROM and OS Stack Segment Data Segment Text Segment Reserved