Overview of Control. CS 152 Computer Architecture and Engineering Lecture 11. Multicycle Controller Design

Transcription

1 S 152 ompute chitectue and Engineeing Lectue 11 Multicycle ontolle Design Oveview of ontol ontol may be designed using one of seveal initial epesentations. The choice of sequence contol, and how logic is epesented, can then be detemined independently; the contol can then be implemented with one of seveal methods using a stuctued logic technique. Initial Repesentation Finite State Diagam Micopogam Ma 8, 1999 John Kubiatowicz (http.cs.bekeley.edu/~kubiton) Sequencing ontol Explicit Next State Micopogam counte Function + Dispatch ROMs Logic Repesentation Logic Equations Tuth Tables lectue slides: Lec11.1 Implementation PL ROM Technique hadwied contol micopogammed contol Lec11.2 Recap: Macoinstuction Intepetation The ig Pictue: Whee ae We Now? Main Memoy execution unit DD SU ND... DT Use pogam plus Data this can change! one of these is mapped into one of these The Five lassic omponents of a ompute Pocesso ontol Memoy Datapath Output PU contol memoy ND micosequence e.g., Fetch alc Opeand dd Fetch Opeand(s) alculate Save nswe(s) Lec11.3 Today s Topics: Micopogamed contol dministivia; ouses Micopogam it youself Exceptions Into to Pipelining (if time pemits) Lec11.4

2 Recap: Hoizontal vs. Vetical Micopogamming Recap: Designing a Micoinstuction Set NOTE: pevious oganization is not TRUE hoizontal micopogamming; egiste decodes give flavo of encoded micoopeations Most micopogamming-based contolles vay between: hoizontal oganization (1 contol bit pe contol point) vetical oganization (fields encoded in the contol memoy and must be decoded to contol something) Hoizontal + moe contol ove the potential paallelism of opeations in the datapath - uses up lots of contol stoe Vetical + easie to pogam, not vey diffeent fom pogamming a RIS machine in assembly language - exta level of decoding may slow the machine down 1) Stat with list of contol signals 2) Goup signals togethe that make sense (vs. andom): called fields 3) Places fields in some logical ode (e.g., LU opeation & LU opeands fist and micoinstuction sequencing last) 4) eate a symbolic legend fo the micoinstuction fomat, showing name of field values and how they set the contol signals Use computes to design computes 5) To minimize the width, encode opeations that will neve be used at the same time Lec11.5 Lec11.6 ltenative datapath (book): Multiple ycle Datapath Miminizes Hadwae: 1 memoy, 1 adde PW P PWond Zeo IoD MemW IRW 0 Mux 1 Rd Ideal Memoy Wd Din Dout Instuction Reg RegDst Rs Rt 5 Rt 0 5 Rd 1 1 Mux 0 Mem Data Reg Imm 16 Mux ExtOp Extend RegW Ra Rb bus Reg File Rw busw bus << 2 MemtoReg LUSel 4 PSc 0 Mux Mux 0 LUSel Zeo LU LU ontol LUOp LU Out Lec11.7 Finite State Machine (FSM) Spec R-type <= fun 0100 R[d] <= 0101 ORi <= o ZX 0110 R[t] <= 0111 IR <= MEM[P] P <= P LW <= + SX 1000 M <= MEM[] 1001 R[t] <= M 1010 instuction fetch decode SW <= + SX 1011 MEM[] <= 1100 EQ Q: How impove to do something in state 0001? <= P +SX 0010 If = then P <= 0011 Execute Memoy Wite-back Lec11.8

3 Single it ontol 1&2) Stat with list of contol signals, gouped into fields Signal name Effect when deasseted Effect when asseted LUSel 1st LU opeand = P 1st LU opeand = Reg[s] RegWite None Reg. is witten MemtoReg Reg. wite data input = LU Reg. wite data input = memoy RegDst Reg. dest. no. = t Reg. dest. no. = d MemRead None Memoy at addess is ead, MDR <= Mem[add] MemWite None Memoy at addess is witten IoD Memoy addess = P Memoy addess = S IRWite None IR <= Memoy PWite None P <= PSouce PWiteond None IF LUzeo then P <= PSouce PSouce PSouce = LU PSouce = Signal name Value Effect LUOp 00 LU adds 01 LU subtacts 10 LU does function code 11 LU does logical OR LUSel 000 2nd LU input = Reg[t] 001 2nd LU input = nd LU input = sign extended IR[15-0] 011 2nd LU input = sign extended, shift left 2 IR[15-0] 100 2nd LU input = zeo extended IR[15-0] Lec11.9 Multiple it ontol Stat with list of contol signals, cont d Fo next state function (next micoinstuction addess), use Sequence-based contol unit fom last lectue alled micop o µp vs. state egiste Signal Value Effect Sequen 00 Next µaddess = 0 -cing 01 Next µaddess = dispatch ROM 10 Next µaddess = µaddess + 1 ould even include banch option which changes micop by adding offset when cetain contol signals ae tue. 1 dde µddess Select Logic micop Mux ROM Opcode Lec ) Micoinstuction Fomat: unencoded vs. encoded fields Field Name Width ontol Signals Set wide naow LU ontol 4 2 LUOp SR1 2 1 LUSel SR2 5 3 LUSel LU Destination 3 2 RegWite, MemtoReg, RegDst Memoy 4 3 MemRead, MemWite, IoD Memoy Registe 1 1 IRWite PWite ontol 4 3 PWite, PWiteond, PSouce Sequencing 3 2 ddtl Total width bits 4) Legend of Fields and Symbolic Names Field Name Values fo Field Function of Field with Specific Value LU dd LU adds Subt. LU subtacts Func code LU does function code O LU does logical OR SR1 P 1st LU input = P s 1st LU input = Reg[s] SR2 4 2nd LU input = 4 Extend 2nd LU input = sign ext. IR[15-0] Extend0 2nd LU input = zeo ext. IR[15-0] Extshft 2nd LU input = sign ex., sl IR[15-0] t 2nd LU input = Reg[t] destination d LU Reg[d] = t LU Reg[t] = t Mem Reg[t] = Mem Memoy Read P Read memoy using P Read LU Read memoy using LU output Wite LU Wite memoy using LU output Memoy egiste IR IR = Mem P wite LU P = LU ond IF LU Zeo then P = Sequencing Seq Go to sequential µinstuction Fetch Go to the fist micoinstuction Dispatch Dispatch using ROM. Lec11.11 Lec11.12

4 Micopogam it youself! Label LU SR1 SR2 LU Dest. Memoy Mem. Reg. P Wite Sequencing Fetch: dd P 4 Read P IR LU Seq dministivia Enjoyed meeting eveyone afte midtem ee and pizza was a geat way to say hello to eveyone Lots of people heading fo industy. Midtem gaded, scoes posted veage scoe: 70.0 Std. Dev: 16.8 Now, stat eading hapte 6 Lec11.13 Lec11.14 Midtem I distibution Multiplie Midtem 1 Distibution Multiplicand Multiplie Multiplicand Registe LoadMp Fequency VG: 70.0 STD: 16.8 Save out out -bit dde HI egiste ( bits) LO egiste ( bits) Shiftll LO[0] ontol Logic Scoe LoadHI leahi LoadLO Result[HI] Result[LO] Lec11.15 Lec11.16

5 Single it ooth Multiplie HI[31] out Multi[31] -bit LU Multiplicand Multiplicand Registe Sub/dd LoadMp Multiplie ontol Logic Double it ooth Multiplie =>34 signex 34 Multiplicand Multiplicand Registe =>34 signex << LoadMp x2 MUX Multi x2/x1 34 Multiplie Save out HI egiste ( bits) LoadHI leahi Result[HI] LO egiste ( bits) LoadLO Result[LO] Shiftll Pev LO[0] ooth Encode EN[1] EN[0] "LO[0]" 2 Exta 2 bits 2 34-bit LU 34 HI egiste (16x2 bits) LoadHI leahi Sub/dd 2 LO egiste (16x2 bits) LoadLO Shiftll Pev LO[1] 2 LO[1:0] ooth Encode EN[2] EN[1] EN[0] "LO[0]" ontol Logic Lec /8/99 U Sping 1999 Result[HI] Result[LO] Lec11.18 dministivia: ouses to conside duing Telebeas Geneal Philosophy Take couses fom geat teaches (HKN atings helps find them) - Take vaiety of undegad couses now to get intoduction to aeas; can lean advanced mateial on own late once know vocabulay Who knows what you will wok on ove a 40 yea caee? S169 Softwae Engineeing Eveyone wites pogams, even hadwae designes Often pogams ae witten in goups => lean skill in school EE122 Intoduction to ommunication Netwoks Wold is getting connected; communications must play majo ole S162 Opeating Systems ll special-pupose hadwae will un a laye of softwae that uses pocesses and concuent pogamming; S162 is the closest thing Lec11.19 Lab4: stat using test benches Idea: wap testing infastuctue aound devices unde test. Include test vectos that ae supposed to detect eos in implementation. Even stange ones an (and pobably should in late labs) include asset statements to check fo things that should neve happen Test ench Device Unde Test Inline vectos sset Statements File IO (eithe fo pattens o output diagnostics) omplete Top-Level Design Inline Monito Output in eadable fomat (disassembly) sset Statements Lec11.20

6 n ltenative Multiycle DataPath What about a 2-us Micoachitectue (datapath)? -us next P P inst mem Reg IR S mem File ZX SX In each clock cycle, each us can be used to tansfe fom one souce µ-instuction can simply contain -us and W-Dst fields us W-us Instuction Fetch next P P IR ZXSX Decode / Opeand Fetch Reg File S Mem M -us us next P P IR ZXSX Reg File S Mem M Lec11.21 Lec11.22 Load Execute Mem next P next P Wite-back next P P P P IR ZXSX IR ZXSX IR ZXSX Reg File Reg File Reg File S S S Mem add Mem Mem M M M Legacy Softwae and Micopogamming IM bet company on 360 Instuction Set chitectue (IS): single instuction set fo many classes of machines (8-bit to 64-bit) Stewat Tucke stuck with job of what to do about softwae compatability If micopogamming could easily do same instuction set on many diffeent micoachitectues, then why couldn t multiple micopogams do multiple instuction sets on the same micoachitectue? oined tem emulation : instuction set intepete in micocode fo non-native instuction set Vey successful: in ealy yeas of IM 360 it was had to know whethe old instuction set o new instuction set was moe fequently used What about 1 bus? 1 adde? 1 Registe pot? Lec11.23 Lec11.24

7 Micopogamming Pos and ons Ease of design Flexibility Easy to adapt to changes in oganization, timing, technology an make changes late in design cycle, o even in the field an implement vey poweful instuction sets (just moe contol memoy) Geneality an implement multiple instuction sets on same machine. an tailo instuction set to application. ompatibility Many oganizations, same instuction set ostly to implement Slow Lec11.25 Exceptions use pogam Exception: nomal contol flow: sequential, jumps, banches, calls, etuns Exception = unpogammed contol tansfe system takes action to handle the exception - must ecod the addess of the offending instuction - ecod any othe infomation necessay to etun aftewads etuns contol to use must save & estoe use state llows constuction of a use vitual machine System Exception Handle etun fom exception Lec11.26 Two Types of Exceptions Inteupts caused by extenal events: - Netwok, Keyboad, Disk I/O, Time asynchonous to pogam execution - Most inteupts can be disabled fo bief peiods of time - Some (like Powe Failing ) ae non-maskable (NMI) may be handled between instuctions simply suspend and esume use pogam Taps MIPS convention: exception means any unexpected change in contol flow, without distinguishing intenal o extenal; use the tem inteupt only when the event is extenally caused. Type of event Fom whee? MIPS teminology I/O device equest Extenal Inteupt Invoke OS fom use pogam Intenal Exception ithmetic oveflow Intenal Exception Using an undefined instuction Intenal Exception Hadwae malfunctions Eithe Exception o Inteupt caused by intenal events - exceptional conditions (oveflow) - eos (paity) - faults (non-esident page) synchonous to pogam execution condition must be emedied by the handle 3/8/99 instuction may be etied o simulated and pogam continued o pogam may be aboted U Sping 1999 Lec11.27 Lec11.28

8 What happens to Instuction with Exception? MIPS achitectue defines the instuction as having no effect if the instuction causes an exception. When get to vitual memoy we will see that cetain classes of exceptions must pevent the instuction fom changing the machine state. This aspect of handling exceptions becomes complex and potentially limits pefomance => why it is had Lec11.29 Pecise Inteupts Pecise state of the machine is peseved as if pogam executed up to the offending instuction ll pevious instuctions completed Offending instuction and all following instuctions act as if they have not even stated Same system code will wok on diffeent implementations Position clealy established by IM Difficult in the pesence of pipelining, out-ot-ode execution,... MIPS takes this position Impecise system softwae has to figue out what is whee and put it all back togethe Pefomance goals often lead designes to fosake pecise inteupts system softwae developes, use, makets etc. usually wish they had not done this Moden techniques fo out-of-ode execution and banch pediction help implement pecise inteupts Lec11.30 ig Pictue: use / system modes y poviding two modes of execution (use/system) it is possible fo the compute to manage itself opeating system is a special pogam that uns in the pivileged mode and has access to all of the esouces of the compute pesents vitual esouces to each use that ae moe convenient that the physical esouces - files vs. disk sectos - vitual memoy vs physical memoy potects each use pogam fom othes potects system fom malicious uses. OS is assumed to know best, and is tusted code, so ente system mode on exception. Exceptions allow the system to taken action in esponse to events that occu while use pogam is executing: ddessing the Exception Handle Taditional ppoach: Inteupt Vecto P <- MEM[ IV_base + cause 00] 370, 68000, Vax, 80x86,... iv_base RIS Handle Table P < IT_base + cause 0000 saves state and jumps Spac, P, M88K,... MIPS ppoach: fixed enty P < EX_add ctually vey small table - RESET enty Might povide supplemental behavio (dealing with denomal floating-point numbes fo instance). - TL Unimplemented instuction used to emulate instuctions that - othe 3/8/99 wee not included in hadwae U Sping (I.e MicoVax) Lec11.31 iv_base cause handle code handle enty code cause Lec11.

9 Saving State Push it onto the stack Vax, 68k, 80x86 Save it in special egistes MIPS EP, advadd, Status, ause Shadow Registes M88k Save state in a shadow of the intenal pipeline egistes Lec11.33 dditions to MIPS IS to suppot Exceptions? Exception state is kept in copocesso 0. EP a -bit egiste used to hold the addess of the affected instuction (egiste 14 of copocesso 0). ause a egiste used to ecod the cause of the exception. In the MIPS achitectue this egiste is bits, though some bits ae cuently unused. ssume that bits 5 to 2 of this egiste encodes the two possible exception souces mentioned above: undefined instuction=0 and aithmetic oveflow=1 (egiste 13 of copocesso 0). advdd - egiste contained memoy addess at which memoy efeence occued (egiste 8 of copocesso 0) Status - inteupt mask and enable bits (egiste 12 of copocesso 0) ontol signals to wite EP, ause, advdd, and Status e able to wite exception addess into P, incease mux to add as input two ( hex ) May have to undo P = P + 4, since want EP to point to offending instuction (not its successo); P = P - 4 Lec11.34 Recap: Details of Status egiste Status Mask = 1 bit fo each of 5 hadwae and 3 softwae inteupt levels 1 => enables inteupts 0 => disables inteupts k = kenel/use 0 => was in the kenel when inteupt occued 1 => was unning use mode e = inteupt enable 0 => inteupts wee disabled 1 => inteupts wee enabled When inteupt occus, 6 LS shifted left 2 bits, setting 2 LS to 0 un in kenel mode with inteupts disabled Mask k e k e k e old pev cuent Lec11.35 Recap: Details of ause egiste Status Pending Pending inteupt 5 hadwae levels: bit set if inteupt occus but not yet seviced handles cases when moe than one inteupt occus at same time, o while ecods inteupt equests when inteupts disabled Exception ode encodes easons fo inteupt 0 (INT) => extenal inteupt 4 (DDRL) => addess eo exception (load o inst fetch) 5 (DDRS) => addess eo exception (stoe) 6 (IUS) => bus eo on instuction fetch 7 (DUS) => bus eo on data fetch 8 (Syscall) => Syscall exception 9 (KPT) => eakpoint exception 10 (RI) => Reseved Instuction exception 12 (OVF) => ithmetic oveflow exception 5 2 ode Lec11.36

10 How ontol Detects Exceptions in ou FSD Undefined Instuction detected when no next state is defined fom state 1 fo the op value. We handle this exception by defining the next state value fo all op values othe than lw, sw, 0 (R-type), jmp, beq, and oi as new state 12. Shown symbolically using othe to indicate that the op field does not match any of the opcodes that label acs out of state 1. ithmetic oveflow hapte 4 included logic in the LU to detect oveflow, and a signal called Oveflow is povided as an output fom the LU. This signal is used in the modified finite state machine to specify an additional possible next state Note: hallenge in designing contol of a eal machine is to handle diffeent inteactions between instuctions and othe exception-causing events such that contol logic emains small and fast. omplex inteactions makes the contol unit the most challenging aspect of hadwae design Lec11.37 How add Exceptions fo Oveflow and Unimplmented? R-type <= fun 0100 R[d] <= 0101 ORi <= op ZX 0110 R[t] <= 0111 IR <= MEM[P] P <= P <= P +SX 0001 LW <= + SX 1000 M <= MEM[] 1001 R[t] <= M 1010 instuction fetch decode SW <= + SX 1011 MEM[] <= 1100 EQ If = then P <= 0010 Execute Memoy Wite-back Lec11.38 Modification to the ontol Specification Pipelining is Natual! EP <= P - 4 P <= exp_add cause <= 12 (Ovf) R-type S <= fun 0100 oveflow R[d] <= S 0101 ORi S <= op ZX 0110 R[t] <= S 0111 IR <= MEM[P] P <= P S<= P +SX 0001 LW S <= + SX 1000 M <= MEM[S] 1001 R[t] <= M 1010 decode othe instuction fetch EQ SW S <= If - = S <= + SX then P <= S MEM[S] <= 1100 undefined instuction EP <= P - 4 P <= exp_add cause <= 10 (RI) Execute Memoy Wite-back Lec11.39 Laundy Example nn, ian, athy, Dave each have one load of clothes to wash, dy, and fold Washe takes 30 minutes Dye takes 40 minutes Folde takes 20 minutes D Lec11.40

11 T a s k O d e Sequential Laundy D 6 PM Midnight Time Sequential laundy takes 6 hous fo 4 loads If they leaned pipelining, how long would laundy take? Lec11.41 T a s k O d e Pipelined Laundy: Stat wok SP 6 PM Midnight Time D Pipelined laundy takes 3.5 hous fo 4 loads Lec11.42 T a s k O d e Pipelining Lessons D 6 PM Time Pipelining doesn t help latency of single task, it helps thoughput of entie wokload Pipeline ate limited by slowest pipeline stage Multiple tasks opeating simultaneously using diffeent esouces Potential speedup = Numbe pipe stages Unbalanced lengths of pipe stages educes speedup Time to fill pipeline and time to dain it educes speedup Stall fo Dependences Lec11.43 Pipelined Execution Time IFetch Dcd Exec Mem W Pogam Flow IFetch Dcd Exec Mem W IFetch Dcd Exec Mem W IFetch Dcd Exec Mem W Utilization? Now we just have to make it wok IFetch Dcd Exec Mem W IFetch Dcd Exec Mem W Lec11.44

12 Single ycle, Multiple ycle, vs. Pipeline ycle 1 ycle 2 lk Single ycle Implementation: Load Stoe Waste ycle 1 ycle 2 ycle 3 ycle 4 ycle 5 ycle 6 ycle 7 ycle 8 ycle 9 ycle 10 lk Multiple ycle Implementation: Load Stoe R-type Ifetch Reg Exec Mem W Ifetch Reg Exec Mem Ifetch Why Pipeline? Suppose we execute 100 instuctions Single ycle Machine 45 ns/cycle x 1 PI x 100 inst = 4500 ns Multicycle Machine 10 ns/cycle x 4.6 PI (due to inst mix) x 100 inst = 4600 ns Ideal pipelined machine 10 ns/cycle x (1 PI x 100 inst + 4 cycle dain) = 1040 ns Pipeline Implementation: Load Ifetch Reg Exec Mem W Stoe Ifetch Reg Exec Mem W R-type Ifetch Reg Exec Mem W Lec11.45 Lec11.46 Why Pipeline? ecause the esouces ae thee! an pipelining get us into touble? Time (clock cycles) Yes: Pipeline Hazads I n s t. O d e Inst 0 Inst 1 Inst 2 Inst 3 Inst 4 LU Im Reg Dm Reg LU Im Reg Dm Reg LU Im Reg Dm Reg LU Im Reg Dm Reg LU Im Reg Dm Reg stuctual hazads: attempt to use the same esouce two diffeent ways at the same time - E.g., combined washe/dye would be a stuctual hazad o folde busy doing something else (watching TV) data hazads: attempt to use item befoe it is eady - E.g., one sock of pai in dye and one in washe; can t fold until get sock fom washe though dye - instuction depends on esult of pio instuction still in the pipeline contol hazads: attempt to make a decision befoe condition is evaulated - E.g., washing football unifoms and need to get pope detegent level; need to see afte dye befoe next load in - banch instuctions an always esolve hazads by waiting Lec11.47 pipeline contol must detect the hazad 3/8/99 take action (o delay action) U Sping to esolve 1999 hazads Lec11.48

13 Summay 1/3 Specialize state-diagams easily captued by micosequence simple incement & banch fields datapath contol fields ontol design educes to Micopogamming Exceptions ae the had pat of contol Need to find convenient place to detect exceptions and to banch to state o micoinstuction that saves P and invokes the opeating system s we get pipelined PUs that suppot page faults on memoy accesses which means that the instuction cannot complete ND you must be able to estat the pogam at exactly the instuction with the exception, it gets even hade Summay 2/3 Micopogamming is a fundamental concept implement an instuction set by building a vey simple pocesso and intepeting the instuctions essential fo vey complex instuctions and when few egiste tansfes ae possible Pipelining is a fundamental concept multiple steps using distinct esouces Utilize capabilities of the Datapath by pipelined instuction pocessing stat next instuction while woking on the cuent one limited by length of longest stage (plus fill/flush) detect and esolve hazads Lec11.49 Lec11.50 Summay: Micopogamming one inspiation fo RIS If simple instuction could execute at vey high clock ate If you could even wite compiles to poduce micoinstuctions If most pogams use simple instuctions and addessing modes If micocode is kept in RM instead of ROM so as to fix bugs If same memoy used fo contol memoy could be used instead as cache fo macoinstuctions Then why not skip instuction intepetation by a micopogam and simply compile diectly into lowest language of machine? (micopogamming is ovekill when IS matches datapath 1-1) Lec11.51