ECE 361 Computer Architecture Lecture 11: Designing a Multiple Cycle Controller. Review of a Multiple Cycle Implementation
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1 ECE 6 Computer Architecture Lecture : Designing a Multiple Cycle ler 6 multicontroller. Review of a Multiple Cycle Implementation The root of the single cycle processor s problems: The cycle time has to be long enough for the slowest instruction Solution: Break the instruction into smaller steps Execute each step (instead of the entire instruction) in one cycle - Cycle time: time it takes to execute the longest step - Keep all the steps to have similar length This is the essence of the multiple cycle processor The advantages of the multiple cycle processor: Cycle time is much shorter Different instructions take different number of cycles to complete - Load takes five cycles - Jump only takes three cycles Allows a functional unit to be used more than once per instruction 6 multicontroller.
2 Review: Instruction Fetch Cycle, In the Beginning Every cycle begins right AFTER the clock tick: mem[] <:> + Clk You are here! One Logic Clock Cycle Wr=? Clk MemWr=? WrAdr Dout Din IRWr=? op=? 6 multicontroller. Clk Review: Instruction Fetch Cycle, The End Every cycle ends AT the next clock tick (storage element updates): IR <-- mem[] <:> <-- <:> + Clk One Logic Clock Cycle Wr= You are here! Clk MemWr= IRWr= WrAdr Din Dout Op = Add Clk 6 multicontroller.
3 Putting it all together: Multiple Cycle Datapath Wr WrCond Src BrWr IorD MemWr IRWr RegDst RegWr SelA Target WrAdr Din Dout Rs Rt Rt Rd Ra Rb busa Reg File Rw busw busb << Imm 6 ExtOp Extend MemtoReg SelB Op 6 multicontroller. Wr= Instruction Fetch Cycle: Overall Picture WrAdr Din Dout Ifetch Op=Add : Wr, IRWr x: WrCond RegDst, MemR Others: s WrCond=x Src= BrWr= IorD= MemWr= IRWr= SelA= Target busa busb SelB= Op=Add 6 multicontroller.6
4 Register Fetch / Instruction Decode (Continue) busa <- Reg[rs] ; busb <- Reg[rt] ; Target <- + SignExt(Imm6)* Wr= IorD=x Beq Rtype Ori 6 multicontroller.7 WrCond= : MemWr= WrAdr Din Dout IRWr= Op 6 Func 6 RegDst=x Rs Rt Rt Rd Imm 6 ExtOp= Extend Op=Add : BrWr, ExtOp SelB= x: RegDst, Src IorD, MemtoReg Others: s RegWr= Ra Rfetch/Decode Rb busa Reg File Rw busw busb << Src=x SelA= SelB= BrWr= Target Op=Add R-type Execution Output <- busa op busb RExec : RegDst SelA SelB= Op=Rtype x: Src, IorD Wr= WrCond= MemtoReg ExtOp Src=x BrWr= IorD=x MemWr= IRWr= RegDst= RegWr= SelA= Target Rs Ra Rt Rb busa Reg File Rt WrAdr Rw Din Dout Rd busw busb << Imm Extend 6 ExtOp=x MemtoReg=x Op=Rtype SelB= 6 multicontroller.8
5 R-type Completion Rfinish Op=Rtype R[rd] <- Output : RegDst, RegWr sela SelB= Wr= WrCond= x: IorD, Src ExtOp Src=x BrWr= IorD=x MemWr= IRWr= RegDst= RegWr= SelA= Target Rs Ra Rt Rb busa Reg File Rt WrAdr Rw Din Dout Rd busw busb << Imm Extend 6 ExtOp=x MemtoReg= Op=Rtype SelB= 6 multicontroller.9 Outline of Today s Lecture Recap Review of FSM control From Finite State Diagrams to Microprogramming 6 multicontroller.
6 Overview may be designed using one of several initial representations. The choice of sequence control, and how logic is represented, can then be determined independently; the control can then be implemented with one of several methods using a structured logic technique. Initial Representation Finite State Diagram Microprogram Sequencing Explicit Next State Microprogram counter Function + Dispatch ROMs Logic Representation Logic Equations Truth Tables Implementation Technique PLA ROM hardwired control microprogrammed control 6 multicontroller. Initial Representation: Finite State Diagram Ifetch Rfetch/Decode 8 : ExtOp LWmem SelA, IorD SelB= Op=Add x: MemtoReg Src Op=Add : Wr, IRWr x: WrCond AdrCal RegDst, MemR : ExtOp SelA Others: s SelB= Op=Add lw or sw x: MemtoReg Src lw sw LWwr : SelA RegWr, ExtOp MemtoReg SelB= Op=Add x: Src IorD SWMem : ExtOp MemWr SelA SelB= Op=Add x: Src,RegDst MemtoReg 6 7 Op=Add : BrWr, ExtOp SelB= x: RegDst, Src IorD, MemtoReg Others: s Rtype Ori RExec : RegDst SelA SelB= Op=Rtype x: Src, IorD MemtoReg ExtOp beq Rfinish Op=Rtype : RegDst, RegWr sela SelB= x: IorD, Src ExtOp BrComplete Op=Sub SelB= x: IorD, MemReg RegDst, ExtOp : WrCond SelA Src OriExec Op=Or : SelA SelB= x: MemtoReg IorD, Src Op=Or OriFinish x: IorD, Src SelB= : SelA RegWr 6 multicontroller. 6
7 Sequencing : Explicit Next State Function Logic Inputs O u t p u t s Multicycle Datapath Opcode State Reg Next state number is encoded just like datapath controls 6 multicontroller. Logic Representative: Logic Equations Next state from current state State -> State State -> S, S6, S8, S State -> State -> State ->State State -> State State 6 -> State 7 State 7 -> State State 8 -> State State 9-> State State -> State State -> State Alternatively, prior state & condition S, S, S7, S8, S9, S -> State -> State -> State -> State -> State State & op = sw -> State -> State 6 State 6 -> State 7 -> State 8 State & op = jmp -> State 9 -> State State -> State 6 multicontroller. 7
8 Implementation Technique: Programmed Logic Arrays Each output line the logical OR of logical AND of input lines or their complement: AND minterms specified in top AND plane, OR sums specified in bottom OR plane Op Op Op Op Op Op S S S S = 6 = = 7 = = 8 = = 9 = = = = = 6 multicontroller. R = beq = lw = sw = ori = jmp = NS NS NS NS Implementation Technique: Programmed Logic Arrays Each output line the logical OR of logical AND of input lines or their complement: AND minterms specified in top AND plane, OR sums specified in bottom OR plane Op Op Op Op Op Op S S S S = 6 = = 7 = = 8 = = 9 = = = = = 6 multicontroller.6 lw = sw = R = ori = beq = jmp = NS NS NS NS 8
9 Multicycle Given numbers of FSM, can turn determine next state as function of inputs, including current state Turn these into Boolean equations for each bit of the next state lines Can implement easily using PLA What if many more states, many more conditions? What if need to add a state? 6 multicontroller.7 Next Iteration: Using Sequencer for Next State Before Explicit Next State: Next try variation step from right hand side Few sequential states in small FSM: suppose added floating point? Still need to go to non-sequential states: e.g., state =>, 6, 8, Initial Representation Finite State Diagram Microprogram Sequencing Explicit Next State Microprogram counter Function + Dispatch ROMs Logic Representation Logic Equations Truth Tables Implementation Technique PLA ROM hardwired control microprogrammed control 6 multicontroller.8 9
10 Sequencer-based control unit Logic Outputs Multicycle Datapath Adder Inputs State Reg Address Select Logic Types of branching Set state to Dispatch (state & ) Use incremented state number 6 multicontroller.9 Opcode Sequencer-based control unit details Adder Address Select Logic Logic Inputs State Reg ROM Opcode ROM Dispatch ROM Op Name State Rtype jmp beq ori lw sw Dispatch ROM Op Name State lw sw 6 multicontroller.
11 Implementing with a ROM Instead of a PLA, use a ROM with one word per state ( word ) State number Word Bits 8- Word Bits multicontroller. Next Iteration: Using Microprogram for Representation Initial Representation Finite State Diagram Microprogram Sequencing Explicit Next State Microprogram counter Function + Dispatch ROMs Logic Representation Logic Equations Truth Tables Implementation Technique PLA ROM hardwired control microprogrammed control ROM can be thought of as a sequence of control words word can be thought of as instruction: microinstruction Rather than program in binary, use assembly language 6 multicontroller.
12 Microprogramming is the hard part of processor design Datapath is fairly regular and well-organized is highly regular is irregular and global Microprogramming: -- A Particular Strategy for Implementing the Unit of a processor by "programming" at the level of register transfer operations Microarchitecture: -- Logical structure and functional capabilities of the hardware as seen by the microprogrammer 6 multicontroller. Macroinstruction Interpretation Main execution unit ADD SUB AND... DATA User program plus Data this can change! one of these is mapped into one of these CPU control memory AND microsequence e.g., Fetch Calc Operand Addr Fetch Operand(s) Calculate Save Answer(s) 6 multicontroller.
13 Microprogramming Pros and Cons Ease of design Flexibility Easy to adapt to changes in organization, timing, technology Can make changes late in design cycle, or even in the field Can implement very powerful instruction sets (just more control memory) Generality Can implement multiple instruction sets on same machine. Can tailor instruction set to application. Compatibility Many organizations, same instruction set Costly to implement Slow 6 multicontroller. Summary: Multicycle Microprogramming and hardwired control have many similarities, perhaps biggest difference is initial representation and ease of change of implementation, with ROM generally being easier than PLA Initial Representation Finite State Diagram Microprogram Sequencing Explicit Next State Microprogram counter Function + Dispatch ROMs Logic Representation Logic Equations Truth Tables Implementation Technique PLA ROM hardwired control microprogrammed control 6 multicontroller.6
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