The Big Picture: Where are We Now? CS 152 Computer Architecture and Engineering Lecture 11. The Five Classic Components of a Computer

Transcription

1 The Big Picture: Where are We Now? S 5 omputer Architecture and ngineering Lecture Multicycle ontroller esign (ontinued) The Five lassic omponents of a omputer Processor Input ontrol atapath Output Today s Topics: Microprogramed control Administrivia Microprogram it yourself xceptions Lec. Lec. ontroller esign The state digrams that arise define the controller for an instruction set processor are highly structured Use this structure to construct a simple microsequencer ontrol reduces to programming this very simple device microprogramming sequencer control microinstruction datapath control Multicycle atapath np_sel Next P P Instruction IR Reg Operand A B qual xtop Src ctr xt S MemRd MemWr Mem Access M ata Mem MemToReg Regst RegWr Reg. Result Store micro-p sequencer Lec.3 Lec.4

2 State iagram of ontroller Using a Jump ounter R-type ORi S <= A fun B S <= A or ZX R[rd] <= S R[rt] <= S IR <= MM[P] A <= R[rs] B <= R[rt] M <= MM[S] decode BQ MM[S] <= B P <= Next(P) Lec.5 xecute Write-back R-type R[rd] <= S load ORi IR <= MM[P] inc A <= R[rs] B <= R[rt] S <= A fun B S <= A or ZX inc inc inc inc M <= MM[S] inc R[rt] <= S decode BQ MM[S] <= B P <= Next(P) Lec.6 xecute Write-back xample: Jump-ounter i i+ i Sequencer Sequencer-based control unit alled microp or µp vs. state register ontrol Value ffect Next µaddress = Next µaddress = dispatch ROM Next µaddress = µaddress + Microprogram op-code Map ROM ounter inc load None of above: o nothing (for wait states) ispatch ROM: Opcode ispatch State R-type BQ ori Adder µaddress Select Logic microp ispatch ROM Opcode Lec.7 Lec.8

3 Microprogramming (Maurice Wilkes) Macro and micro - instruction Interpretation ontrol is the hard part of processor design atapath is fairly regular and well-organized is highly regular ontrol is irregular and global Microprogramming: -- A Particular Strategy for Implementing the ontrol Unit of a processor by "programming" at the level of register transfer operations Main execution unit A SUB AN... ATA User program plus ata this can change! one of these is mapped into one of these Microarchitecture: -- Logical structure and functional capabilities of the hardware as seen by themicroprogrammer Historical Note: IBM 36 Series first to distinguish between architecture & organization Same instruction set across wide range of implementations, each with different cost/performance Lec.9 PU control memory AN microsequence e.g., alc Operand Addr Operand(s) alculate Save Answer(s) Lec. Variations on Microprogramming Horizontal Microcode control field for each control point in the machine µseq µaddr A-mux B-mux bus enables register enables Vertical Microcode compact microinstruction format for each class of microoperation local decode to generate all control points (remember?) branch: µseq-op µadd execute: -op A,B,R memory: mem-op S, Vertical Horizontal Lec. xtreme Horizontal... bit for each loadable register enbmar enba... 3 N3 N N N Incr P control epending on bus organization, many potential control combinations simply wrong, i.e., implies transfers that can never hap pen at the same time. Makes sense to encode fields to save ROM space input select xample: mem_to_reg and _to_reg should never happen simultaneously; => encode in single bit which is decoded rather than two separate bits NOT: the encoding should be only wide enough so that parallel actionsthat the datapath supports should still be specifiable in a single microinstruction Lec.

4 More Vertical Format Hybrid ontrol src dst other control fields next states inputs MUX Not all critical control information is derived from control logic.g., Instruction Register (IR) contains useful control information, such as register sources, destinations, opcodes, etc. Multiformat Microcode: 3 6 cond next address Branch Jump enable signals from control R S R S R Register dst src alu Register Xfer Operation Lec.3 IR to control op rs rs rd Lec.4 Summary: Horizontal vs. Vertical Microprogramming Microprogramming a multicycle processor NOT: previous organization is not TRU horizontal microprogramming; register decoders give flavor of encoded microoperations Most microprogramming-based controllers vary between: horizontal organization ( control bit per control point) vertical organization (fields encoded in the control memory and must be decoded to control something) Horizontal Vertical ) hoose datapath and sequencer architecture ) Assign states and sequence of each (multicycle) instruction (i.e. define the controller FSM) ) hoose microinstruction format (minimum bits to describe all allowable functions of sequencer and datapath) 3) Map instructions into microinstruction sequences + more control over the potential parallelism of operations in the datapath - uses up lots of control store + easier to program, not very different from programming a RIS machine in assembly language - extra level of decoding may slow the machine down Lec.5 Lec.6

5 Sequencer Sequencer-based control unit alled microp or µp vs. state register ontrol Value ffect Next µaddress = Next µaddress = dispatch ROM Next µaddress = µaddress + ispatch ROM: Opcode ispatch State R-type BQ ori Adder µaddress Select Logic Microprogram microp ispatch ROM Opcode Lec.7 atapath single memory, single regfile Miminizes Hardware: memory, adder PWr P Ior PWrond Zero MemWr RAdr Ideal WrAdr in out IRWr Instruction Reg Rs Rt Memata Reg Regst Rt Imm Rd xtop xtend RegWr Ra Rb busa A Reg Rw B buswbusb << MemtoReg SelA 4 PSrc 3 Zero ontrol Op SelB Lec.8 Out Finite State Machine (FSM) Spec Finite State Machine (FSM) Spec (improved) IR <= MM[P] IR <= MM[P] R-type ORi <= A fun B <= A or ZX <= A + SX decode <= A + SX BQ Q: What can we do in state? <= P +SX xecute R-type ORi <= A fun B <= A or ZX <= P +SX <= A + SX decode <= A + SX BQ If A = B then P <= xecute R[rd] <= R[rt] <= M <= MM[] MM[] <= B If A = B then P <= Lec.9 Write-back R[rd] <= R[rt] <= M <= MM[] MM[] <= B Lec. Write-back

6 esigning a Microinstruction Set ) Start with list of control signals ) Group signals together that make sense (vs. random): called fields 3) Place fields in some logical order (e.g., operation & operands first and microinstruction sequencing last) 4) reate a symbolic legend for the microinstruction format, showing name of field values and how they set the control signals 5) To minimize the width, encode operations that will never be used at the same time Lec. Single Bit ontrol Multiple Bit ontrol ) Start with list of control signals Signal name ffect when deasserted ffect when asserted SelA st operand = P st operand =Reg [rs] RegWr None Reg. is written MemtoReg Reg. write data input = Reg. write data input = memory Regst Reg. dest. no. = rt Reg. dest. no. = rd MemRd None at address is read, MemWr None at address is written Ior address = P address = S IRWr None IR <= PWr None P <= PSource PWrond None IF then P <= PSource PSrc PSource = PSource = xtop Zero xtended Sign xtended Signal name Value ffect Op adds subtracts does function code does logical OR SelB nd input = 4 nd input = Reg [rt] nd input = extended,shift left nd input = extended Lec. ) Group into fields of unrelated signals Miminizes Hardware: memory, adder PWr P Ior PWrond Zero MemWr RAdr Ideal WrAdr in out MemRd IRWr Instruction Reg Rs Rt Memata Reg SR Regst Rt Imm Rd xtop xtend RegWr Ra Rb busa A Reg Rw B buswbusb << MemtoReg SR SelA 4 PSrc 3 PWrite Zero ontrol Op SelB Lec.3 Out,3 & 4 ) Group into fields, order and assign names SR SR est Mem Memreg Pwrite Seq Field Name Values for Field Function of Field with Specific Value Add adds Subt. subtracts Func Or does function code does logical OR SR P st input <= P rs st input <= Reg [rs] SR 4 nd input <= 4 xtend xtend nd input <= sign ext. IR[5-] nd input <= ext. IR[5-] xtshft rt nd input <= sign ex., sl IR[5-] nd input <= Reg [rt] dest(ination) rd Reg[rd] <= rt Reg[rt] <= rt Mem Reg[rt] <= Mem Mem(ory) Read P Read Read memory using P Read memory using for addr Write Write memory using for addr Memreg IR IR <= Mem Pwrite Pwr P <= PSource PSrc IF Zero then PSource <= else PWrond IF Zero then P <= PSource Seq(uencing) Seq Go to sequential µinstruction Go to the first microinstructionlec.4 ispatch ispatch using ROM.

7 5) ncode each field Field Name Width ontrol Signals Set wide narrow 4 Op SR SelA SR 5 3 SelB, xtop est 3 RegWrite, MemtoReg, Regst Mem 3 MemRd, MemWre, Ior Memreg IRWrite PWrite 3 PWr, PSrc, PWrond Seq 3 Addrtl Total width 4 4 bits 5) ncode each field (cont.) est: ode Name RegWrite MemToReg Regest --- X X rd rt rt MM SR: ode Name SelB xtop --- X X 4 X rt X xtshft xtend xtend Lec.5 Lec.6 Finally o the microprogram. Label SR SR est. MemReg. PWrite Seq : Add P 4 Read P IR Pwr Seq Add P xtshft ispatch Rtype:Func rs rt Seq rd Ori: Or rs xtend Seq rt Lw: Add rs xtend Seq Read Seq rt MM Sw: Add rs xtend Seq Write Beq: Subt. rs rt PWrond. Lec.7 Microprogramming Pros and ons ase of design Flexibility asy to adapt to changes in organization, timing, technology an make changes late in design cycle, or even in the field an implement very powerful instruction sets (just more control memory) Generality an implement multiple instruction sets on same machine. an tailor instruction set to application. ompatibility Many organizations, same instruction set ostly to implement Slow Lec.8

8 Adding a more complex memory model ontroller handles non-ideal memory IR <= MM[P] P addr Instruction data Inst.Reg InstMem_rd IM_wait IR_en R-type S <= A fun B ORi S <= A or ZX ~IMwait A <= R[rs] B <= R[rt] IMwait decode / operand fetch BQ P <= Next(P) xecute Add a wait flag of indeterminate length IM_wait (due to caching) Lec.9 R[rd] <= S R[rt] <= S M <= MM[S] ~wait MM[S] <= B wait ~wait wait Lec.3 Write-back Really Simple Time-State ontrol Time-state ontrol Path instruction fetch xecute write-back decode R-type S <= A fun B R[rd] <= S ORi S <= A or ZX R[rt] <= S IR <= MM[P] ~IMwait A <= R[rs] B <= R[rt] M <= MM[S] wait IMwait MM[S] <= B BQ wait P <= Next(P) Local decode and control at each stage Next P P Inst. Mem IR Valid cdtrl Reg IRex A B x trl xec IRmem S Mem Access Mem trl M IRwb ata Mem WB trl Reg. qual Lec.3 Lec.

9 Overview of ontrol ontrol may be designed using one of several initial representations. The choice of sequence control, and how logic is represented, can then be determined independently; the control can then be implemented with one of several methods using a structured logic technique. Initial Representation Finite State iagram Microprogram Sequencing ontrol xplicit Next State Microprogram counter Function + ispatch ROMs Logic Representation Logic quations Truth Tables Implementation PLA ROM Technique hardwired control microprogrammedcontrol Lec.33 Summary Specialize state-diagrams easily captured by microsequencer simple increment & branch fields datapath control fields Most microprogramming-based controllers vary between: horizontal organization ( control bit per control point) vertical organization (fields encoded in the control memory and must be decoded to control something) Steps: identify control signals, group them, develop mini language, then microprogram ontrol design reduces to Microprogramming Arbitrarily complicated instructions possible Lec.34 Summary: Microprogramming one inspiration for RIS If simple instruction could execute at very high clock rate If you could even write compilers to produce microinstructions If most programs use simple instructions and addressing modes If microcode is kept in RAM instead of ROM so as to fix bugs If same memory used for control memory could be used instead as cache for macroinstructions Then why not skip instruction interpretation by a microprogram and simply compile directly into lowest language of machine? Lec.35