Reference Architecture Proposals and Channel Data

Transcription

1 Reference Architecture Proposals and Channel Data Richard Mellitz, Samtec Howard Heck. Intel Contribution Acknowledgment: Oluwafemi Akinwale and Subas Bastola, Intel IEEE802.3 Plenary July 2018, San Diego, Ca IEEE Gb/s, 200 Gb/s, and 400 Gb/s Electrical Interfaces Task Force 1

2 Outline 4 COM architectures Data for each architecture vs a collection of channels Next steps IEEE Gb/s, 200 Gb/s, and 400 Gb/s Electrical Interfaces Task Force 2

3 4 Signal Architecture Approaches 1. Zero Forced DFE 2. Quantized Forced DFE 3. One DFE tap and a number of (Rx)FFE taps 4. One DFE tap and a number of (Rx)FFE taps with gain at cursor IEEE Gb/s, 200 Gb/s, and 400 Gb/s Electrical Interfaces Task Force 3

4 COM is based on the pulse response (Annex 93A) Thru (ISI) channel response is h (0) (t) i.e. the pulse response The following uses pulse response plots to describe COM equalization IEEE Gb/s, 200 Gb/s, and 400 Gb/s Electrical Interfaces Task Force 4

5 Zero Forced (ZF) DFE All legal Tx FFE and CTF (continuous time function) settings are considered Called a full grid search Caveat: Very often CTF settings dominate over the Tx FFE post cursor. Exception: Samples corresponding to DFE cursor of is h (0) (t) greater than certain values (b max ) are converted in to ISI noise Example where 1 st DFE tap reach limit creating ISI noise Pulse response IEEE Gb/s, 200 Gb/s, and 400 Gb/s Electrical Interfaces Task Force 5

6 Quantized DFE Same as Zero force except: Samples corresponding to a DFE cursor h (0) (t n ) greater than the DFE quantization step size are also converted into ISI noise Pulse response IEEE Gb/s, 200 Gb/s, and 400 Gb/s Electrical Interfaces Task Force 6

7 One DFE tap + (Rx)FFE Same full grid as for zero forced DFE except 1 tap of DFE w/ an Rx FFE of a specified number and resolution of pre-cursors and post-cursors are determined from a vector forced optimization. The cursor for the vector forcing is h (0) (t s ) where t s is the sample point and The first post cursor is set the maximum allowed setting (b max ) C=((HH'*HH)^-1*HH')'*FV ; C are the Rx FFE taps HH is derived from h (0) (t) FV is the forcing vector, FV = [... 0, 0, As, bmax(1)*as, 0, 0, 0, 0...] FOM is computed from each CTF and Tx FFE setting with h fferx (f) is computed from the C found as in eq 93A-32 FFE(3,32) used here for now 3 precursors and 32 post cursors IEEE Gb/s, 200 Gb/s, and 400 Gb/s Electrical Interfaces Task Force 7

8 One DFE tap + (Rx) FFE w/ Cursor Gain Same as one DFE tap and a number of Rx FFE taps (pre and post cursor) except: The cursor for the vector forcing (h (0) (t s ) where t s is the sample point) has some gain C=((HH'*HH)^-1*HH')'*FV ; C are the Rx FFE taps HH is derived from h (0) (t) FV is the forcing vector, FV = [... 0, 0, As*10 gain 20, b max (1)*As, 0, 0, 0, 0...] 3 db gain seems to work best IEEE Gb/s, 200 Gb/s, and 400 Gb/s Electrical Interfaces Task Force 8

9 Table 93A-1 parameters I/O control Table 93A 3 parameters Parameter Setting Units Information DIAGNOSTICS 1 logical Parameter Setting Units f_b GBd DISPLAY_WINDOW 1 logical package_tl_gamma0_a1_a2 [ e e-4] f_min 0.05 GHz CSV_REPORT 1 logical package_tl_tau 6.141E-03 ns/mm Delta_f 0.01 GHz RESULT_DIR.\results\100G_Study_Grou p_{date}\ package_z_c 90 Ohm (tdr sel) C_d [1.3e-4 1.3e-4] nf [TX RX] SAVE_FIGURES 0 logical z_p select [ 2 ] [test cases to run] Port Order [ ] Table parameters z_p (TX) [12 30] mm [test cases] RUNTAG KR_Study_Group Parameter Setting z_p (NEXT) [12 30] mm [test cases] Receiver testing board_tl_gamma0_a1_a2 [ e e-4] z_p (FEXT) [12 30] mm [test cases] RX_CALIBRATION 0 logical board_tl_tau 6.191E-03 ns/mm z_p (RX) [12 30] mm [test cases] Sigma BBN step 5.00E-03 V board_z_c 110 Ohm C_p [1.1e-4 1.1e-4] nf [TX RX] IDEAL_TX_TERM 0 logical z_bp (TX) 151 mm R_0 50 Ohm T_r 6.16E-03 ns z_bp (NEXT) 72 mm R_d [ 50 50] Ohm [TX RX] or selected FORCE_TR 1 logical z_bp (FEXT) 72 mm f_r 0.75 *fb z_bp (RX) 151 mm c(0) 0.6 min Non standard control options c(-1) [-0.28:0.025:0] [min:step:max] COM_CONTRIBUTION 0 logical c(-2) [0:0.05:0.1] [min:step:max] TDR 1 logical c(-3) [-0.1:0.025:0] [min:step:max] ERL 1 logical c(-4) 0 [min:step:max] ERL_ONLY 0 logical c(1) [-0.05:.025:0] [min:step:max] TR_TDR ns g_dc [-20:1:10] db [min:step:max] N 1000 f_z GHz TDR_Butterworth 1 logical f_p GHz beta_x 1.70E+09 f_p GHz rho_x 0.18 A_v 0.41 V tdr selected fixture delay time 0 A_fe 0.41 V tdr selected Rx FFE A_ne 0.6 V tdr selected ffe_pre_tap_len 0 UI L 4 ffe_post_tap_len 0 UI M 32 ffe_tap_step_size 0.01 N_b 32 UI ffe_main_cursor_min 0.7 N_b_step 0 normailized ffe_pre_tap1_max 0.3 b_max(1) 0.7 ffe_post_tap1_max 0.3 b_max(2..n_b) 0.2 ffe_tapn_max 0.1 sigma_rj 0.01 UI A_DD 0.02 UI eta_0 8.20E-09 V^2/GHz SNR_TX 32.5 db tdr selected R_LM 0.95 DER_0 1.00E-04 Operational control COM Pass threshold 3 db Include PCB 0 Value 0, 1, 2 g_dc_hp [-6:1:0] [min:step:max] f_hp_pz GHz COM config sheet for ZF or Q DFE Set to zero N_b 32 UI N_b_step normailized Q DFE For reference IEEE Gb/s, 200 Gb/s, and 400 Gb/s Electrical Interfaces Task Force 9

10 Table 93A-1 parameters I/O control Table 93A 3 parameters Parameter Setting Units Information DIAGNOSTICS 1 logical Parameter Setting Units f_b GBd DISPLAY_WINDOW 1 logical package_tl_gamma0_a1_a2 [ e e-4] f_min 0.05 GHz CSV_REPORT 1 logical package_tl_tau 6.141E-03 ns/mm Delta_f 0.01 GHz RESULT_DIR.\results\100G_Study_Group _{date}\ package_z_c 90 Ohm (tdr sel) C_d [1.3e-4 1.3e-4] nf [TX RX] SAVE_FIGURES 0 logical z_p select [ 2 ] [test cases to run] Port Order [ ] Table parameters z_p (TX) [12 30] mm [test cases] RUNTAG CK_100GEL Parameter Setting z_p (NEXT) [12 30] mm [test cases] Receiver testing board_tl_gamma0_a1_a2 [ e e-4] z_p (FEXT) [12 30] mm [test cases] RX_CALIBRATION 0 logical board_tl_tau 6.191E-03 ns/mm z_p (RX) [12 30] mm [test cases] Sigma BBN step 5.00E-03 V board_z_c 110 Ohm C_p [1.1e-4 1.1e-4] nf [TX RX] IDEAL_TX_TERM 0 logical z_bp (TX) 151 mm R_0 50 Ohm T_r 6.16E-03 ns z_bp (NEXT) 72 mm R_d [ 50 50] Ohm [TX RX] or selected FORCE_TR 1 logical z_bp (FEXT) 72 mm f_r 0.75 *fb z_bp (RX) 151 mm c(0) 0.6 min Non standard control options c(-1) [-0.28:0.025:0] [min:step:max] COM_CONTRIBUTION 0 logical c(-2) [0:0.05:0.1] [min:step:max] TDR 1 logical c(-3) 0 [min:step:max] ERL 1 logical c(-4) 0 [min:step:max] ERL_ONLY 0 logical c(1) [-0.05:.025:0] [min:step:max] TR_TDR ns g_dc [-20:1:10] db [min:step:max] N 1000 f_z GHz TDR_Butterworth 1 logical f_p GHz beta_x 1.70E+09 f_p GHz rho_x 0.18 A_v 0.41 V tdr selected fixture delay time 0 A_fe 0.41 V tdr selected A_ne 0.6 V tdr selected Rx FFE L 4 ffe_pre_tap_len 3 UI M 32 ffe_post_tap_len 32 UI N_b 1 UI ffe_tap_step_size 0.01 b_max(1) 0.7 ffe_main_cursor_min 0.7 b_max(2..n_b) 0.2 ffe_pre_tap1_max 0.3 sigma_rj 0.01 UI ffe_post_tap1_max 0.3 A_DD 0.02 UI ffe_tapn_max 0.1 eta_0 8.20E-09 V^2/GHz crusor_gain 0:1:4 db SNR_TX 32.5 db tdr selected R_LM 0.95 DER_0 1.00E-04 Operational control COM Pass threshold 3 db Include PCB 0 Value 0, 1, 2 g_dc_hp [-6:1:0] [min:step:max] f_hp_pz GHz Set to zero for no gain COM config sheet for FFE and w/wo gain For reference IEEE Gb/s, 200 Gb/s, and 400 Gb/s Electrical Interfaces Task Force 10

11 Reference: ZF DFE Channels: Cabled backplane (2) Cabled fabric switch (12) Used channels with COM 2.3dB Analysis used 32 taps total (DFE+FFE or DFE-only) Is the ZF DFE too optimistic Does the implication of the ZF DFE require too much power IEEE Gb/s, 200 Gb/s, and 400 Gb/s Electrical Interfaces Task Force 11

12 Data Summary Quantized DFE seems like just derating COM of the ZF DFE FFE with gain seems to get closer to ZF DFE for high loss IEEE Gb/s, 200 Gb/s, and 400 Gb/s Electrical Interfaces Task Force 12

13 COM Correlations to DFE-based COM Stat Uncertainty More variability for the FFE based COM X and Y axis are db of COM IEEE Gb/s, 200 Gb/s, and 400 Gb/s Electrical Interfaces Task Force 13

14 Summary & Next Steps Reference EQ architecture choices impact on COM results More variability in results with DFE+FFE-based reference EQ Is a quantized DFE good enough? It seems like it is the same as raising the COM threshold Follow-on work Assess the sensitivity to # of taps in the Rx Equalizer Look at algorithm to better optimize gain in FFE; goal being to reduce uncertainty in results Follow-work for channels: Address PCB manufacturing to further reduce the channel ISI. IEEE Gb/s, 200 Gb/s, and 400 Gb/s Electrical Interfaces Task Force 14

15 Backup IEEE Gb/s, 200 Gb/s, and 400 Gb/s Electrical Interfaces Task Force 15

16 COM vs Channel IL ZF DFE Quantized ZF DFE DFE+FFE DFE+FFE w/ Gain IEEE Gb/s, 200 Gb/s, and 400 Gb/s Electrical Interfaces Task Force 16

17 Consolidated Data IEEE Gb/s, 200 Gb/s, and 400 Gb/s Electrical Interfaces Task Force 17

18 Consolidated Data #2 IEEE Gb/s, 200 Gb/s, and 400 Gb/s Electrical Interfaces Task Force 18

19 Quantized DFE Delta calculated relative to ZF-DFE. IEEE Gb/s, 200 Gb/s, and 400 Gb/s Electrical Interfaces Task Force 19

20 DFE + FFE IEEE Gb/s, 200 Gb/s, and 400 Gb/s Electrical Interfaces Task Force 20

21 DFE + FFE w/ 3dB Cursor Gain IEEE Gb/s, 200 Gb/s, and 400 Gb/s Electrical Interfaces Task Force 21

22 Correlation to COM with DFE DFE Quantized DFE FFE w/ gain IEEE Gb/s, 200 Gb/s, and 400 Gb/s Electrical Interfaces Task Force 22