NONVOLATILE MEMORY TECHNOLOGIES WITH EMPHASIS ON FLASH

Transcription

1 NONVOLATILE MEMORY TECHNOLOGIES WITH EMPHASIS ON FLASH A Comprehensive Guide to Understanding and Using NVM Devices Edited by Joe E. Brewer Manzur Gill IEEE Press Series on Microelectronic Systems Stuart K. Tewksbury and Joe E. Brewer, Series Editors IEEE Components, Packaging, and Manufacturing Technology Society, Sponsor IEEE Electron Devices Society, Sponsor 4HEEE IEEE PRESS В 1С ENTEN N 1 A L I807 j WILEY j 2007! BICENTENNIAL > WILEY-INTEI ^SCIENCE A JOHN WILEY & SONS, INC., PUBI.ICATION

2 Foreword Preface Contributors xvii xxi xxiü 1 INTRODUCTION TO NONVOLATILE MEMORY 1 Joe E. Brewer 1.1 Introduction Elementary Memory Concepts Unique Aspects of Nonvolatile Memory Storage Storage Mechanisms Retention Endurance Flash Memory and Flash Cell Variations Semiconductor Device Technology Generations 16 References 18 2 FLASH MEMORY APPLICATIONS 19 Gary Forni, Collin Ong, Christine Rice, Ken McKee, and Ronald J. Bauer 2.1 Introduction Spectrum of Memory Devices Evolving from EPROMs NOR and NAND Evolution of Flash Usage Models Understanding Flash Attributes Code Storage Execute-in-Place Store and Download Contrasting Execute-in-Place Versus Store and Download Future Code Storage Applications Data Storage Why Use Flash to Store Data? 46

3 2.3.2 Architectural Decisions Embedded Flash Storage Removable Media Code+Data Storage Relevant Attributes for Code+Data Fitting the Pieces Together for Code+Data Benefits of Code+Data Conclusion 62 3 MEMORY CIRCUIT TECHNOLOGIES 63 Giulio G. Marotta, Giovanni Naso, and Giuseppe Savarese 3.1 Introduction Flash Cell Basic Operation Cell Programming Cell Erase Compaction Read Flash Memory Architecture Memory Cell Array Analog Blocks Control Logic Redundancy Detectivity and Process Variations Yield Improvement Yield Simulator Redundancy Fuses Design Row Redundancy Design Column Redundancy Design Advanced Redundancy Design Error Correction Coding (ECC) On-Chip ECC and Endurance/Retention in Flash Memories On-Chip ECC and Multilevel Flash Memories Design for Testability (DFT) Test Entry and Organization Fuse Cell Sense Amplifier Reference Trimming and Monitor High Voltages Trimming Timings Trimming and External Control Internal State Machine Algorithm Skips and Monitor Address Path Configuration Data Path Configuration and Trimming 99

4 3.6.9 High Voltages External Forcing and Monitor Array Direct Access and Stresses Internal Pattern Write and Verify Data Compression Flash-Specific Circuit Techniques Voltage Level Shifting Sensing Voltage Multiplication Reference Voltage Generation Voltage Regulation I/O Signal Buffering 122 References 123 PHYSICS OF FLASH MEMORIES 129 /. Van Houdt, R. Degraeve, G. Groeseneken, and H. E. Maes 4.1 Introduction Basic Operating Principles and Memory Characteristics Floating-Gate Principle Basic Definitions with Examples Basic Equations and Models Physics of Programming and Erase Mechanisms Fowler-Nordheim Tunneling Polyoxide Conduction Channel Hot-Electron Injection (CHEI) Substrate Hot-Electron Injection (SHEI) Source-Side Injection (SSI) Secondary Impact Ionization Initiated Channel Hot-Electron Injection Physics of Degradation and Disturb Mechanisms Band-to-Band Tunneling Oxide Degradation Oxide Breakdown Conclusion 171 References 172 NOR FLASH STACKED AND SPLIT-GATE MEMORY TECHNOLOGY 179 Stephen N. Keeney, Manzur Gill, and David Sweetman 5.1 Introduction ETOX Flash Cell Technology Introduction Cell Structure 180

5 VIII CONTENTS Read (Sensing) Programming Erasing Array Operation Erase Threshold Control Process and Scaling Issues Key Circuits and Circuit/Technology Interactions Multilevel Cell Technology Circuits 5.3 SST SuperFlash EEPROM Cell Technology Introduction Cell Cross Sections and Layout Charge Transfer Mechanisms Erase Programming Cell Array Architecture and Operation Erase Threshold Control and Distribution Process Scaling Issues Key Circuit Interactions Multilevel Cell Implementation 5.4 Reliability Issues and Solutions Applications References Oxide Integrity Contact Integrity Data Retention Endurance Disturbs Life Test (Dynamic Burn-in) NAND FLASH MEMORY TECHNOLOGY Koji Sakui and Kang-Deog Suh 6.1 Overview of NAND EEPROM 6.2 NAND Cell Operation Cell Structure Erase Operation Program Operation Program Disturb Read Operation 6.3 NAND Array Architecture and Operation Staggered Row Decoder Self-Boosted Erase Inhibit Scheme

6 ix Self-Boosted Program Inhibit Scheme Read Operation Program Threshold Control and Program V, Spread Reduction Bit-by-Bit Verify Circuit Sophisticated Bit-by-Bit Verify Circuit Overprogram Elimination Scheme Process and Scaling Issues Shallow Trench Isolation NAND Technology (256-Mbit NAND) Booster Plate Technology Channel Boost Capacitance Cell Negative V, h Cell Free Wordline Spacing Cell Key Circuits and Circuit/Technology Interactions Shielded Bitline Sensing Method Full Chip Burst Read Operation Symmetric Sense Amplifier with Page Copy Function Source Line Programming Scheme Multilevel NAND Multilevel Circuit Technology Array Noise Suppression Technology Side-Wall Transfer Transistor Cell Three-Level NAND High-Speed Programming 301 References 307 Bibliography 310 DINOR FLASH MEMORY TECHNOLOGY 313 Moriyoshi Nakashima and Natsuo Ajika 7.1 Introduction DINOR Operation and Array Architecture DINOR Operation DINOR Cell Characteristics DINOR Array Architecture DINOR Advanced Array Architecture VGA-DINOR Device Structure and Fabrication Characteristics of the Cell with Asymmetrical Offset Source/Drain Structure DINOR Technology Features Low-Voltage Read Fast Read Access 321

7 7.4 DINOR Circuit for Low-Voltage Operation High-Voltage Generation [7] Wordline Boost Scheme 7.5 Background Operation Function Background Operation and DINOR Emulating Electrically Erasable Programmable Read-Only Memory (EEPROM) and Static Random-Access Memory (SRAM) Background Operation Fast Erase 7.6 P-Channel DINOR Architecture Introduction Band-to-Band Hot-Electron Injection Cell Operation DINOR BBHE Programmed Cell P-Channel DINOR Summary References Bibliography P-CHANNEL FLASH MEMORY TECHNOLOGY Frank Ruei-Ling Lin and Charles Ching-Hsiang Hsu 8.1 Introduction 8.2 Device Structure 8.3 Operations of P-Channel Flash 8.4 Array Architecture of P-Channel Flash NOR-Type Array Architecture NAND-Type Array Architecture 8.5 Evolution of P-Channel Flash Hsu et al. [1] Ohnakado et al. [4] Ohnakado et al. [5] Shen et al. [6] Chung et al. [7] Sarin et al. [8] Wang et al. [9] Ohnakado et al. [2] For Further Study 8.6 Processing Technology for P-Channel Flash NOR-Type Array Architecture NAND-Type Array Architecture References Bibliography

8 EMBEDDED FLASH MEMORY 373 Chang-Kiang (Clinton) Kuo and Ko-Min Chang 9.1 Introduction Embedded Flash Versus Stand-Alone Flash Memory Advantages of Embedded over Stand-Alone Flash Memory Disadvantages of Embedded over Stand-Alone Flash Memory Embedded Flash Memory Applications Applications by Device Type Applications by Function Applications by End Product Applications by Usage Embedded Flash Memory Cells Special Requirements and Considerations Cell Selection for Embedded Applications Embedded Flash Memory Design Special Requirements and Consideration Flash Module Design for Embedded Applications Design Techniques for Embedded Flash Module 398 References TUNNEL DIELECTRICS FOR SCALED FLASH MEMORY CELLS 407 T. P. Ma 10.1 Introduction Si0 2 as Tunnel Dielectric Historical Perspective Early Work on Silicon Nitride as a Tunnel Dielectric Jet-Vapor Deposition Silicon Nitride Deposition Properties of Gate-Quality JVD Silicon Nitride Films Deposited Silicon Nitride as Tunnel Dielectric N-Channel Floating-Gate Device with Deposited Silicon Nitride Tunnel Dielectric P-Channel Floating-Gate Device with Deposited Silicon Nitride Tunnel Dielectric Reliability Concerns Associated with Hot-Hole Injection Tunnel Dielectric for SONOS Cell Prospects for High-K Dielectrics 434

9 / Tunnel Barrier Engineering with Multiple Barriers Crested Barrier U-Shaped Barrier Summary References FLASH MEMORY RELIABILITY 445 Jian Justin Chen, Neal R. Mielke, and Chenming Calvin Ни 11.1 Introduction Cycling-Induced Degradations in Flash Memories Overview of Cycling-Induced Degradations Channel Hot-Electron Programming-Induced Oxide Degradation Tunnel-Erase-Induced Oxide Degradation Erratic Erase Flash Memory Data Retention Activation Energy and Accelerated Data Retention Bake Tests Charge-Loss and Gain Mechanisms in EPROMs and Flash EPROMs Flash EEPROM Cycling-Induced Data Retention Issues Data Retention Characteristics Related to Tunnel Oxide and Floating-Gate Poly Texture Soft Errors Flash Memory Disturbs Read Disturb and the Effects of Cycling Program Disturb Erase Disturb Block-to-Block Disturbs Stress-Induced Tunnel Oxide Leakage Current Uniform SILC in Thin Oxide SILC in Thin Oxide after Bipolarity Stress Microscopic Characteristics of Stress-Induced Leakage Current (msilc) Stress-Induced Leakage Current in Oxynitride Stress-Induced Leakage Current as the Limiting Factor for Tunnel Oxide Scaling Special Reliability Issues for Poly-to-Poly Erase and Source-Side Injection Program Poly-to-Poly Erase and Its Reliability Issues Source-Side Injection and Its Reliability Issues Process Impacts on Flash Memory Reliability 525

10 XIII Tunnel Oxide Process and Nitrogen Incorporation Effects of Floating-Gate Process and Morphology Stacked Gate SAS (Self-Aligned Source) Etch Process and Erase Distribution In-Line Plasma Charging Damage Impacts of Intermetal Dielectric and Passivation Films on Flash Memory Reliability High-Voltage Periphery Transistor Reliability High-Voltage Transistor Technology Reliability of HV Transistors in Flash Memory Products Process Defects: The Role of Cycling and Burn-in Design and System Impacts on Flash Memory Reliability Embedded Erase and Program Algorithm Redundancy and Defect Mapping Error Correction Concepts and Techniques Wear Leveling Flash Memory Reliability Screening and Qualification Introduction to Reliability Testing and Screening Classification of Flash Memory Reliability Tests Acceleration Models of the Reliability Tests Flash Memory Sort and Reliability Test Flow Flash Memory Product Qualification Flow Burn-In and Reliability Monitoring Program Failure Rate Calculations For Further Study Introduction Erratic Erase Stress-Induced-Leakage-Current Related Retention Effects Detrapping-Related Retention Effects Qualification Methods Flash Memory Floating-Gate to Floating-Gate Coupling New Program Disturb Phenomenon in NAND Flash Memory Impacts of Random Telegraph Signals and Few-Electron Phenomena on the Scaling of Flash Memories 576 References 579

11 MULTILEVEL CELL DIGITAL MEMORIES 591 Albert Fazio and Mark Bauer 12.1 Introduction Pursuit of Low-Cost Memory Multibit Storage Breakthrough Intel StrataFlash Technology Evolution of MLC Memory Technology Development Multilevel Cell Concept View of MLC Today Multilevel Cell Key Features Flash Cell Structure and Operation Multilevel Cell Operation Mixed Signal Design Implementation Low-Cost Design Implementation Low-Cost Process Manufacturing Standard Product Feature Set Programming Speed Read Speed Power Supply Reliability Further Reading: Multilevel Flash Memory and Technology Scaling Conclusion 614 References 614 ALTERNATIVE MEMORY TECHNOLOGIES 617 Gary F. Derbenwick and Joe E. Brewer 13.1 Introduction Limitations of Flash Memory Introduction Programming Voltage Programming Speed Endurance Scaling NROM Memories Introduction Memory Cell and Array; Structure and Operation Storage Mechanism Reliability Quad NROM Technology Fabrication 650

12 XV Scaling Products Summary Ferroelectric Memories Introduction Storage Mechanism Memory Cells and Arrays Fabrication Nonvolatile Characteristics Scaling Reliability Die and Test Cost Ferroelectric Products Ferroelectric Memory Summary Magnetic Memories Introduction Magnetic Random-Access Memory with Giant Magnetoresistive Devices Magnetic Random-Access Memory with Magnetic Tunnel Junction Devices Programming Characteristics Fabrication Nonvolatile Characteristics Scaling Reliability Die and Test Cost Magnetic Memory Summary Single-Electron and Few-Electron Memories Introduction Electric Charge Quantization in Solids Single-Electron Effects in Memory Cells Single-Electron Memories Few-Electron Memories Resistive and Hybrid CMOS/Nanodevice Memories Introduction Programmable Diode Technologies Hybrid CMOS/Nanodevice Resistive Memories Expected Performance Resistive Memory Summary NOVORAM/FRAM Cell and Architecture Introduction Crested Tunnel Barriers

13 XVi CONTENTS NOVORAM/FGRAM Cell and Architecture NOVORAM/FGRAM Summary Phase Change Memories Introduction Storage Mechanism GST Phase Change Material Memory Cell Memory Array and Support Circuitry Fabrication Scaling Reliability Products Summary 728 References 728 Index 741 About the Editors 759