CUSTOM FPGA CRYPTOGRAPHIC BLOCKS FOR RECONFIGURABLE EMBEDDED NIOS PROCESSOR

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1 CUSTO PGA CRYPTOGRAPHIC BLOCKS OR RECONIGURABLE EBEE NIOS PROCESSOR loš rutarovský, artn Šmka epartment of Electroncs and ultmeda Communcatons, aculty of Electrcal Engneerng and Informatcs, Techncal Unversty of Košce, Park Komenského 13, Košce, Slovak Republc, E-mal: {los.rutarovsky, artn.smka}@tuke.sk SUARY Ths paper ntroduces two custom blocks for Nos reconfgurable embedded processor mplemented on Altera eld Programmable Gate Arrays (PGAs). When operatons lke modular multplcaton and modular exponentaton of long ntegers or other complex algebrac functons are performed on a general-purpose processor they usually consume a lot of processor resources and executon tmes are not satsfactory. A soluton of ths problem les n development of custom coprocessors. The algebrac coprocessor for ontgomery ultplcaton () makes possble a fast executon of modular multplcaton wth large numbers that can be used n several publc key cryptographc algorthms. A True Random Number Generator (TRNG) enhances an applcaton of the Nos processor n cryptographc protocols. Untl now only few mplementatons of TRNG on PGA have been presented n lterature. We descrbe a custom TRNG mplementaton based on a recently proposed method that relably extracts ntrnsc randomness from low-jtter clock sgnals syntheszed by on-chp PGA analog PLLs. Both perpheral blocks are connected to the Nos processor through Altera Avalon bus that drectly supports scalable connecton and dfferent sources of the clock sgnal. In ths way we can optmally use the resources of Altera PGAs and mplement desgns customsable wth regard to avalable area resources and desred level of securty or tmng constrants. Proposed solutons sgnfcantly mprove securty and computatonal power of System on a Chp (SoC) embedded cryptographc applcatons based on the Nos processor. Keywords: cryptographc algorthm, SoC, embedded coprocessor, TRNG, IP blocks, ontgomery multplcaton 1. INROUCTION The recent rapd ncrease of the devces complexty and decreasng tme-to-market are forcng new ways of system desgn. Capable soluton of ths problem les n applcaton of System on a Chp (SoC) based on pre-desgned Intellectual Property (IP) cores and buldng blocks. IP blocks optmsed for target devces, and wth standardsed nterfaces offer fast soluton wthout need for longterm development of often-used parts of desgns. A cryptographc IP block ether executes whole cryptographc algorthms, or, as t s n our case, offers sgnfcant mprovement of computatonal power or securty level of the system. The coprocessor for ontgomery ultplcaton () enables a faster executon of large numbers of multplcaton needed for several cryptographc publc key algorthms. The True Random Number Generator (TRNG) enhances an applcaton of the Nos processor [1] n cryptographc protocols. Almost all cryptographc protocols requre generaton and use of secret values that must be unknown to attackers []. or example, TRNGs are requred to generate publc/prvate key pars for asymmetrc (publc key) algorthms ncludng RSA, SA, and ffe-hellman []. Unfortunately, standard processors (ncludng syntheszable Nos processor from Altera) are not able to generate true random numbers, as they are determnstc systems. The only way how to get true random numbers, hence true securty for cryptographc systems, s to buld a generator based on a random physcal phenomenon. Current modern eld Programmable Gate Arrays (PGAs) provde an alternatve hardware platform even for system-level ntegraton of embedded symmetrc and asymmetrc cryptographc algorthms, but not for hgh qualty TRNGs. ost hardware TRNGs follow unpredctable natural processes, such as thermal (resstance or shoot) nose or nuclear decay. Snce these prncples of random numbers generaton requre addtonal external devces, they cannot be embedded completely nsde the PGAs. Such TRNGs are not compatble wth modern PGAs and do not provde a SoC soluton. Ths paper descrbes a custom TRNG IP block based on a recently proposed method [3] that uses on-chp analog PLLs ncluded n Altera APEX PGAs [4]. The proposed method relably extracts ntrnsc randomness from low-jtter clock sgnals syntheszed by on-chp APEX analog PLLs. The TRNG s developed as a custom IP buldng block optmsed for Nos processor and provdes sgnfcantly hgher system level securty for complete embedded cryptographc SoC desgns. Publc key algorthms, such as RSA, ffe- Hellman key exchange algorthm or Ellptc curve cryptography use modular multplcaton and modular exponentaton of long ntegers (up to 048 bts for RSA). When these operatons are performed

2 8 Acta Electrotechnca et Informatca No. 1, Vol. 1, 001 on a general-purpose processor they consume a lot of tme and processor resources. A soluton of ths problem les n development of a custom coprocessor for modular long nteger multplcaton. Chosen algorthm provdes certan advantages n the mplementaton of modular multplcaton. The coprocessor has a scalable structure and uses effectvely the resources of PGA. Thanks to the mplementaton on PGA we can obtan a very flexble and secure soluton. The paper s organsed as follows: n Secton we present brefly the Nos processor and ts features mportant to nterface of the coprocessor and TRNG. In Secton 3 we gve a bref descrpton of the TRNG prncple and n Secton 4 the algorthm s presented. In the Secton 5 we deal wth a way of an mplementaton of the blocks and ther nterface to the Nos processor, mprovements of the coprocessor's structure, and speed and area results of mplementatons n Altera PGA devces. In the Secton 6 we present our conclusons and propose possble ways of future development.. AN OVERVIEW O EBEE NIOS PROCESSOR The Nos CPU [1] s a ppelned general-purpose RISC processor that s generated by propretary Altera VHL generator (SOPC Bulder) and can be synthessed and embedded n all recent Altera PGAs. The Nos supports both 3-bt and 16-bt archtectural varants. Both varants use 16-bt nstructons. The prncpal features of the Nos nstructon set archtecture are: Large, wndowed regster fle Nos mplementatons can nclude up to 51 nternal general-purpose regsters. The compler uses the nternal regsters to accelerate subroutne calls and local varable access. Smple, complete nstructon set both 3-bt and 16-bt Nos varants use 16-bt wde nstructons. 16-bt nstructons reduce code sze and nstructonmemory bandwdth. Powerful addressng modes the Nos nstructon set ncludes Load and Store nstructons that the compler uses to accelerate structure access and local-varable (stack) access. Extensblty users can ncorporate custom logc drectly nto the Nos arthmetc logc unt. The automatcally-generated software development kt ncludes macros for accessng custom nstructon hardware for C and assembly-language programs. Exstng Nos perpherals (e.g. UART, Tmer...) as well as new custom perpherals can be connected through an Avalon bus [5]. Avalon s a smple bus archtecture desgned for connectng on-chp processor(s) and perpheral together nto a SoC. The prncpal features of the Avalon bus are: Smplcty provdes an easy to understand protocol wth a short learnng curve. Optmzed resource utlzaton conserves Logc Elements (LEs) nsde the PGAs. Synchronous operaton ntegrates well wth other user logc that coexsts on the same PGA, whle avodng complex tmng analyss ssues. An example of a SoC structure wth user-defned custom perpherals s shown n g.1. Custom perpherals can be ncluded n a system block generated by SOPC Bulder what brngs optmsed mplementaton of the whole system, or they can be fed to Avalon bus as pre-synthessed blocks. The g. 1 depcts a smplfed clock dstrbuton, where s a prmary clock sgnal used for clockng of the 1 Nos and all of perpherals, and denotes addtonal clock sgnals whose functon s explaned later. data_rx data_tx ext 1 PLL SOPC Bulder System Block UART Custom perpheral Custom perpheral Custom perpheral Altera PGA g. 1 Example of a system module ntegrated wth custom perpherals nto an Altera PGA 3. BASIC PRINCIPLE O TRNG IP BLOCK Several well-known TRNGs requre addtonal off-chp component whch decreases a securty level of the system. In addton, some practcal mplementatons based on free runnng oscllators are not secure enough for cryptographc applcatons as the entropy ncrease s not suffcently hgh, so that the output of the generator can be predcted [6]. In next we shortly descrbe an mplementaton completely embedded n Altera PGAs [3]. odern Altera PGAs use reconfgurable analog on-chp PLLs to ncrease performance and to provde on-chp clock-frequency synthess. The basc prncple behnd our method s an extracton of a randomness from the jtter of the clock sgnal syntheszed n the embedded analog PLL [3] (llustrated n g.). PLL q(nt) XOR ecmator (K) x(nt) g. Basc prncple of randomness extracton from the low-jtter clock sgnal The jtter s detected by the samplng of a reference clock sgnal ( 1 n g. 1) wth

3 8 Acta Electrotechnca et Informatca No. 1, Vol. 1, 001 frequency usng ratonally related clock sgnal ( n g. 1) syntheszed n the PLL wth the frequency: K K where m and k can range from to 160, and n ranges from 1 to 16 [4]. Let values of multplcaton factor K and dvson factor K be relatve prmes, so GC( K, K where GC s an abbrevaton of Greatest Common vsor. Equaton () ensures that the maxmum guaranteed dstance between the closest edges of and (denoted as AX( T )) over the perod: mn T K K T (3) T s equal to [3]: σ jt m n k, (1) ) 1, () GC( K, K) AX( Tmn ) T 4K GC( K, K) T. 4K (4) By proper choosng of K, K and T t s possble to guarantee that AX( T ) < σ, where mn s the RS (root mean square) value of PLL ntrnsc jtter. Accordng to [7] and [8], an ntrnsc jtter can be approxmated by Gaussan dstrbuton and σ 15ps. oreover, the jt proposed method s nsenstve to an overall jtter characterstc as far as an ntrnsc PLL jtter s ncluded. In general, the obtaned bts are statstcally based random bts. Acceptable TRNG should produce output bts wth equal probablty. A common way how to reduce the statstcal bas s to use a XOR corrector. Non-overlapped pars of bts are XORed together. In ths way, a unform dstrbuton of generated true random bts wth perod T (3) s guaranteed [3]. 4. SCALABLE WOR-BASE ONTGOERY ULTIPLICATION ALGORITH jt E Z X mod, (5) that a bnary or general m -ary method can break nto a seres of modular multplcatons. All of these computatons have to be performed wth large k -bt ntegers (typcally k { 104, 048 }). The well-known algorthm [9] speeds-up modular multplcaton and squarng requred for exponentaton (5). It computes the product for k -bt ntegers X, Y as 1 ( X, Y) XYR mod, (6) where R k, and s an nteger n the range k 1 k < < such that GC ( R, ) 1. Basc (6) can be used for effcent computaton of (5) by the standard ontgomery exponentaton algorthm []. The startng pont of ths algorthm s the. The faster s performed, the faster exponentaton process wll be accomplshed. or mplementaton of on PGAs we use a modfed verson of ultple Word Radx- ontgomery ultplcaton (WR) algorthm [10]. WR wth word wdth w performs btlevel computatons and produces word-level outputs. The scalablty and word-orentaton of the algorthm makes possble to mplement the scalable coprocessor. or operands wth a k -bt precson, e k w words are requred. WR algorthm scans word-wse operand Y (multplcand) and, and bt-wse operand X (multpler). ependng on tmng requrements, area lmtatons and connected verson of Nos processor we can choose the word wdth w 8,16,3, 64 or descrpton of the WR algorthm we use the followng denomnatons: ( e 1) ( 1) ( 0) ( ),,,, ( e 1) ( 1) ( 0) Y ( Y,, Y, Y ), (7) X ( x,, x, x ). k The concatenaton of vectors A and B s represented as ( A, B ). A partcular range of bts n a vector A from poston to poston j s represented as th A. The bt poston of the k word j.. ( ) k of A s represented as A. Then a fragment of the WR algorthm can be descrbed as: Basc mathematcal operaton used by RSA s modular exponentaton []:

4 10 Acta Electrotechnca et Informatca No. 1, Vol. 1, 001 for 0 to k 1 do ( 0) ( 0) ( 0) ( CS, ) xy + S f ( 0) S0 1 then ( 0) ( 0) ( 0) ( CS, ) C+ S + for j 1 to e 1 do S ( j) ( j) ( j) ( j) ( CS, ) C+ xy + + S ( ) e ( C, Sw 1..1) ( j 1) ( j) ( j 1) 0, w 1..1 S S S ( e 1) ( 1) The computatons are performed wth precson w bts, what means that they are ndependent on the operands precson k. What vares s the number of loop teratons needed to compute the result of modular multplcaton. ue to the mutual dependency of the operatons nsde the j loop the parallel executon s not possble. Ths s not the case of the nstructons n dfferent loops whch can be executed n parallel. Ths fact makes possble to mplement even more flexble and faster scalable ppelned archtecture. 5. HARWARE APPING TO THE ALTERA PGA The Altera Nos Embedded Processor evelopment Board wth APEX EP0K00 [11] has been used for the mplementaton of the proposed IP blocks. The board and the provded software form powerful development tools for mplementaton and testng of the desgns. Thanks to the fact that the custom blocks are descrbed by VHL code we obtaned parametersed desgns that can be modfed accordng to the desred tme and area lmts. All presented results have been obtaned by usng the Altera uartus II ver.., Altera Nos., and PGA Advantage 5.3 tools TRNG The same Nos development board was also used n [8] for reference PLL measurements so we can expect that jtter characterstcs presented n [8] can be drectly appled to our desgn. The confguraton of the TRNG block s depcted n g.3. The board features a PLL-capable APEX EP0K00-X wth four on-chp analog PLLs. We used the same PLL organsaton as descrbed n the prevous desgn of TRNG [3], the values of parameters K and K were chosen accordng to the connecton of the TRNG to the Nos processor. The two on-chp PLLs shown n g.3 have been used for generatng and sgnals. The external clock source was 33.3Hz, on-chp syntheszed clocks were EXT Hz EXT 33.3 Hz PLL4 clk1 nclk clk0 PLL clk1 nclk clk0 80*14 EXT Hz 11* EXT EXT Hz Hz 4 edcated Clocks G4 G G1 G3 g. 3 Actual PLL confguraton used n the proposed TRNG IP block 33.3Hz and ( 110 / 3333) 11.9 Hz (can be modfed accordng to other requrements). Accordng to (4) these parameters ensure that AX( T ) 6.7 ps < σ. The output bt-rate of the TRNG s 1 / T bts/s. Example of resource requrements of 16-bt and 3-bt Nos wth correspondng 16-bt and 3-bt TRNG mplementatons are shown n Tab.1 (LE Logc Element s the basc buldng block of Altera PGAs). Name of the block # LEs % of total capacty Nos-16 Nos UART 170 TRNG-16 TRNG ALL ALL + nterface logc Tab. 1 Results of TRNG mappng to Altera APEX EP0K00-X TRNG nterface The TRNG perpheral s connected to Avalon bus as a standard memory mapped perpheral. TRNG can be accessed from the Nos processor through three custom regsters. ata (read only) and Control/Status regsters (wrte/read access) are mapped nto two memory locatons shown n g.4. read access TRNG_base+0 TRNG ata (data regster) TRN G_base+1 X X X... X X X C V (status regster) mn wrte access X X X... X X X IE (control regster) jt :3 V 1/0 - vald/nvald data C 1/0 - proper/mproper clocks IE1/0 - nterrupt enable/dsable X - undefned g. 4 ata and Control/Status regsters of 16-bt TRNG TRNG can be accessed by the standard memory poolng as well as by usng an nterrupt servce request that can be enabled by an applcaton program. The exact poston of a TRNG_base

5 8 Acta Electrotechnca et Informatca No. 1, Vol. 1, 001 address and TRNG_IR can be confgured by the SOPC Bulder TRNG statstcal testng Statstcal testng s very mportant for random number generators dedcated to usage n cryptographc algorthms. ore detaled descrpton of applyng NIST statstcal test sute [1] on presented TRNG can be found n [3]. Whle n [3] the generator s the only one block mplemented on the devce, n ths paper we present confguraton wth TRNG connected to the Nos processor. ore complex desgn and logc clocked by dfferent clock sources can affect the jtter dstrbuton. The am of tests was to detect possble devatons of statstcal characterstcs. After testng we have obtaned smlar results of statstcal tests as n [3]. Ths confrms the fact that the relablty of TRNG and the randomness of ts output are ndependent on the desgn complexty, PGA confguraton, and nternal crcut actvty. 5.. Scalable coprocessor The mplemented radx- coprocessor s a unt realzng the WR algorthm. Input values ( X,Y, and ) as well as the result S obtaned by the coprocessor are stored n coprocessor's memory. Snce nput and output values can have hgh precson (104 bts or more), we have decded to store nputs and ntermedate results n Embedded emory Blocks (EBs). EBs can mplement varous types of memory wth one block sze 048 bts [4]. Therefore, the coprocessor has been splt nto two blocks: a Radx- ontgomery multpler and a dual port data memory. In order to reduce storage and arthmetc hardware complexty, data path of the coprocessor uses X,Y, and n a standard nonredundant form. The nternal sum S s receved and generated n the redundant Carry-Save form [13]. Therefore, the bt resoluton of the sum S s effectvely doubled and we use denomnaton 1 S j and for t. Then 1 S represents the second bt th of the j word of the frst part of S (see g. 5). The advantage of Carry-Save form s faster addton process wthout usng the carry logc especally for w > 16. The data path desgn s based on the structure presented n [10]. The unt conssts of two layers of carry-save adders as t s shown n g. 5 for w 3. Input c represents latched value t that s S ( ) ( ) ( ) 0 0 the least sgnfcant bt of the value S + x Y and s used to control the addton of. The most mportant parameter nfluencng the overall multpler speed s the memory access tme. Snce durng one cycle prevous results 1 S and S g. 5 Structure of the unt for w 3 (A ull Adder) have to be read and current results from the last stage have to be wrtten to the same memory, we have chosen the EB confguraton as a dual port RA usng the Altera-specfc functon lpm_ram_dp from the Lbrary of Parameterzed odules (LP). The memory wth regstered nput/output data has been found as the faster mplementaton. The ppelned verson of the coprocessor has been mplemented usng changes publshed n [14]. The data path s organzed as a ppelned structure of several unts shown n g. 6. A dstrbuton of sgnal X to the unts has been found as a crtcal path n the tme analyss. Therefore ths part has been redesgned by addng an 1-bt regster for x nto the unt (see g. 6). Thanks to ths modfcaton there are no lmtatons for a number of unts as n [15]. g. 6 Block dagram of the coprocessor data path

6 1 Acta Electrotechnca et Informatca No. 1, Vol. 1, 001 The maxmum degree of parallelsm that can be obtaned wth ths archtecture s found as: asserted. Ths state perssts untl the results are read wthn the nterrupt routne by the processor. e k 104 k 048 nmax. (8) LEs f LEs clk f clk n The number n denomnator expresses the n number of clock cycles after whch the output of the n unt s vald. When less than n max unts are n avalable, the total executon tme wll ncrease, but on the other hand the area occupaton of the Tab. Area occupaton (LEs)/max f clk (Hz) coprocessor can be changed accordng to the area constrants of a target devce. The computaton tme of the coprocessor ( w 3, n 1..4 ) of the sngle operaton when n n max k 104 k 048 unts are used s: n n 1 k T + f clk wn n. (9) n n The coprocessor has 3 man parameters ( w, e, and n ) that can be changed accordng to the requred area of the mplemented coprocessor and the requred tmngs for computatons ( n, w ) or the securty level ( e ). Ths approach gves hgh flexblty to the processor and coprocessor desgn. Area occupaton expressed n LEs and maxmal possble PGA clock frequency for Altera APEX 0K00E are gven n Table for precsons k 104, and 048 bts. The coprocessor has the maxmal clock frequency sgnfcantly hgher than the Nos processor ( f Hz ). To acheve hgher performance of the system, we use one clock sgnal ( ) for the Nos processor, and another one ( f clk f clk Nos clk Nos ), wth hgher frequency, for the coprocessor. The computatonal tme (n µs) of the sngle operaton (accordng to the equaton 9) s presented n Table 3 for frequency value of the coprocessor clock sgnal f Hz. clk coprocessor nterface The way n whch the coprocessor s connected to the embedded processor s mportant for the computng process control (the process startng and the processor status checkng), and for an exchange of processed data. In the prevous soluton [15] the status regster has been used for checkng the actual status of the coprocessor and the computatonal process. The current verson uses the communcaton over an nterrupt. Ths soluton s more sutable for software control of coprocessors and for a confguraton wth several coprocessors that can be used for parallel computaton of. After the computaton of the nterrupt sgnal of the processor s Tab. 3 Computatonal tme T (µs) for w 3, f Hz, n 1..4 clk Thereafter new operands can be loaded nto the memory and the whole process starts agan. The second area where the most sutable soluton needs to be found s the nterface between the coprocessor's memory block and the bus of the embedded processor. Snce there s a need for faster clockng of the coprocessor, we have assumed the case wth two clock sgnals (see g. 7). g. 7 ext PLL SOPC Bulder System Block f clk f clknos Coprocessor Block dagram of the nterface between the coprocessor and the Nos processor The slower one s connected to the processor, and through the bus and the nterface to the coprocessor. All the processes concernng the operatons between the processor's bus and the coprocessor's memory block are clocked by ths sgnal ( ). The operatons nsde the f clk Nos coprocessor are clocked by the external faster clock sgnal ( ). Thanks to ths clock sgnals f clk organsaton almost three tmes hgher performance has been obtaned compared to the prevous mplementaton [15].

7 8 Acta Electrotechnca et Informatca No. 1, Vol. 1, CONCLUSIONS AN UTURE EVELOPENT The paper has demonstrated the possblty of custom IP blocks development for cryptographc applcatons n PGAs. Advancements n PGAs provde new optons for desgn engneers. PGAs mantan the advantages of custom functonalty, lke an ASIC, but avod hgh development costs and the nablty to make desgn modfcatons after productons. Implemented IP blocks enhance the applcablty of the Nos processor n a cryptographc SoC. Both blocks have scalable structure and hence create together wth the parametersable Nos processor very flexble soluton. A support for faster modular multplcaton and a need of true random numbers are functons requred for several currently used cryptographc protocols and algorthms Thanks to the changes n mplemented coprocessor we obtaned faster soluton wth optmsed features of the nterface. The fact that TRNG can be mplemented nsde the PGAs represents sgnfcant securty and system advantage n embedded cryptographc applcatons. The future development should nclude the mplementatons of other cryptographc algorthms and the mprovements of the presented blocks. REERENCES [1] NIOS. CPU. ata Sheet, September 00, ver. 1.3, pp. 1-14, [] J.A. enezes, P.C. Oorschot, and S.A. Vanstone: Handbook of Appled Cryptography, CRC Press, New York, [3] V. scher and. rutarovský: True Random Number Generator Embedded n Reconfgurable Hardware, Proceedngs of the Workshop on Cryptographc Hardware and Embedded Systems CHES 00, Redwood Shores, Calforna, USA, August 00, pp [4] APEX 0K Programmable Logc evce amly. ata Sheet, ebruary 00, ver. 4.3, pp , [5] Avalon Bus Specfcaton, Altera Reference anual, January 003, ver..1, pp , [6]. chtl: How to Predct the Output of a Hardware Random Number Generator, In C.. Walter, C. K. Koc, Ch. Paar (Eds.): Cryptographc Hardware and Embedded Systems 003, LNCS 779, Sprnger, Berln, 003, pp [7] Jtter comparson analyss: APEX 0KE PLL vs. Vrtex-E LL, Techncal Bref 70, January 001, ver.1.1, pp.1-7, [8] Superor Jtter management wth LLs. Vrtex Tech Topc VTT013(v1.), January 1, 00, pp. 1-6, [9] C.K. Koc, T. Acar: Analyzng and Comparng ontgomery ultplcaton Algorthms, IEEE cro, (16) 3, pp. 6-33, June [10] A.. Tenca, C.K. Koc: A Scalable Archtecture for odular ultplcaton Based on ontgomery s Algorthm, IEEE Transactons on Computers, 5(9), pp , September 003. [11] Nos Embedded Processor evelopment Board, Altera ata Sheet, v..1, Aprl 00, pp.1-, [1] A. Rukhn, et al.: A statstcal test sute for random and pseudorandom number generators for cryptographc applcatons, NIST Specal Publcaton 800-, ay 15, 001, pp , cs- [13] C.K. Koc: RSA Hardware Implementaton, pp.1-8, August [14]. rutarovský, V. scher: Implementaton of Scalable ontgomery ultplcaton Coprocessor n Altera Reconfgurable Hardware, Proceedngs of 5 th Internatonal Scentfc Conference SP CO 001, Košce, Slovaka, pp , November 001. [15]. Šmka, V. scher: ontgomery ultplcaton Coprocessor for Altera Nos Embedded Processor, Proceedngs of the 5 th Internatonal Scentfc Conference on Electronc Computers and Informatcs 00, Košce, Slovaka, pp , October 00. BIOGRAPHY loš rutarovský was born n 1965 n Prešov, Slovak Republc. He receved the Sc degree and Ph degree n radoelectroncs from the aculty of Electrcal Engneerng and Informatcs, Techncal Unversty of Košce, n 1988 and 1995, respectvely. He defended hs habltaton work - gtal Sgnal Processors n gtal Sgnal Processng n 000. He s currently workng as an assocated professor at the epartment of Electroncs and ultmeda Communcatons, Techncal Unversty of Košce. an areas of hs research are appled cryptography, dgtal sgnal processng, and algorthms for embedded cryptographc archtectures. artn Šmka was born n 1979 n Košce. He receved hs Sc. degree n Electroncs and Telecommuncatons n 00 after defendng hs aster's Thess - Concepton of connecton of embedded processor to arthmetc coprocessor n SOPC Altera. Currently he s a Ph student at the epartment of Electroncs and ultmeda Communcatons, Techncal Unversty of Košce and hs man research area s an mplementaton of cryptographc blocks on PGAs.