Policy-Based RTL Design. Bhanu Kapoor and Bernard Murphy Atrenta Inc. EDA Challenges
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1 Policy-Based RTL Design Bhanu Kapoor and Bernard Murphy Atrenta Inc. Atrenta Inc Page 1 EDA Challenges Technology allows for 100M transistors on a chip Good but point EDA solutions exit Time consuming due to complexity of designs Discover problems after hours and days of run Early decisions affect entire design process Guiding a given RTL towards various design constraints remains a big challenge Reliable RTL design process Atrenta Inc Page 2 1
2 Challenges in Product Development Design commitment Knowledge Gap Available Design Information Design Cycle Atrenta Inc Page 3 Policy-Based RTL Design Policies that guide the creation of efficient RTL Target design needs early in the design cycle Conflicting issues known early Long simulation and synthesis not always needed Disseminate expert knowledge Towards Golden RTL Atrenta Inc Page 4 2
![Model for Policy Management Policy Lint & Reuse [OpenMORE & STARC] RTL Signoff Design Timing, Testability, Power Verification SoC Integration](/docs-images/79/79732748/images/3-0.jpg "Rule Groups Rules Policy Application Policy Creation Analysis and Report Atrenta Inc Page 5 Rules and Groups Rule Group Rule Atrenta Inc Page 6")
3 Model for Policy Management Policy Lint & Reuse [OpenMORE & STARC] RTL Signoff Design Timing, Testability, Power Verification SoC Integration Rule Groups Rules Policy Application Policy Creation Analysis and Report Atrenta Inc Page 5 Rules and Groups Rule Group Rule Atrenta Inc Page 6 3
4 Parameterized Policies Max levels of logic Max fanout Atrenta Inc Page 7 Policy Engines Fast high-level synthesis Traversal Engine Cycle-based simulator Atrenta Inc Page 8 4
5 Analysis & Report Guiding from detection of issues to solution Various formats for reporting - variations on summary - scoring Software management of underlying issues - manage by design units, files, design as a whole - manage the state of issues - mechanisms to control reporting Atrenta Inc Page 9 Policies DFT Timing Tool Policies Area RTL Code Power Clocks Reuse Verification Atrenta Inc Page 10 5
6 Levels of Logic Cross-probe to schematic Cross-probe to RTL code Levels of Logic Violation Atrenta Inc Page 11 Atrenta Inc Page 11 Fanout Violations Atrenta Inc Page 12 Atrenta Inc Page 12 6
7 Resolving Issues By Simulation Only one driver active at a time for tri-state buses 'DWD /RJLF 6\VWHP /RJLF (QDEOH /RJLF Atrenta Inc Page 13 Atrenta Inc Page 13 Multiple Clock Domain Issues module abc clk_1) begin // clk domain1 q1 <= din; module // of module abc module xyz. ) begin // clk domain2 q2 <= q1; module // of module xyz.. ) begin //synch dout <= q2; assign f2 = func2(q1,..); assign f1 = func1(dout,..); assign sig1 = f1 & f2; Signals from multiple clock domains converging to a common logic-- multi-transition, multi-sample signals din q1 q2 dout f1 clk_1 Module boundaries f2 sig1 Atrenta Inc Page 14 Atrenta Inc Page 14 7
8 Clock Synchronization Problems module synch clk1) begin q <= d; z <= w; ready <= dready; End // generate sync signal clk2) begin rds <= ready; pass <= rds; // synchronize clk2) begin if (pass) qsync = q; zsynch = z; d w CK2 CK1 ready q z pass CK2 z-bus not correctly synchronized May not be found in simulation Impact Yield issues Field failures E qsync zsync Atrenta Inc Page 15 Clock Synchronization module abc clk_1) begin // clk domain1 ar <= a;br <= b; r<=ready module // of module abc module xyz. ) begin // clk domain2 rr <= r; ) begin // clk domain2 rs <= rr; ) begin // clk domain2 if (rs) as<= ar; if (rr) bs<= br;.. module // of module xyz Enable of destination flop is driven by a synchronized signal a clk_1 b clk_1 ready ar br r rr rs as bs Atrenta Inc Page 16 Atrenta Inc Page 16 8
9 Testability Issues Signals from mixed edge domains combined Create problems for scan insertion Not found until ATPG check Impact Wasted implementation cycles Schedule delays module src1 clk) q1 = d module src2 clk) q2 = g module aggregate clk) mix = q1 & q2 CLK d g src 1 src 2 CLK aggregate mix Atrenta Inc Page 17 Clock Gating Use of gated clocks to selectively turn on/off various units in the design All large functional units are use enabled clock ƒ ƒ All banks of memory controlled by enabled clock Large fanout flops use enabled clocks Clock Enable Functional Unit Atrenta Inc Page 18 9
10 Pre-computation Suggest the use of precomputation An Bn Example: A > B where A and B are 32-bit buses, result can be obtained by examining A[31] and B[31] and rest of the computation gated based on this result An-1 B1 A>B Atrenta Inc Page 19 Summary Policy-Based RTL Design Policy Management Elements of Policy Policy elements Policy engine Analysis and reporting Examples of pertinent design issues Atrenta Inc Page 20 10
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