Chapter 6: Pipelining

Transcription

1 CSE 322 COPUTER ARCHITECTURE II Chapter 6: Pipelining Chapter 6: Pipelining Febrary 10, Clothes Washing CSE 322 COPUTER ARCHITECTURE II The Assembly Line Accmlate dirty clothes in hamper Place in washer Unload washer into hamper and move to dryer Unload dryer into hamper and move to folding table & fold Place folded clothes in hamper & pt away Compare yo doing yor wash to a landry - with 1 person per fnction YOU: TIE WASH DRY FOLD PUT_AWAY If 1 hor per step, this takes hors Landry: WASH1 DRY1 FOLD1 PACK1 WASH2 DRY2 FOLD2 PACK2 WASH3 DRY3 FOLD3 PACK3 WASH DRY FOLD PACK Still takes hors per patron, BUT!!!! Landry gets 1 patron/hor thrpt Chapter 6: Pipelining Febrary 10,

2 CSE 322 COPUTER ARCHITECTURE II Atomobile Assembly Plant Chemical factory Garden Hose Cooking Other Eamples General Characteristics Complete process broken down into S independent pieces Each piece done independently at a stage Stages arranged in linear order to match process As each stage finishes its piece, it passes piece to net stage Time for one complete processing seqence: sm of all stages BUT: rate at which we can initiate new work = ma of any stage time If times for all S stages are eqal to T: Time for one initiation to complete still ST; Time between 2 initiaties = T NOT ST! Initiations per second = 1/T Pipelining: Overlap mltiple eections of same seqence - Improves throghpt, not the time to perform a single operation Chapter 6: Pipelining Febrary 10, CSE 322 COPUTER ARCHITECTURE II Book s Approach to Draw Pipeline Timing Diagrams Time rns left to right, in nits of stage time Each row below corresponds to distinct initiation Bondary between 2 colmn entries: pipeline ister (eg hamper) st look at colmn contents to see what each stage is doing what Wash1 Dry1 Fold1 Pack1 Wash2 Dry2 Fold2 Pack2 Wash3 Dry3 Fold3 Pack3 Wash Dry Fold Pack Wash5 Dry5 Fold5 Pack5 Wash6 Dry6 Fold6 Pack6 Wash7 Dry7 Fold7 Pack7 Wash8 Dry8 Fold8 Pack8 Wash9 Dry9 Fold9 Pack9 TIE for N initiations = NT + (S-1)T Thrpt: Time per initiation = T + (S-1)T/N ==> T! Chapter 6: Pipelining Febrary 10, 2000

3 CSE 322 COPUTER ARCHITECTURE II An Alternative: Reservation Tables As before, time rns left to right, in nits of stage time Each row below corresponds to a distinct stage of processing Individal initiations are diagonal Stage Wash Dry Fold Pack Easy to see what stage is doing what Harder to see each initiation We will se both Chapter 6: Pipelining Febrary 10, CSE 322 COPUTER ARCHITECTURE II Complications Dividing processing so each stage takes same time Strctral Hazard: cannot spport the combination of operations to do concrrently - Eg. combined washer/dryer, not separate - Eg. only one memory, not two - Soltion: architect so problem does not eist or add hardware Hazard: need opt of one stage for an earlier stage of a scceeding initiation - Eg. deciding on wash time of football niforms - Eg. sing otpt of an add as inpt to a scceeding add - Soltion: forward on a special path back to where its needed Control Hazard: cannot even decide on what to initiation to start net withot completing a crrent one - Eg. branching on vale in a compted by previos instrction - Soltion: predict (i.e. gess) which way to go Stalls: know what to do, bt some stage takes longer than one cycle - Eg. memory takes longer than one cycle - Introdces bbble of nsed time slots into pipeline - Soltion: fill with ot-of-order initiations (aka sperscalar) Chapter 6: Pipelining Febrary 10,

4 Unpipelined: CSE 322 COPUTER ARCHITECTURE II Ideal Digital System Pipeline Speedp Latch Pipelined: Latch combinational logic delay = τ combinational logic delay = τ combinational logic delay = τ combinational logic delay = τ delay for 1 piece of = τ + latch_setp (assme small) appro delay for 1000 pieces of = 000τ combinational logic delay = τ combinational logic delay = τ combinational logic delay = τ combinational logic delay = τ Latch Latch Latch delay for 1 piece of = (τ + latch_setp) appro delay for 1000 pieces of = τ + 999τ = 1003τ 000 speedp for 1000 pieces of = Latch Latch Ideal speedp = nmber of pipeline stages Chapter 6: Pipelining Febrary 10, CSE 322 COPUTER ARCHITECTURE II Processing of IPS Instrctions Increment program conter; fetch net instrction one or two isters according to instrction fields emory- Reference Arithmetic- Logic Branching Calclate effective ess Eecte op-code Compare (check flag) / to memory to ister Change instrction ess Chapter 6: Pipelining Febrary 10,

5 CSE 322 COPUTER ARCHITECTURE II The Instrction Eection Seqence Instrction eection in a processor (and possible times) IF - instrction fetch (2ns) ID - Decode & fetch ister operands (1 ns) EX - Perform operation (2ns) E - Perform memory operation (2ns) WB - reslt (if any) back into ister file (1ns) Hm? - 5 stages => 5X performance increase over single cycle design? Electrical Design Challenge: can we make hardware to do each stage in same time? Chapter 6: Pipelining Febrary 10, CSE 322 COPUTER ARCHITECTURE II Timimg The Instrction Seqence One Initiation: IF ID EX E WB Total time = 8 ns Try to overlap IF ID EX E WB Doesn t line p! IF ID EX E WB Possible soltion: insert 1 ns after ID to allow alignment IF ID EX E WB Strctral Hazard IF ID EX E WB IF ID EX E WB IF ID EX E WB Chapter 6: Pipelining Febrary 10,

6 CSE 322 COPUTER ARCHITECTURE II A Better Soltion Delay ID by 1 ns also 9 ns IF IF ID EX IF ID E WB EX E WB ID EX EWB IF ID EX E WB 15 ns No Strctral Hazard One initiation = 9 ns oe 10 ns (depennding on how yo look at it) initiations = 15 ns => Ave of 1 initiation every 3.75 ns! How long for 1000 initiations? What is eqivalent time between initiations: What is effective speedp? Chapter 6: Pipelining Febrary 10, CSE 322 COPUTER ARCHITECTURE II Why is IPS ISA Good Pipeline Target? All instrctions are the same length - decoder doesn t need to figre ot how long ister specifiers in instrction always in same place - go get isters before knowing instrction type Only LOAD/STORE memory access - need only 1 emory operands all assmed aligned in memory Discssion: what if we did it differently? Chapter 6: Pipelining Febrary 10,

7 CSE 322 COPUTER ARCHITECTURE II Review: The Single-Cycle path Instrction fetch Instrction decode / ister fetch Eecte / ess calclation emory access back ess Instrction emory etend emory EX/E E/WB Flow is left to right, with 2 eceptions -back (into ister file) Selection of net vale (increment or branch ess) Chapter 6: Pipelining Febrary 10, CSE 322 COPUTER ARCHITECTURE II Program eection order (instrctions) ltiple Clock Cycle Pipeline Diagram Time (clock cycles) CC 1 CC 2 CC 3 CC CC5 CC6 CC 7 lw $1, 100($0) I D lw $2, 200($0) I D lw $3, 300($0) I D Sppose each instrction cold have its own path Shows hardware sed by each instrction dring each phase of eection I D Instrction emory ister emory ister Chapter 6: Pipelining Febrary 10,

8 CSE 322 COPUTER ARCHITECTURE II Inserting Pipeline into path Nmber of pipeline bits varies between stages EX/E E/WB ess Instrction emory etend emory Latch Latch Latch Latch Chapter 6: Pipelining Febrary 10, CSE 322 COPUTER ARCHITECTURE II Eecting Instrctions in Pipelined path Following charts describe 3 scenerios: 1. Processing of load word (lw) instrction - bg inclded in design (ake SURE yo nderstand bg!) 2. Processing of lw - bg corrected (ake SURE yo nderstand fi!) 3. Processing of lw followed in pipeline by sb (Set the stage for discssion on HAZARDS and inter-instrction dependencies!) Chapter 6: Pipelining Febrary 10,

9 CSE 322 COPUTER ARCHITECTURE II lw Instrction fetch Load Word: Cycle 1 Note: prple in a latch indicates from that instrction stored there EX/E E/WB ess Instrction emory etend emory Chapter 6: Pipelining Febrary 10, CSE 322 COPUTER ARCHITECTURE II Load Word: Cycle 2 lw Instrction decode EX/E E/WB ess Instrction emory etend emory Chapter 6: Pipelining Febrary 10,

10 CSE 322 COPUTER ARCHITECTURE II Load Word: Cycle 3 lw Eection EX/E E/WB ess Instrction emory etend emory Chapter 6: Pipelining Febrary 10, CSE 322 COPUTER ARCHITECTURE II Load Word: Cycle lw emory EX/E E/WB ess Instrction emory etend emory Chapter 6: Pipelining Febrary 10,

11 CSE 322 COPUTER ARCHITECTURE II Load Word: Cycle 5 Where s the bg? lw back EX/E E/WB ess Instrction emory etend emory Chapter 6: Pipelining Febrary 10, CSE 322 COPUTER ARCHITECTURE II Fiing Load Bg Bg: sorce for is invalid Soltion: Need to preserve ister nmber for write-back additional pipeline bits for write ister ess EX/E E/WB ess Instrction emory etend emory Chapter 6: Pipelining Febrary 10,

12 CSE 322 COPUTER ARCHITECTURE II Processing a Two-Instrction Seqence Eamine mltiple-cycle and single-cycle diagrams for a seqence of 2 independent instrctions (no common isters between instrctions): lw $10, 9($1) sb $11, $2, $3 ltiple-cycle diagram Program eection order (instrctions) Time (clock cycles) CC 1 CC 2 CC 3 CC CC5 CC6 lw $10, 9($1) I D sb $11, $2, $3 I D newest instrction at bottom Chapter 6: Pipelining Febrary 10, CSE 322 COPUTER ARCHITECTURE II lw $10,9($1) Instrction fetch Single-Cycle Diagrams: Cycle 1 EX/E E/WB ess Instrction emory etend emory Chapter 6: Pipelining Febrary 10,

13 CSE 322 COPUTER ARCHITECTURE II sb $11,$2,$3 Instrction fetch Single-Cycle Diagrams: Cycle 2 lw $10,9($1) Instrction decode EX/E E/WB ess Instrction emory etend emory Chapter 6: Pipelining Febrary 10, CSE 322 COPUTER ARCHITECTURE II Single-Cycle Diagrams: Cycle 3 sb $11,$2,$3 Instrction decode lw $10,9($1) Eection EX/E E/WB ess Instrction emory etend emory don t need sign etend, bt don t know this yet Chapter 6: Pipelining Febrary 10,

14 CSE 322 COPUTER ARCHITECTURE II Single-Cycle Diagrams: Cycle sb $11,$2,$3 Eection lw $10,9($1) emory EX/E E/WB ess Instrction emory etend emory Chapter 6: Pipelining Febrary 10, CSE 322 COPUTER ARCHITECTURE II Single-Cycle Diagrams: Cycle 5 sb $11,... emory lw.. back EX/E E/WB ess Instrction emory etend emory Chapter 6: Pipelining Febrary 10,

15 CSE 322 COPUTER ARCHITECTURE II Single-Cycle Diagrams: Cycle 6 sb. back EX/E E/WB ess Instrction emory etend emory Chapter 6: Pipelining Febrary 10, CSE 322 COPUTER ARCHITECTURE II Pipelined Control Potentially very complicated, need to approach this methodically Eample: independent instrctions (no ister operands in common) lw $10, 9($1) sb $11, $2, $3 and $12, $, $5 or $13, $6, $7 add $1, $8, $9 Eample: dependent instrctions ($2 sed in seqential instrctions) sb $2, $1, $3 # ister $2 written by sb and $12, $2, $5 # 1st operand ($2) depends on sb or $13, $6, $2 # 2nd operand ($2) depends on sb add $1, $2, $2 # 1st and 2nd ($2) depends on sb sw $15, 100($2) # inde ($2) depends on sb Problem: write-back for sb won t occr ntil 5th cycle First assme seqence of independent instrctions Later remove this assmption Chapter 6: Pipelining Febrary 10,

16 CSE 322 COPUTER ARCHITECTURE II Control al Smmary Src Src Branch em emto EX/E E/WB ess Instrction emory 1 2 Inst[15-0] 1 2 etend control emory Inst[20-16] Inst[15-11] Dst Op em Chapter 6: Pipelining Febrary 10, CSE 322 COPUTER ARCHITECTURE II Qestions on Control als Following discssion relevant to a single instrction Qestion: Are all control signals active at same time? - Answer: No, different signals needed at different times (cycles) Qestion: Can we generate all these signals at same time? - Answer: Yes, bt... we cannot apply then at same time Chapter 6: Pipelining Febrary 10,

17 CSE 322 COPUTER ARCHITECTURE II Classifying Control Lines by Pipeline Stage Each flow component is active in only one pipeline stage. So, divide control signals into grops according to active component (see page for smmary charts) 1. Instrction Fetch always read instrction memory & write (nothing special to control) 2. Instrction Decode / ister Fetch still nothing special to control, same action every time 3. Eection: following control signals mst be decoded from instrction Dst: does target come from bits or Op: how to control operation Src: does 2nd inpt come from file or sign-etension literal. emory: likewise Branch: sed to generate Src Src: does get incremented or replaced by otpt of branch adder em: signal reads from memory em: signal writes to memory 5. Back: likewise emto: does vale going back to file come from or mem : is there in fact a ister write back to perform Chapter 6: Pipelining Febrary 10, CSE 322 COPUTER ARCHITECTURE II Passing Control with Pipeline Analogy: sending instrctions with a car on an assembly line Install Corinthian leather interior on car 6 when its at stage 3 strip off signals for eection phase WB strip off signals for memory phase Instrction Control Generation EX WB strip off signals for write-back phase WB Dst Op Src Branch em em emto EX/E E/WB Chapter 6: Pipelining Febrary 10,

18 CSE 322 COPUTER ARCHITECTURE II Pipelined path with Control als ed Src WB EX/E Control EX Op Src WB Branch em em E/WB WB emto ess Instrction emory 1 2 Inst[15-0] 1 2 etend Dst control emory Inst[20-16] Inst[15-11] Chapter 6: Pipelining Febrary 10,