Lecture 10: Pipelined Implementations

Transcription

1 U 8-7 S 9 L- 8-7 Lectre : Pipelined Implementations James. Hoe ept of EE, U Febrary 23, 29 nnoncements: Project is de this week idterm graded, d reslts posted Handots: H9 Homework 3 (on lackboard) Graded idterms idterm soltions with statstics U 8-7 S 9 L-2 oing landry more qickly: in theory 6 P place one dirty load of clothes in the washer when the washer is finished, place the wet load in the dryer when the dryer is finished, place the dry load on a table and fold when folding is finished, ask yor roommate (??) to pt the clothes away - ste to do a load are seqentially dependent - no dependence between different loads ased on figres from [P&H O&, OPYRIGHT 2 Elsevier. LL RIGHTS RESERVE.]

2 U 8-7 S 9 L-3 oing landry more qickly: in theory 6 P P loads of landry in parallel - no additional resorces -throghpt increased by - latency per load is the same ased on figres from [P&H O&, OPYRIGHT 2 Elsevier. LL RIGHTS RESERVE.] oing landry more qickly: in practice U 8-7 S 9 L- 6 P P ased on figres from [P&H O&, OPYRIGHT 2 Elsevier. LL RIGHTS RESERVE.] the slowest step decides throghpt

3 U 8-7 S 9 L-5 oing landry more qickly: in practice 6 P P Throghpt restored (2 loads per hor) sing 2 dryers ased on figres from [P&H O&, OPYRIGHT 2 Elsevier. LL RIGHTS RESERVE.] Pipeline Idealism U 8-7 S 9 L-6 otivation: Increase throghpt with little increase in hardware Repetition of identical operations The same operation is repeated on a large nmber of different inpts Repetition of independent operations No ing dependencies between repeated operations Uniformly partitionable sboperations an be evenly divided d d into niform-latency sboperations (that do not share resorces) Good eamples: atomobile assembly line, doing landry, bt instrction pipeline???

4 Ideal Pipelining U 8-7 S 9 L-7 combinational logic T ec W=~(/T) T/2 T/2 W=~(2/T) T/3 T/3 T/3 W=~(3/T) Performance odel Nonpipelined version with delay T W = /(T+S) where S = latch delay U 8-7 S 9 L-8 T k-stage pipelined version W k-stage = / (T/k +S ) W ma = / ( gate delay + S ) T/k T/k

5 ost odel Nonpipelined version with combinational cost G ost = G+L where L = latch cost U 8-7 S 9 L-9 G gates k-stage pipelined version ost k-stage = G + Lk k-stage G/k G/K ost/performance Trade-off [Peter. Kogge, 98] /P ost/performance: /P = [Lk + G] / [/(T/k + S)] = (Lk + G) (T/k + S) = LT + GS + LSk + GT/k Optimal ost/performance: find min. /P w.r.t. choice of k U 8-7 S 9 L- k d Lk + G = + + LS GT dk k 2 T -- + S k GT LS k 2 = k opt = GT LS

6 The Reality of Pipelining Eection.... U 8-7 S 9 L- [25 ] Shift Jmp address [3 ] left Src =Jmp + [3 28] [3 26] ontrol st Jmp ranch em emto Op em Src Shift left 2 reslt Src 2 =r Taken address [3 ] [25 2] [2 6] [5 ] register register 2 isters register 2 Zero reslt bcond ress [5 ] 6 32 Sign etend control [5 ] operation ased on figres from [P&H O&, OPYRIGHT 2 Elsevier. LL RIGHTS RESERVE.] T W=~(/T) RIS Processing U 8-7 S 9 L-2 5 generic ste instrction fetch instrction decode and operand fetch /eecte access (not reqired by non-mem instrctions) write-back IF ister # ress isters ister # I ister # ased on figres from [P&H O&, OPYRIGHT 2 Elsevier. LL RIGHTS RESERVE.] EX ress E

7 2 IF: fetch ividing into Stages 2 2 I: decode/ register file read EX: Eecte/ address calclation reslt E: emory access : back U 8-7 S 9 L-3 ignore ntil Lec 3 Shift left 2 ress register register 2 isters register 2 Zero reslt ress RF write 6 Sign etend 32 Is this the correct partitioning? Why not or 6 stages? Why not different bondaries ased on figres from [P&H O&, OPYRIGHT 2 Elsevier. LL RIGHTS RESERVE.] Pipelining U 8-7 S 9 L- Program eection (in instrctions) lw $, ($) fetch access lw $2, 2($) 8 8 ns fetch access lw $3, 3($) 8 8 ns fetch ns Program eection (in instrctions) lw $, ($) fetch access lw $2, 2($) 2 2 ns fetch access lw $3, 3($) 2 2 ns fetch access 2 2 ns 2 2 ns 2 2 ns 2 2 ns 2 2 ns 5-stage speedp is, not 5 as predicated by the ideal model ased on figres from [P&H O&, OPYRIGHT 2 Elsevier. LL RIGHTS RESERVE.]

8 Pipeline isters U 8-7 S 9 L-5 IF: fetch I: decode/ register file read EX: Eecte/ address calclation E: emory access : back No resorce is sed by more than stage! IF/I I/EX EX/E E/ + E + reslt reslt n Shift Shift left left 2 2 F ress ress IR E register register register 2 2 isters 2 2 register register Sign Sign etend etend E Imm E Zero Zero reslt reslt ot ress ress R W ot W T/k T T/k ased on figres from [P&H O&, OPYRIGHT 2 Elsevier. LL RIGHTS RESERVE.] Pipelined Operation U 8-7 S 9 L-6 lw fetch lw decode lw Eection lw emory lw back I/EX IF/I EX/E E/ Shift left left 2 reslt ress register register 2 isters 2 register 6 32 Sign etend Zero reslt ress ll instrction classes mst follow the same path and timing throgh the pipeline stages. ny performance impact? ased on figres from [P&H O&, OPYRIGHT 2 Elsevier. LL RIGHTS RESERVE.]

9 Pipelined Operation U 8-7 S 9 L-7 sb lw $, $, 2($) $2, $3 fetch sb lw $, $, 2($) $2, $3 decode lw $, 2($) Eection sb $, $2, $3 Eection sb lw $, $, 2($) $2, $3 emory sb lw $, $, 2($) $2, $3 back k IF/I I/EX EX/E E/ Shift left 2 reslt ress register register 2 isters g 2 register Zero reslt ress d 6 32 Sign etend lock lock lock 6 ased on figres from [P&H O&, OPYRIGHT 2 Elsevier. LL RIGHTS RESERVE.] Illstrating Pipeline Operation: Operation View U 8-7 S 9 L-8 t t t 2 t 3 t t 5 Inst IF I EX E Inst IF I EX E Inst 2 IF I EX E Inst 3 IF I EX Inst IF I IF E EX I IF E EX I IF

10 Illstrating Pipeline Operation: Resorce View U 8-7 S 9 L-9 t t t 2 t 3 t t 5 t 6 t 7 t 8 t 9 t IF I I I 2 I 3 I I 5 I 6 I 7 I 8 I 9 I I I I I 2 I 3 I I 5 I 6 I 7 I 8 I 9 EX I I I 2 I 3 I I 5 I 6 I 7 I 8 E I I I 2 I 3 I I 5 I 6 I 7 I I I 2 I 3 I I 5 I 6 ontrol Points U 8-7 S 9 L-2 Src IF/I I/EX EX/E E/ Shift left 2 reslt ranch ress register register 2 isters register 2 Src Zero reslt em ress emto [5 ] 6 32 Sign etend 6 control em ased on figres from [P&H O&, OPYRIGHT 2 Elsevier. LL RIGHTS RESERVE.] [2 6] [5 ] st Op Identical set of control points as the single-cycle path!!

11 Seqential ontrol: Special ase For a given instrction same control settings as single-cycle, bt control signals reqired at different cycles, depending on stage decode once sing the same logic as single-cycle and bffer control signals ntil consmed U 8-7 S 9 L-2 ontrol EX IF/I I/EX EX/E E/ or carry relevant instrction word/field down the pipeline and decode locally within each stage (still same logic) Src Pipelined ontrol U 8-7 S 9 L-22 ontrol I/EX EX/E E/ IF/I EX ress register register 2 isters register 2 Shift left 2 reslt Src Zero reslt ranch em ress emto [5 ] 6 32 Sign etend 6 control em ased on figres from [P&H O&, OPYRIGHT 2 Elsevier. LL RIGHTS RESERVE.] [2 6] [5 ] st Op

12 Pipeline Reality U 8-7 S 9 L-23 Identical operations... NOT! nifying instrction types - coalescing instrction types into one mlti-fnction pipe - eternal fragmentation (some idle stages) Uniform Sboperations... NOT! balance pipeline stages - stage qantization to yield balanced stages -internal fragmentation (some too-fast stages ) Independent operations... NOT! resolve and resorce hazards - dplicate contended resorces - inter-instrction dependency detection and resoltion IPS IS featres are engineered for improved pipelineability How to do better on idterm 2 U 8-7 S 9 L-2 the tet before lectre Pay attention in lectre o homework o lab sk qestions in lectre, lab, office hor Eat breakfast every morning on t rn with scissors..... o yo really need me to tell yo any of these?